1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright © 2009 Keith Packard 4 * 5 * Permission to use, copy, modify, distribute, and sell this software and its 6 * documentation for any purpose is hereby granted without fee, provided that 7 * the above copyright notice appear in all copies and that both that copyright 8 * notice and this permission notice appear in supporting documentation, and 9 * that the name of the copyright holders not be used in advertising or 10 * publicity pertaining to distribution of the software without specific, 11 * written prior permission. The copyright holders make no representations 12 * about the suitability of this software for any purpose. It is provided "as 13 * is" without express or implied warranty. 14 * 15 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 16 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 17 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 18 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 19 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 20 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 21 * OF THIS SOFTWARE. 22 */ 23 24 #include <common.h> 25 #include <drm/drm_dp_helper.h> 26 27 /** 28 * DOC: dp helpers 29 * 30 * These functions contain some common logic and helpers at various abstraction 31 * levels to deal with Display Port sink devices and related things like DP aux 32 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 33 * blocks, ... 34 */ 35 36 /* Helpers for DP link training */ 37 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 38 { 39 return link_status[r - DP_LANE0_1_STATUS]; 40 } 41 42 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], 43 int lane) 44 { 45 int i = DP_LANE0_1_STATUS + (lane >> 1); 46 int s = (lane & 1) * 4; 47 u8 l = dp_link_status(link_status, i); 48 49 return (l >> s) & 0xf; 50 } 51 52 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 53 int lane_count) 54 { 55 u8 lane_align; 56 u8 lane_status; 57 int lane; 58 59 lane_align = dp_link_status(link_status, 60 DP_LANE_ALIGN_STATUS_UPDATED); 61 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 62 return false; 63 for (lane = 0; lane < lane_count; lane++) { 64 lane_status = dp_get_lane_status(link_status, lane); 65 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 66 return false; 67 } 68 return true; 69 } 70 71 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 72 int lane_count) 73 { 74 int lane; 75 u8 lane_status; 76 77 for (lane = 0; lane < lane_count; lane++) { 78 lane_status = dp_get_lane_status(link_status, lane); 79 if ((lane_status & DP_LANE_CR_DONE) == 0) 80 return false; 81 } 82 return true; 83 } 84 85 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 86 int lane) 87 { 88 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 89 int s = ((lane & 1) ? 90 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 91 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 92 u8 l = dp_link_status(link_status, i); 93 94 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 95 } 96 97 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 98 int lane) 99 { 100 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 101 int s = ((lane & 1) ? 102 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 103 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 104 u8 l = dp_link_status(link_status, i); 105 106 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 107 } 108 109 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 110 { 111 int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 112 DP_TRAINING_AUX_RD_MASK; 113 114 if (rd_interval > 4) 115 printf("AUX interval %d, out of range (max 4)\n", rd_interval); 116 117 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 118 udelay(100); 119 else 120 mdelay(rd_interval * 4); 121 } 122 123 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 124 { 125 int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 126 DP_TRAINING_AUX_RD_MASK; 127 128 if (rd_interval > 4) 129 printf("AUX interval %d, out of range (max 4)\n", rd_interval); 130 131 if (rd_interval == 0) 132 udelay(400); 133 else 134 mdelay(rd_interval * 4); 135 } 136 137 u8 drm_dp_link_rate_to_bw_code(int link_rate) 138 { 139 switch (link_rate) { 140 default: 141 WARN(1, "unknown DP link rate %d, using %x\n", link_rate, 142 DP_LINK_BW_1_62); 143 case 162000: 144 return DP_LINK_BW_1_62; 145 case 270000: 146 return DP_LINK_BW_2_7; 147 case 540000: 148 return DP_LINK_BW_5_4; 149 case 810000: 150 return DP_LINK_BW_8_1; 151 } 152 } 153 154 int drm_dp_bw_code_to_link_rate(u8 link_bw) 155 { 156 switch (link_bw) { 157 default: 158 WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw); 159 case DP_LINK_BW_1_62: 160 return 162000; 161 case DP_LINK_BW_2_7: 162 return 270000; 163 case DP_LINK_BW_5_4: 164 return 540000; 165 case DP_LINK_BW_8_1: 166 return 810000; 167 } 168 } 169 170 #define AUX_RETRY_INTERVAL 500 /* us */ 171 172 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 173 unsigned int offset, void *buffer, size_t size) 174 { 175 struct drm_dp_aux_msg msg; 176 unsigned int retry, native_reply; 177 int err = 0, ret = 0; 178 179 memset(&msg, 0, sizeof(msg)); 180 msg.address = offset; 181 msg.request = request; 182 msg.buffer = buffer; 183 msg.size = size; 184 185 /* 186 * The specification doesn't give any recommendation on how often to 187 * retry native transactions. We used to retry 7 times like for 188 * aux i2c transactions but real world devices this wasn't 189 * sufficient, bump to 32 which makes Dell 4k monitors happier. 190 */ 191 for (retry = 0; retry < 32; retry++) { 192 if (ret != 0 && ret != -ETIMEDOUT) 193 udelay(AUX_RETRY_INTERVAL); 194 195 ret = aux->transfer(aux, &msg); 196 if (ret >= 0) { 197 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; 198 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { 199 if (ret == size) 200 goto out; 201 202 ret = -EPROTO; 203 } else { 204 ret = -EIO; 205 } 206 } 207 208 /* 209 * We want the error we return to be the error we received on 210 * the first transaction, since we may get a different error the 211 * next time we retry 212 */ 213 if (!err) 214 err = ret; 215 } 216 217 printf("%s: Too many retries, giving up. First error: %d\n", 218 aux->name, err); 219 ret = err; 220 221 out: 222 return ret; 223 } 224 225 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 226 void *buffer, size_t size) 227 { 228 int ret; 229 230 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, 231 buffer, 1); 232 if (ret != 1) 233 goto out; 234 235 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, 236 buffer, size); 237 238 out: 239 return ret; 240 } 241 242 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 243 void *buffer, size_t size) 244 { 245 int ret; 246 247 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, 248 buffer, size); 249 250 return ret; 251 } 252 253 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 254 u8 status[DP_LINK_STATUS_SIZE]) 255 { 256 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, 257 DP_LINK_STATUS_SIZE); 258 } 259 260 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, 261 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 262 { 263 u8 dpcd_ext[6]; 264 int ret; 265 266 /* 267 * Prior to DP1.3 the bit represented by 268 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. 269 * If it is set DP_DPCD_REV at 0000h could be at a value less than 270 * the true capability of the panel. The only way to check is to 271 * then compare 0000h and 2200h. 272 */ 273 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 274 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) 275 return 0; 276 277 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, 278 sizeof(dpcd_ext)); 279 if (ret < 0) 280 return ret; 281 if (ret != sizeof(dpcd_ext)) 282 return -EIO; 283 284 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { 285 printf("%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", 286 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); 287 return 0; 288 } 289 290 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) 291 return 0; 292 293 debug("%s: Base DPCD: %*ph\n", 294 aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 295 296 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); 297 298 return 0; 299 } 300 301 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 302 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 303 { 304 int ret; 305 306 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); 307 if (ret < 0) 308 return ret; 309 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) 310 return -EIO; 311 312 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); 313 if (ret < 0) 314 return ret; 315 316 debug("%s: DPCD: %*ph\n", 317 aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 318 319 return ret; 320 } 321 322 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) 323 { 324 /* 325 * In case of i2c defer or short i2c ack reply to a write, 326 * we need to switch to WRITE_STATUS_UPDATE to drain the 327 * rest of the message 328 */ 329 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { 330 msg->request &= DP_AUX_I2C_MOT; 331 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; 332 } 333 } 334 335 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 336 { 337 unsigned int retry, defer_i2c; 338 int ret; 339 /* 340 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device 341 * is required to retry at least seven times upon receiving AUX_DEFER 342 * before giving up the AUX transaction. 343 * 344 * We also try to account for the i2c bus speed. 345 */ 346 int max_retries = 7; 347 348 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); 349 retry++) { 350 ret = aux->transfer(aux, msg); 351 if (ret < 0) { 352 if (ret == -EBUSY) 353 continue; 354 355 /* 356 * While timeouts can be errors, they're usually normal 357 * behavior (for instance, when a driver tries to 358 * communicate with a non-existent DisplayPort device). 359 * Avoid spamming the kernel log with timeout errors. 360 */ 361 if (ret == -ETIMEDOUT) 362 printf("%s: transaction timed out\n", 363 aux->name); 364 else 365 printf("%s: transaction failed: %d\n", 366 aux->name, ret); 367 return ret; 368 } 369 370 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { 371 case DP_AUX_NATIVE_REPLY_ACK: 372 /* 373 * For I2C-over-AUX transactions this isn't enough, we 374 * need to check for the I2C ACK reply. 375 */ 376 break; 377 378 case DP_AUX_NATIVE_REPLY_NACK: 379 printf("%s: native nack (result=%d, size=%zu)\n", 380 aux->name, ret, msg->size); 381 return -EREMOTEIO; 382 383 case DP_AUX_NATIVE_REPLY_DEFER: 384 printf("%s: native defer\n", aux->name); 385 /* 386 * We could check for I2C bit rate capabilities and if 387 * available adjust this interval. We could also be 388 * more careful with DP-to-legacy adapters where a 389 * long legacy cable may force very low I2C bit rates. 390 * 391 * For now just defer for long enough to hopefully be 392 * safe for all use-cases. 393 */ 394 udelay(AUX_RETRY_INTERVAL); 395 continue; 396 397 default: 398 printf("%s: invalid native reply %#04x\n", 399 aux->name, msg->reply); 400 return -EREMOTEIO; 401 } 402 403 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { 404 case DP_AUX_I2C_REPLY_ACK: 405 /* 406 * Both native ACK and I2C ACK replies received. We 407 * can assume the transfer was successful. 408 */ 409 if (ret != msg->size) 410 drm_dp_i2c_msg_write_status_update(msg); 411 return ret; 412 413 case DP_AUX_I2C_REPLY_NACK: 414 printf("%s: I2C nack (result=%d, size=%zu)\n", 415 aux->name, ret, msg->size); 416 aux->i2c_nack_count++; 417 return -EREMOTEIO; 418 419 case DP_AUX_I2C_REPLY_DEFER: 420 printf("%s: I2C defer\n", aux->name); 421 /* DP Compliance Test 4.2.2.5 Requirement: 422 * Must have at least 7 retries for I2C defers on the 423 * transaction to pass this test 424 */ 425 aux->i2c_defer_count++; 426 if (defer_i2c < 7) 427 defer_i2c++; 428 udelay(AUX_RETRY_INTERVAL); 429 drm_dp_i2c_msg_write_status_update(msg); 430 431 continue; 432 433 default: 434 printf("%s: invalid I2C reply %#04x\n", 435 aux->name, msg->reply); 436 return -EREMOTEIO; 437 } 438 } 439 440 printf("%s: Too many retries, giving up\n", aux->name); 441 return -EREMOTEIO; 442 } 443 444 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, 445 const struct i2c_msg *i2c_msg) 446 { 447 msg->request = (i2c_msg->flags & I2C_M_RD) ? 448 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; 449 if (!(i2c_msg->flags & I2C_M_STOP)) 450 msg->request |= DP_AUX_I2C_MOT; 451 } 452 453 /* 454 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. 455 * 456 * Returns an error code on failure, or a recommended transfer size on success. 457 */ 458 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, 459 struct drm_dp_aux_msg *orig_msg) 460 { 461 int err, ret = orig_msg->size; 462 struct drm_dp_aux_msg msg = *orig_msg; 463 464 while (msg.size > 0) { 465 err = drm_dp_i2c_do_msg(aux, &msg); 466 if (err <= 0) 467 return err == 0 ? -EPROTO : err; 468 469 if (err < msg.size && err < ret) { 470 printf("%s: Reply: requested %zu bytes got %d bytes\n", 471 aux->name, msg.size, err); 472 ret = err; 473 } 474 475 msg.size -= err; 476 msg.buffer += err; 477 } 478 479 return ret; 480 } 481 482 int drm_dp_i2c_xfer(struct ddc_adapter *adapter, struct i2c_msg *msgs, 483 int num) 484 { 485 struct drm_dp_aux *aux = container_of(adapter, struct drm_dp_aux, ddc); 486 unsigned int i, j; 487 unsigned int transfer_size; 488 struct drm_dp_aux_msg msg; 489 int err = 0; 490 491 memset(&msg, 0, sizeof(msg)); 492 493 for (i = 0; i < num; i++) { 494 msg.address = msgs[i].addr; 495 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 496 /* Send a bare address packet to start the transaction. 497 * Zero sized messages specify an address only (bare 498 * address) transaction. 499 */ 500 msg.buffer = NULL; 501 msg.size = 0; 502 err = drm_dp_i2c_do_msg(aux, &msg); 503 504 /* 505 * Reset msg.request in case in case it got 506 * changed into a WRITE_STATUS_UPDATE. 507 */ 508 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 509 510 if (err < 0) 511 break; 512 /* We want each transaction to be as large as possible, but 513 * we'll go to smaller sizes if the hardware gives us a 514 * short reply. 515 */ 516 transfer_size = DP_AUX_MAX_PAYLOAD_BYTES; 517 for (j = 0; j < msgs[i].len; j += msg.size) { 518 msg.buffer = msgs[i].buf + j; 519 msg.size = min(transfer_size, msgs[i].len - j); 520 521 err = drm_dp_i2c_drain_msg(aux, &msg); 522 523 /* 524 * Reset msg.request in case in case it got 525 * changed into a WRITE_STATUS_UPDATE. 526 */ 527 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 528 529 if (err < 0) 530 break; 531 transfer_size = err; 532 } 533 if (err < 0) 534 break; 535 } 536 if (err >= 0) 537 err = num; 538 /* Send a bare address packet to close out the transaction. 539 * Zero sized messages specify an address only (bare 540 * address) transaction. 541 */ 542 msg.request &= ~DP_AUX_I2C_MOT; 543 msg.buffer = NULL; 544 msg.size = 0; 545 (void)drm_dp_i2c_do_msg(aux, &msg); 546 547 return err; 548 } 549 550