1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * maxim-max96755.c -- I2C register interface access for max96755 serdes chip 4 * 5 * Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd. 6 * 7 * Author: luowei <lw@rock-chips.com> 8 */ 9 10 #include "../core.h" 11 #include "maxim-max96755.h" 12 13 struct serdes_function_data { 14 u8 gpio_out_dis:1; 15 u8 gpio_tx_en:1; 16 u8 gpio_rx_en:1; 17 u8 gpio_tx_id; 18 u8 gpio_rx_id; 19 u16 mdelay; 20 }; 21 22 struct config_desc { 23 u16 reg; 24 u8 mask; 25 u8 val; 26 }; 27 28 struct serdes_group_data { 29 const struct config_desc *configs; 30 int num_configs; 31 }; 32 33 static int MAX96755_MFP0_pins[] = {0}; 34 static int MAX96755_MFP1_pins[] = {1}; 35 static int MAX96755_MFP2_pins[] = {2}; 36 static int MAX96755_MFP3_pins[] = {3}; 37 static int MAX96755_MFP4_pins[] = {4}; 38 static int MAX96755_MFP5_pins[] = {5}; 39 static int MAX96755_MFP6_pins[] = {6}; 40 static int MAX96755_MFP7_pins[] = {7}; 41 42 static int MAX96755_MFP8_pins[] = {8}; 43 static int MAX96755_MFP9_pins[] = {9}; 44 static int MAX96755_MFP10_pins[] = {10}; 45 static int MAX96755_MFP11_pins[] = {11}; 46 static int MAX96755_MFP12_pins[] = {12}; 47 static int MAX96755_MFP13_pins[] = {13}; 48 static int MAX96755_MFP14_pins[] = {14}; 49 static int MAX96755_MFP15_pins[] = {15}; 50 51 static int MAX96755_MFP16_pins[] = {16}; 52 static int MAX96755_MFP17_pins[] = {17}; 53 static int MAX96755_MFP18_pins[] = {18}; 54 static int MAX96755_MFP19_pins[] = {19}; 55 static int MAX96755_MFP20_pins[] = {20}; 56 static int MAX96755_I2C_pins[] = {19, 20}; 57 static int MAX96755_UART_pins[] = {19, 20}; 58 59 #define GROUP_DESC(nm) \ 60 { \ 61 .name = #nm, \ 62 .pins = nm ## _pins, \ 63 .num_pins = ARRAY_SIZE(nm ## _pins), \ 64 } 65 66 #define GROUP_DESC_CONFIG(nm) \ 67 { \ 68 .name = #nm, \ 69 .pins = nm ## _pins, \ 70 .num_pins = ARRAY_SIZE(nm ## _pins), \ 71 .data = (void *)(const struct serdes_group_data []) { \ 72 { \ 73 .configs = nm ## _configs, \ 74 .num_configs = ARRAY_SIZE(nm ## _configs), \ 75 } \ 76 }, \ 77 } 78 79 static const struct config_desc MAX96755_MFP0_configs[] = { 80 { 0x0005, LOCK_EN, 0 }, 81 { 0x0048, LOC_MS_EN, 0 }, 82 }; 83 84 static const struct config_desc MAX96755_MFP1_configs[] = { 85 { 0x0005, ERRB_EN, 0 }, 86 }; 87 88 static const struct config_desc MAX96755_MFP4_configs[] = { 89 { 0x070, SPI_EN, 0 }, 90 }; 91 92 static const struct config_desc MAX96755_MFP5_configs[] = { 93 { 0x006, RCLKEN, 0 }, 94 }; 95 96 static const struct config_desc MAX96755_MFP7_configs[] = { 97 { 0x0002, AUD_TX_EN_X, 0 }, 98 { 0x0002, AUD_TX_EN_Y, 0 } 99 }; 100 101 static const struct config_desc MAX96755_MFP8_configs[] = { 102 { 0x0002, AUD_TX_EN_X, 0 }, 103 { 0x0002, AUD_TX_EN_Y, 0 } 104 }; 105 106 static const struct config_desc MAX96755_MFP9_configs[] = { 107 { 0x0002, AUD_TX_EN_X, 0 }, 108 { 0x0002, AUD_TX_EN_Y, 0 } 109 }; 110 111 static const struct config_desc MAX96755_MFP10_configs[] = { 112 { 0x0001, IIC_2_EN, 0 }, 113 { 0x0003, UART_2_EN, 0 }, 114 { 0x0140, AUD_RX_EN, 0 }, 115 }; 116 117 static const struct config_desc MAX96755_MFP11_configs[] = { 118 { 0x0001, IIC_2_EN, 0 }, 119 { 0x0003, UART_2_EN, 0 }, 120 { 0x0140, AUD_RX_EN, 0 }, 121 }; 122 123 static const struct config_desc MAX96755_MFP12_configs[] = { 124 { 0x0140, AUD_RX_EN, 0 }, 125 }; 126 127 static const struct config_desc MAX96755_MFP13_configs[] = { 128 { 0x0005, PU_LF0, 0 }, 129 }; 130 131 static const struct config_desc MAX96755_MFP14_configs[] = { 132 { 0x0005, PU_LF1, 0 }, 133 }; 134 135 static const struct config_desc MAX96755_MFP15_configs[] = { 136 { 0x0005, PU_LF2, 0 }, 137 }; 138 139 static const struct config_desc MAX96755_MFP16_configs[] = { 140 { 0x0005, PU_LF3, 0 }, 141 }; 142 143 static const struct config_desc MAX96755_MFP17_configs[] = { 144 { 0x0001, IIC_1_EN, 0 }, 145 { 0x0003, UART_1_EN, 0 }, 146 }; 147 148 static const struct config_desc MAX96755_MFP18_configs[] = { 149 { 0x0001, IIC_1_EN, 0 }, 150 { 0x0003, UART_1_EN, 0 }, 151 }; 152 153 static const char *serdes_gpio_groups[] = { 154 "MAX96755_MFP0", "MAX96755_MFP1", "MAX96755_MFP2", "MAX96755_MFP3", 155 "MAX96755_MFP4", "MAX96755_MFP5", "MAX96755_MFP6", "MAX96755_MFP7", 156 157 "MAX96755_MFP8", "MAX96755_MFP9", "MAX96755_MFP10", "MAX96755_MFP11", 158 "MAX96755_MFP12", "MAX96755_MFP13", "MAX96755_MFP14", "MAX96755_MFP15", 159 160 "MAX96755_MFP16", "MAX96755_MFP17", "MAX96755_MFP18", "MAX96755_MFP19", 161 "MAX96755_MFP20", 162 }; 163 164 static const char *MAX96755_I2C_groups[] = { "MAX96755_I2C" }; 165 static const char *MAX96755_UART_groups[] = { "MAX96755_UART" }; 166 167 #define FUNCTION_DESC(nm) \ 168 { \ 169 .name = #nm, \ 170 .group_names = nm##_groups, \ 171 .num_group_names = ARRAY_SIZE(nm##_groups), \ 172 } \ 173 174 #define FUNCTION_DESC_GPIO_INPUT(id) \ 175 { \ 176 .name = "DES_RXID"#id"_TO_SER", \ 177 .group_names = serdes_gpio_groups, \ 178 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \ 179 .data = (void *)(const struct serdes_function_data []) { \ 180 { .gpio_out_dis = 0, .gpio_rx_en = 1, .gpio_rx_id = id } \ 181 }, \ 182 } \ 183 184 #define FUNCTION_DESC_GPIO_OUTPUT(id) \ 185 { \ 186 .name = "SER_TXID"#id"_TO_DES", \ 187 .group_names = serdes_gpio_groups, \ 188 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \ 189 .data = (void *)(const struct serdes_function_data []) { \ 190 { .gpio_out_dis = 1, .gpio_tx_en = 1, .gpio_tx_id = id } \ 191 }, \ 192 } \ 193 194 static struct pinctrl_pin_desc max96755_pins_desc[] = { 195 PINCTRL_PIN(MAXIM_MAX96755_MFP0, "MAX96755_MFP0"), 196 PINCTRL_PIN(MAXIM_MAX96755_MFP1, "MAX96755_MFP1"), 197 PINCTRL_PIN(MAXIM_MAX96755_MFP2, "MAX96755_MFP2"), 198 PINCTRL_PIN(MAXIM_MAX96755_MFP3, "MAX96755_MFP3"), 199 PINCTRL_PIN(MAXIM_MAX96755_MFP4, "MAX96755_MFP4"), 200 PINCTRL_PIN(MAXIM_MAX96755_MFP5, "MAX96755_MFP5"), 201 PINCTRL_PIN(MAXIM_MAX96755_MFP6, "MAX96755_MFP6"), 202 PINCTRL_PIN(MAXIM_MAX96755_MFP7, "MAX96755_MFP7"), 203 204 PINCTRL_PIN(MAXIM_MAX96755_MFP8, "MAX96755_MFP8"), 205 PINCTRL_PIN(MAXIM_MAX96755_MFP9, "MAX96755_MFP9"), 206 PINCTRL_PIN(MAXIM_MAX96755_MFP10, "MAX96755_MFP10"), 207 PINCTRL_PIN(MAXIM_MAX96755_MFP11, "MAX96755_MFP11"), 208 PINCTRL_PIN(MAXIM_MAX96755_MFP12, "MAX96755_MFP12"), 209 PINCTRL_PIN(MAXIM_MAX96755_MFP13, "MAX96755_MFP13"), 210 PINCTRL_PIN(MAXIM_MAX96755_MFP14, "MAX96755_MFP14"), 211 PINCTRL_PIN(MAXIM_MAX96755_MFP15, "MAX96755_MFP15"), 212 213 PINCTRL_PIN(MAXIM_MAX96755_MFP16, "MAX96755_MFP16"), 214 PINCTRL_PIN(MAXIM_MAX96755_MFP17, "MAX96755_MFP17"), 215 PINCTRL_PIN(MAXIM_MAX96755_MFP18, "MAX96755_MFP18"), 216 PINCTRL_PIN(MAXIM_MAX96755_MFP19, "MAX96755_MFP19"), 217 PINCTRL_PIN(MAXIM_MAX96755_MFP20, "MAX96755_MFP20"), 218 }; 219 220 static struct group_desc max96755_groups_desc[] = { 221 GROUP_DESC_CONFIG(MAX96755_MFP0), 222 GROUP_DESC_CONFIG(MAX96755_MFP1), 223 GROUP_DESC(MAX96755_MFP2), 224 GROUP_DESC(MAX96755_MFP3), 225 GROUP_DESC_CONFIG(MAX96755_MFP4), 226 GROUP_DESC_CONFIG(MAX96755_MFP5), 227 GROUP_DESC(MAX96755_MFP6), 228 GROUP_DESC_CONFIG(MAX96755_MFP7), 229 230 GROUP_DESC_CONFIG(MAX96755_MFP8), 231 GROUP_DESC_CONFIG(MAX96755_MFP9), 232 GROUP_DESC_CONFIG(MAX96755_MFP10), 233 GROUP_DESC_CONFIG(MAX96755_MFP11), 234 GROUP_DESC_CONFIG(MAX96755_MFP12), 235 GROUP_DESC_CONFIG(MAX96755_MFP13), 236 GROUP_DESC_CONFIG(MAX96755_MFP14), 237 GROUP_DESC_CONFIG(MAX96755_MFP15), 238 239 GROUP_DESC_CONFIG(MAX96755_MFP16), 240 GROUP_DESC_CONFIG(MAX96755_MFP17), 241 GROUP_DESC_CONFIG(MAX96755_MFP18), 242 GROUP_DESC(MAX96755_MFP19), 243 GROUP_DESC(MAX96755_MFP20), 244 GROUP_DESC(MAX96755_I2C), 245 GROUP_DESC(MAX96755_UART), 246 }; 247 248 static struct function_desc max96755_functions_desc[] = { 249 FUNCTION_DESC_GPIO_INPUT(0), 250 FUNCTION_DESC_GPIO_INPUT(1), 251 FUNCTION_DESC_GPIO_INPUT(2), 252 FUNCTION_DESC_GPIO_INPUT(3), 253 FUNCTION_DESC_GPIO_INPUT(4), 254 FUNCTION_DESC_GPIO_INPUT(5), 255 FUNCTION_DESC_GPIO_INPUT(6), 256 FUNCTION_DESC_GPIO_INPUT(7), 257 258 FUNCTION_DESC_GPIO_INPUT(8), 259 FUNCTION_DESC_GPIO_INPUT(9), 260 FUNCTION_DESC_GPIO_INPUT(10), 261 FUNCTION_DESC_GPIO_INPUT(11), 262 FUNCTION_DESC_GPIO_INPUT(12), 263 FUNCTION_DESC_GPIO_INPUT(13), 264 FUNCTION_DESC_GPIO_INPUT(14), 265 FUNCTION_DESC_GPIO_INPUT(15), 266 267 FUNCTION_DESC_GPIO_INPUT(16), 268 FUNCTION_DESC_GPIO_INPUT(17), 269 FUNCTION_DESC_GPIO_INPUT(18), 270 FUNCTION_DESC_GPIO_INPUT(19), 271 FUNCTION_DESC_GPIO_INPUT(20), 272 273 FUNCTION_DESC_GPIO_OUTPUT(0), 274 FUNCTION_DESC_GPIO_OUTPUT(1), 275 FUNCTION_DESC_GPIO_OUTPUT(2), 276 FUNCTION_DESC_GPIO_OUTPUT(3), 277 FUNCTION_DESC_GPIO_OUTPUT(4), 278 FUNCTION_DESC_GPIO_OUTPUT(5), 279 FUNCTION_DESC_GPIO_OUTPUT(6), 280 FUNCTION_DESC_GPIO_OUTPUT(7), 281 282 FUNCTION_DESC_GPIO_OUTPUT(8), 283 FUNCTION_DESC_GPIO_OUTPUT(9), 284 FUNCTION_DESC_GPIO_OUTPUT(10), 285 FUNCTION_DESC_GPIO_OUTPUT(11), 286 FUNCTION_DESC_GPIO_OUTPUT(12), 287 FUNCTION_DESC_GPIO_OUTPUT(13), 288 FUNCTION_DESC_GPIO_OUTPUT(14), 289 FUNCTION_DESC_GPIO_OUTPUT(15), 290 291 FUNCTION_DESC_GPIO_OUTPUT(16), 292 FUNCTION_DESC_GPIO_OUTPUT(17), 293 FUNCTION_DESC_GPIO_OUTPUT(18), 294 FUNCTION_DESC_GPIO_OUTPUT(19), 295 FUNCTION_DESC_GPIO_OUTPUT(20), 296 297 FUNCTION_DESC(MAX96755_I2C), 298 FUNCTION_DESC(MAX96755_UART), 299 }; 300 301 static struct serdes_chip_pinctrl_info max96755_pinctrl_info = { 302 .pins = max96755_pins_desc, 303 .num_pins = ARRAY_SIZE(max96755_pins_desc), 304 .groups = max96755_groups_desc, 305 .num_groups = ARRAY_SIZE(max96755_groups_desc), 306 .functions = max96755_functions_desc, 307 .num_functions = ARRAY_SIZE(max96755_functions_desc), 308 }; 309 310 static bool max96755_bridge_linka_locked(struct serdes *serdes) 311 { 312 u32 val; 313 314 if (dm_gpio_is_valid(&serdes->lock_gpio)) { 315 val = dm_gpio_get_value(&serdes->lock_gpio); 316 SERDES_DBG_CHIP("serdes %s:val=%d\n", __func__, val); 317 return val; 318 } 319 320 if (serdes_reg_read(serdes, 0x0013, &val)) { 321 SERDES_DBG_CHIP("serdes %s: false val=%d\n", __func__, val); 322 return false; 323 } 324 325 if (!FIELD_GET(LOCKED, val)) { 326 SERDES_DBG_CHIP("serdes %s: false val=%d\n", __func__, val); 327 return false; 328 } 329 330 return true; 331 } 332 333 static bool max96755_bridge_linkb_locked(struct serdes *serdes) 334 { 335 u32 val; 336 337 if (dm_gpio_is_valid(&serdes->lock_gpio)) { 338 val = dm_gpio_get_value(&serdes->lock_gpio); 339 SERDES_DBG_CHIP("serdes %s:val=%d\n", __func__, val); 340 return val; 341 } 342 343 if (serdes_reg_read(serdes, 0x0013, &val)) { 344 SERDES_DBG_CHIP("serdes %s: false val=%d\n", __func__, val); 345 return false; 346 } 347 348 if (!FIELD_GET(LOCKED, val)) { 349 SERDES_DBG_CHIP("serdes %s: false val=%d\n", __func__, val); 350 return false; 351 } 352 353 return true; 354 } 355 356 static bool max96755_bridge_detect(struct serdes *serdes, int link) 357 { 358 if (link == LINKA) 359 return max96755_bridge_linka_locked(serdes); 360 else 361 return max96755_bridge_linkb_locked(serdes); 362 } 363 364 static int max96755_bridge_enable(struct serdes *serdes) 365 { 366 int ret = 0; 367 368 SERDES_DBG_CHIP("%s: serdes chip %s ret=%d\n", 369 __func__, serdes->chip_data->name, ret); 370 return ret; 371 } 372 373 static int max96755_bridge_disable(struct serdes *serdes) 374 { 375 int ret = 0; 376 377 ret = serdes_set_bits(serdes, 0x0002, VID_TX_EN_X, 378 FIELD_PREP(VID_TX_EN_X, 0)); 379 380 return ret; 381 } 382 383 static struct serdes_chip_bridge_ops max96755_bridge_ops = { 384 .detect = max96755_bridge_detect, 385 .enable = max96755_bridge_enable, 386 .disable = max96755_bridge_disable, 387 }; 388 389 static int max96755_pinctrl_set_pin_mux(struct serdes *serdes, 390 unsigned int pin_selector, 391 unsigned int func_selector) 392 { 393 struct function_desc *func; 394 struct pinctrl_pin_desc *pin; 395 int offset; 396 u16 ms; 397 398 func = &serdes->chip_data->pinctrl_info->functions[func_selector]; 399 if (!func) { 400 printf("%s: func is null\n", __func__); 401 return -EINVAL; 402 } 403 404 pin = &serdes->chip_data->pinctrl_info->pins[pin_selector]; 405 if (!pin) { 406 printf("%s: pin is null\n", __func__); 407 return -EINVAL; 408 } 409 410 SERDES_DBG_CHIP("%s: serdes %s func=%s data=%p pin=%s num=%d\n", 411 __func__, serdes->dev->name, 412 func->name, func->data, 413 pin->name, pin->number); 414 415 if (func->data) { 416 struct serdes_function_data *fdata = func->data; 417 418 ms = fdata->mdelay; 419 offset = pin->number; 420 if (offset > 32) 421 dev_err(serdes->dev, "%s offset=%d > 32\n", 422 serdes->dev->name, offset); 423 else 424 SERDES_DBG_CHIP("%s: serdes %s txid=%d rxid=%d off=%d\n", 425 __func__, serdes->dev->name, 426 fdata->gpio_tx_id, fdata->gpio_rx_id, offset); 427 428 if (!ms) { 429 serdes_set_bits(serdes, GPIO_A_REG(offset), 430 GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN, 431 FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) | 432 FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) | 433 FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en)); 434 435 if (fdata->gpio_tx_en) 436 serdes_set_bits(serdes, 437 GPIO_B_REG(offset), 438 GPIO_TX_ID, 439 FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id)); 440 if (fdata->gpio_rx_en) 441 serdes_set_bits(serdes, 442 GPIO_C_REG(offset), 443 GPIO_RX_ID, 444 FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id)); 445 } else { 446 mdelay(ms); 447 SERDES_DBG_CHIP("%s: delay %dms\n", __func__, ms); 448 } 449 } 450 451 return 0; 452 } 453 454 static int max96755_pinctrl_set_grp_mux(struct serdes *serdes, 455 unsigned int group_selector, 456 unsigned int func_selector) 457 { 458 struct serdes_pinctrl *pinctrl = serdes->serdes_pinctrl; 459 struct function_desc *func; 460 struct group_desc *grp; 461 int i, offset; 462 u16 ms; 463 464 func = &serdes->chip_data->pinctrl_info->functions[func_selector]; 465 if (!func) { 466 printf("%s: func is null\n", __func__); 467 return -EINVAL; 468 } 469 470 grp = &serdes->chip_data->pinctrl_info->groups[group_selector]; 471 if (!grp) { 472 printf("%s: grp is null\n", __func__); 473 return -EINVAL; 474 } 475 476 SERDES_DBG_CHIP("%s: serdes %s func=%s data=%p grp=%s data=%p, num=%d\n", 477 __func__, serdes->chip_data->name, func->name, 478 func->data, grp->name, grp->data, grp->num_pins); 479 480 if (func->data) { 481 struct serdes_function_data *fdata = func->data; 482 483 ms = fdata->mdelay; 484 for (i = 0; i < grp->num_pins; i++) { 485 offset = grp->pins[i] - pinctrl->pin_base; 486 if (offset > 32) 487 dev_err(serdes->dev, "%s offset=%d > 32\n", 488 serdes->dev->name, offset); 489 else 490 SERDES_DBG_CHIP("%s: serdes %s txid=%d rxid=%d off=%d\n", 491 __func__, serdes->dev->name, 492 fdata->gpio_tx_id, fdata->gpio_rx_id, offset); 493 494 if (!ms) { 495 serdes_set_bits(serdes, GPIO_A_REG(offset), 496 GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN, 497 FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) | 498 FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) | 499 FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en)); 500 if (fdata->gpio_tx_en) 501 serdes_set_bits(serdes, 502 GPIO_B_REG(offset), 503 GPIO_TX_ID, 504 FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id)); 505 if (fdata->gpio_rx_en) 506 serdes_set_bits(serdes, 507 GPIO_C_REG(offset), 508 GPIO_RX_ID, 509 FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id)); 510 } else { 511 mdelay(ms); 512 SERDES_DBG_CHIP("%s: delay %dms\n", __func__, ms); 513 } 514 } 515 } 516 517 if (grp->data) { 518 struct serdes_group_data *gdata = grp->data; 519 520 for (i = 0; i < gdata->num_configs; i++) { 521 const struct config_desc *config = &gdata->configs[i]; 522 serdes_set_bits(serdes, config->reg, 523 config->mask, config->val); 524 } 525 } 526 527 return 0; 528 } 529 530 static int max96755_pinctrl_config_set(struct serdes *serdes, 531 unsigned int pin_selector, 532 unsigned int param, unsigned int argument) 533 { 534 u8 res_cfg; 535 536 switch (param) { 537 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 538 serdes_set_bits(serdes, GPIO_B_REG(pin_selector), 539 OUT_TYPE, FIELD_PREP(OUT_TYPE, 0)); 540 break; 541 case PIN_CONFIG_DRIVE_PUSH_PULL: 542 serdes_set_bits(serdes, GPIO_B_REG(pin_selector), 543 OUT_TYPE, FIELD_PREP(OUT_TYPE, 1)); 544 break; 545 case PIN_CONFIG_BIAS_DISABLE: 546 serdes_set_bits(serdes, GPIO_C_REG(pin_selector), 547 PULL_UPDN_SEL, 548 FIELD_PREP(PULL_UPDN_SEL, 0)); 549 break; 550 case PIN_CONFIG_BIAS_PULL_UP: 551 switch (argument) { 552 case 40000: 553 res_cfg = 0; 554 break; 555 case 1000000: 556 res_cfg = 1; 557 break; 558 default: 559 return -EINVAL; 560 } 561 562 serdes_set_bits(serdes, GPIO_A_REG(pin_selector), 563 RES_CFG, FIELD_PREP(RES_CFG, res_cfg)); 564 serdes_set_bits(serdes, GPIO_C_REG(pin_selector), 565 PULL_UPDN_SEL, 566 FIELD_PREP(PULL_UPDN_SEL, 1)); 567 break; 568 case PIN_CONFIG_BIAS_PULL_DOWN: 569 switch (argument) { 570 case 40000: 571 res_cfg = 0; 572 break; 573 case 1000000: 574 res_cfg = 1; 575 break; 576 default: 577 return -EINVAL; 578 } 579 580 serdes_set_bits(serdes, GPIO_A_REG(pin_selector), 581 RES_CFG, FIELD_PREP(RES_CFG, res_cfg)); 582 serdes_set_bits(serdes, GPIO_C_REG(pin_selector), 583 PULL_UPDN_SEL, 584 FIELD_PREP(PULL_UPDN_SEL, 2)); 585 break; 586 case PIN_CONFIG_OUTPUT: 587 serdes_set_bits(serdes, GPIO_A_REG(pin_selector), 588 GPIO_OUT_DIS | GPIO_OUT, 589 FIELD_PREP(GPIO_OUT_DIS, 0) | 590 FIELD_PREP(GPIO_OUT, argument)); 591 break; 592 default: 593 return -EOPNOTSUPP; 594 } 595 596 return 0; 597 } 598 599 static struct serdes_chip_pinctrl_ops max96755_pinctrl_ops = { 600 .pinconf_set = max96755_pinctrl_config_set, 601 .pinmux_set = max96755_pinctrl_set_pin_mux, 602 .pinmux_group_set = max96755_pinctrl_set_grp_mux, 603 }; 604 605 static int max96755_gpio_direction_input(struct serdes *serdes, int gpio) 606 { 607 return 0; 608 } 609 610 static int max96755_gpio_direction_output(struct serdes *serdes, 611 int gpio, int value) 612 { 613 return 0; 614 } 615 616 static int max96755_gpio_get_level(struct serdes *serdes, int gpio) 617 { 618 return 0; 619 } 620 621 static int max96755_gpio_set_level(struct serdes *serdes, int gpio, int value) 622 { 623 return 0; 624 } 625 626 static int max96755_gpio_set_config(struct serdes *serdes, 627 int gpio, unsigned long config) 628 { 629 return 0; 630 } 631 632 static int max96755_gpio_to_irq(struct serdes *serdes, int gpio) 633 { 634 return 0; 635 } 636 637 static struct serdes_chip_gpio_ops max96755_gpio_ops = { 638 .direction_input = max96755_gpio_direction_input, 639 .direction_output = max96755_gpio_direction_output, 640 .get_level = max96755_gpio_get_level, 641 .set_level = max96755_gpio_set_level, 642 .set_config = max96755_gpio_set_config, 643 .to_irq = max96755_gpio_to_irq, 644 }; 645 646 static int max96755_select(struct serdes *serdes, int chan) 647 { 648 u32 link_cfg; 649 int ret = 0; 650 651 serdes_set_bits(serdes, 0x0001, DIS_REM_CC, 652 FIELD_PREP(DIS_REM_CC, 0)); 653 654 serdes_reg_read(serdes, 0x0010, &link_cfg); 655 if ((link_cfg & LINK_CFG) == SPLITTER_MODE) 656 SERDES_DBG_CHIP("%s: serdes %s is split mode cfg=0x%x\n", 657 __func__, 658 serdes->chip_data->name, link_cfg); 659 660 if (chan == 0 && (link_cfg & LINK_CFG) != DUAL_LINK) { 661 ret = serdes_set_bits(serdes, 0x0004, 662 LINK_EN_B | LINK_EN_A, 663 FIELD_PREP(LINK_EN_A, 1) | 664 FIELD_PREP(LINK_EN_B, 1)); 665 ret = serdes_set_bits(serdes, 0x0010, 666 RESET_ONESHOT | AUTO_LINK | LINK_CFG, 667 FIELD_PREP(RESET_ONESHOT, 1) | 668 FIELD_PREP(AUTO_LINK, 0) | 669 FIELD_PREP(LINK_CFG, DUAL_LINK)); 670 SERDES_DBG_CHIP("%s: change to use dual link\n", __func__); 671 } else if (chan == 1 && (link_cfg & LINK_CFG) != LINKA) { 672 ret = serdes_set_bits(serdes, 0x0004, 673 LINK_EN_B | LINK_EN_A, 674 FIELD_PREP(LINK_EN_A, 1) | 675 FIELD_PREP(LINK_EN_B, 0)); 676 ret = serdes_set_bits(serdes, 0x0010, 677 RESET_ONESHOT | AUTO_LINK | LINK_CFG, 678 FIELD_PREP(RESET_ONESHOT, 1) | 679 FIELD_PREP(AUTO_LINK, 0) | 680 FIELD_PREP(LINK_CFG, LINKA)); 681 SERDES_DBG_CHIP("%s: change to use linkA\n", __func__); 682 } else if (chan == 2 && (link_cfg & LINK_CFG) != LINKB) { 683 ret = serdes_set_bits(serdes, 0x0004, 684 LINK_EN_B | LINK_EN_A, 685 FIELD_PREP(LINK_EN_A, 0) | 686 FIELD_PREP(LINK_EN_B, 1)); 687 ret = serdes_set_bits(serdes, 0x0010, 688 RESET_ONESHOT | AUTO_LINK | LINK_CFG, 689 FIELD_PREP(RESET_ONESHOT, 1) | 690 FIELD_PREP(AUTO_LINK, 0) | 691 FIELD_PREP(LINK_CFG, LINKB)); 692 SERDES_DBG_CHIP("%s: change to use linkB\n", __func__); 693 } else if (chan == 3 && (link_cfg & LINK_CFG) != SPLITTER_MODE) { 694 ret = serdes_set_bits(serdes, 0x0004, 695 LINK_EN_B | LINK_EN_A, 696 FIELD_PREP(LINK_EN_A, 1) | 697 FIELD_PREP(LINK_EN_B, 1)); 698 ret = serdes_set_bits(serdes, 0x0010, 699 RESET_ONESHOT | AUTO_LINK | LINK_CFG, 700 FIELD_PREP(RESET_ONESHOT, 1) | 701 FIELD_PREP(AUTO_LINK, 0) | 702 FIELD_PREP(LINK_CFG, SPLITTER_MODE)); 703 SERDES_DBG_CHIP("%s: change to use split mode\n", __func__); 704 } 705 706 return ret; 707 } 708 709 static int max96755_deselect(struct serdes *serdes, int chan) 710 { 711 //serdes_set_bits(serdes, 0x0001, DIS_REM_CC, 712 // FIELD_PREP(DIS_REM_CC, 1)); 713 714 return 0; 715 } 716 717 static struct serdes_chip_split_ops max96755_split_ops = { 718 .select = max96755_select, 719 .deselect = max96755_deselect, 720 }; 721 722 struct serdes_chip_data serdes_max96755_data = { 723 .name = "max96755", 724 .serdes_type = TYPE_SER, 725 .serdes_id = MAXIM_ID_MAX96755, 726 .connector_type = DRM_MODE_CONNECTOR_DSI, 727 .pinctrl_info = &max96755_pinctrl_info, 728 .bridge_ops = &max96755_bridge_ops, 729 .pinctrl_ops = &max96755_pinctrl_ops, 730 .gpio_ops = &max96755_gpio_ops, 731 .split_ops = &max96755_split_ops, 732 }; 733 EXPORT_SYMBOL_GPL(serdes_max96755_data); 734 735 MODULE_LICENSE("GPL"); 736