1 /* 2 * Driver for AT91/AT32 MULTI LAYER LCD Controller 3 * 4 * Copyright (C) 2012 Atmel Corporation 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 #include <asm/arch/gpio.h> 28 #include <asm/arch/clk.h> 29 #include <lcd.h> 30 #include <atmel_hlcdc.h> 31 32 int lcd_line_length; 33 34 void *lcd_base; /* Start of framebuffer memory */ 35 void *lcd_console_address; /* Start of console buffer */ 36 37 short console_col; 38 short console_row; 39 40 /* configurable parameters */ 41 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 42 #define ATMEL_LCDC_DMA_BURST_LEN 8 43 #ifndef ATMEL_LCDC_GUARD_TIME 44 #define ATMEL_LCDC_GUARD_TIME 1 45 #endif 46 47 #define ATMEL_LCDC_FIFO_SIZE 512 48 49 #define lcdc_readl(reg) __raw_readl((reg)) 50 #define lcdc_writel(reg, val) __raw_writel((val), (reg)) 51 52 /* 53 * the CLUT register map as following 54 * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0) 55 */ 56 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) 57 { 58 lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) 59 | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) 60 | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk), 61 panel_info.mmio + ATMEL_LCDC_LUT(regno)); 62 } 63 64 void lcd_ctrl_init(void *lcdbase) 65 { 66 unsigned long value; 67 struct lcd_dma_desc *desc; 68 struct atmel_hlcd_regs *regs; 69 70 if (!has_lcdc()) 71 return; /* No lcdc */ 72 73 regs = (struct atmel_hlcd_regs *)panel_info.mmio; 74 75 /* Disable DISP signal */ 76 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); 77 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) 78 udelay(1); 79 /* Disable synchronization */ 80 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS); 81 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) 82 udelay(1); 83 /* Disable pixel clock */ 84 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS); 85 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) 86 udelay(1); 87 /* Disable PWM */ 88 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS); 89 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) 90 udelay(1); 91 92 /* Set pixel clock */ 93 value = get_lcdc_clk_rate(0) / panel_info.vl_clk; 94 if (get_lcdc_clk_rate(0) % panel_info.vl_clk) 95 value++; 96 97 if (value < 1) { 98 /* Using system clock as pixel clock */ 99 lcdc_writel(®s->lcdc_lcdcfg0, 100 LCDC_LCDCFG0_CLKDIV(0) 101 | LCDC_LCDCFG0_CGDISHCR 102 | LCDC_LCDCFG0_CGDISHEO 103 | LCDC_LCDCFG0_CGDISOVR1 104 | LCDC_LCDCFG0_CGDISBASE 105 | panel_info.vl_clk_pol 106 | LCDC_LCDCFG0_CLKSEL); 107 108 } else { 109 lcdc_writel(®s->lcdc_lcdcfg0, 110 LCDC_LCDCFG0_CLKDIV(value - 2) 111 | LCDC_LCDCFG0_CGDISHCR 112 | LCDC_LCDCFG0_CGDISHEO 113 | LCDC_LCDCFG0_CGDISOVR1 114 | LCDC_LCDCFG0_CGDISBASE 115 | panel_info.vl_clk_pol); 116 } 117 118 /* Initialize control register 5 */ 119 value = 0; 120 121 value |= panel_info.vl_sync; 122 123 #ifndef LCD_OUTPUT_BPP 124 /* Output is 24bpp */ 125 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; 126 #else 127 switch (LCD_OUTPUT_BPP) { 128 case 12: 129 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP; 130 break; 131 case 16: 132 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP; 133 break; 134 case 18: 135 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP; 136 break; 137 case 24: 138 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; 139 break; 140 default: 141 BUG(); 142 break; 143 } 144 #endif 145 146 value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME); 147 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); 148 lcdc_writel(®s->lcdc_lcdcfg5, value); 149 150 /* Vertical & Horizontal Timing */ 151 value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1); 152 value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); 153 lcdc_writel(®s->lcdc_lcdcfg1, value); 154 155 value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); 156 value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); 157 lcdc_writel(®s->lcdc_lcdcfg2, value); 158 159 value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); 160 value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); 161 lcdc_writel(®s->lcdc_lcdcfg3, value); 162 163 /* Display size */ 164 value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1); 165 value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1); 166 lcdc_writel(®s->lcdc_lcdcfg4, value); 167 168 lcdc_writel(®s->lcdc_basecfg0, 169 LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO); 170 171 switch (NBITS(panel_info.vl_bpix)) { 172 case 16: 173 lcdc_writel(®s->lcdc_basecfg1, 174 LCDC_BASECFG1_RGBMODE_16BPP_RGB_565); 175 break; 176 default: 177 BUG(); 178 break; 179 } 180 181 lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0)); 182 lcdc_writel(®s->lcdc_basecfg3, 0); 183 lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA); 184 185 /* Disable all interrupts */ 186 lcdc_writel(®s->lcdc_lcdidr, ~0UL); 187 lcdc_writel(®s->lcdc_baseidr, ~0UL); 188 189 /* Setup the DMA descriptor, this descriptor will loop to itself */ 190 desc = (struct lcd_dma_desc *)(lcdbase - 16); 191 192 desc->address = (u32)lcdbase; 193 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */ 194 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN 195 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; 196 desc->next = (u32)desc; 197 198 lcdc_writel(®s->lcdc_baseaddr, desc->address); 199 lcdc_writel(®s->lcdc_basectrl, desc->control); 200 lcdc_writel(®s->lcdc_basenext, desc->next); 201 lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN | 202 LCDC_BASECHER_UPDATEEN); 203 204 /* Enable LCD */ 205 value = lcdc_readl(®s->lcdc_lcden); 206 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN); 207 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) 208 udelay(1); 209 value = lcdc_readl(®s->lcdc_lcden); 210 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN); 211 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) 212 udelay(1); 213 value = lcdc_readl(®s->lcdc_lcden); 214 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN); 215 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) 216 udelay(1); 217 value = lcdc_readl(®s->lcdc_lcden); 218 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN); 219 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) 220 udelay(1); 221 } 222