1*352d2591SJean-Christophe PLAGNIOL-VILLARD /* 2*352d2591SJean-Christophe PLAGNIOL-VILLARD * ATI PCI IDs from XFree86, kept here to make sync'ing with 3*352d2591SJean-Christophe PLAGNIOL-VILLARD * XFree much simpler. Currently, this list is only used by 4*352d2591SJean-Christophe PLAGNIOL-VILLARD * radeonfb 5*352d2591SJean-Christophe PLAGNIOL-VILLARD */ 6*352d2591SJean-Christophe PLAGNIOL-VILLARD 7*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3150 0x3150 8*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3151 0x3151 9*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3152 0x3152 10*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3153 0x3153 11*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3154 0x3154 12*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3156 0x3156 13*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3E50 0x3E50 14*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3E51 0x3E51 15*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3E52 0x3E52 16*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3E53 0x3E53 17*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3E54 0x3E54 18*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_3E56 0x3E56 19*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS100_4136 0x4136 20*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS200_4137 0x4137 21*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R300_AD 0x4144 22*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R300_AE 0x4145 23*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R300_AF 0x4146 24*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R300_AG 0x4147 25*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R350_AH 0x4148 26*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R350_AI 0x4149 27*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R350_AJ 0x414A 28*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R350_AK 0x414B 29*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_AP 0x4150 30*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_AQ 0x4151 31*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV360_AR 0x4152 32*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_AS 0x4153 33*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_AT 0x4154 34*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_AV 0x4156 35*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH32 0x4158 36*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS250_4237 0x4237 37*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R200_BB 0x4242 38*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R200_BC 0x4243 39*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS100_4336 0x4336 40*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS200_4337 0x4337 41*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64CT 0x4354 42*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64CX 0x4358 43*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS250_4437 0x4437 44*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64ET 0x4554 45*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GB 0x4742 46*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GD 0x4744 47*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GI 0x4749 48*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GL 0x474C 49*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GM 0x474D 50*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GN 0x474E 51*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GO 0x474F 52*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GP 0x4750 53*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GQ 0x4751 54*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GR 0x4752 55*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GS 0x4753 56*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GT 0x4754 57*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GU 0x4755 58*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GV 0x4756 59*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GW 0x4757 60*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GX 0x4758 61*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GY 0x4759 62*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64GZ 0x475A 63*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV250_Id 0x4964 64*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV250_Ie 0x4965 65*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV250_If 0x4966 66*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV250_Ig 0x4967 67*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_JH 0x4A48 68*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_JI 0x4A49 69*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_JJ 0x4A4A 70*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_JK 0x4A4B 71*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_JL 0x4A4C 72*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_JM 0x4A4D 73*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_JN 0x4A4E 74*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_JP 0x4A50 75*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LB 0x4C42 76*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LD 0x4C44 77*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128LE 0x4C45 78*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128LF 0x4C46 79*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LG 0x4C47 80*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LI 0x4C49 81*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LM 0x4C4D 82*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LN 0x4C4E 83*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LP 0x4C50 84*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LQ 0x4C51 85*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LR 0x4C52 86*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LS 0x4C53 87*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64LT 0x4C54 88*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RADEON_LW 0x4C57 89*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RADEON_LX 0x4C58 90*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RADEON_LY 0x4C59 91*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RADEON_LZ 0x4C5A 92*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV250_Ld 0x4C64 93*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV250_Le 0x4C65 94*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV250_Lf 0x4C66 95*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV250_Lg 0x4C67 96*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV250_Ln 0x4C6E 97*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128MF 0x4D46 98*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128ML 0x4D4C 99*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R300_ND 0x4E44 100*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R300_NE 0x4E45 101*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R300_NF 0x4E46 102*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R300_NG 0x4E47 103*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R350_NH 0x4E48 104*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R350_NI 0x4E49 105*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R360_NJ 0x4E4A 106*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R350_NK 0x4E4B 107*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_NP 0x4E50 108*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_NQ 0x4E51 109*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_NR 0x4E52 110*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_NS 0x4E53 111*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_NT 0x4E54 112*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV350_NV 0x4E56 113*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PA 0x5041 114*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PB 0x5042 115*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PC 0x5043 116*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PD 0x5044 117*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PE 0x5045 118*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PF 0x5046 119*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PG 0x5047 120*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PH 0x5048 121*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PI 0x5049 122*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PJ 0x504A 123*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PK 0x504B 124*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PL 0x504C 125*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PM 0x504D 126*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PN 0x504E 127*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PO 0x504F 128*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PP 0x5050 129*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PQ 0x5051 130*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PR 0x5052 131*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PS 0x5053 132*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PT 0x5054 133*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PU 0x5055 134*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PV 0x5056 135*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PW 0x5057 136*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128PX 0x5058 137*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RADEON_QD 0x5144 138*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RADEON_QE 0x5145 139*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RADEON_QF 0x5146 140*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RADEON_QG 0x5147 141*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R200_QH 0x5148 142*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R200_QI 0x5149 143*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R200_QJ 0x514A 144*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R200_QK 0x514B 145*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R200_QL 0x514C 146*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R200_QM 0x514D 147*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R200_QN 0x514E 148*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R200_QO 0x514F 149*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV200_QW 0x5157 150*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV200_QX 0x5158 151*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV100_QY 0x5159 152*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV100_QZ 0x515A 153*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RN50 0x515E 154*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128RE 0x5245 155*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128RF 0x5246 156*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128RG 0x5247 157*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128RK 0x524B 158*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128RL 0x524C 159*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128SE 0x5345 160*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128SF 0x5346 161*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128SG 0x5347 162*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128SH 0x5348 163*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128SK 0x534B 164*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128SL 0x534C 165*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128SM 0x534D 166*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128SN 0x534E 167*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128TF 0x5446 168*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128TL 0x544C 169*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128TR 0x5452 170*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128TS 0x5453 171*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128TT 0x5454 172*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RAGE128TU 0x5455 173*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5460 0x5460 174*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5461 0x5461 175*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5462 0x5462 176*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5463 0x5463 177*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5464 0x5464 178*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5465 0x5465 179*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5466 0x5466 180*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5467 0x5467 181*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R423_UH 0x5548 182*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R423_UI 0x5549 183*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R423_UJ 0x554A 184*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R423_UK 0x554B 185*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R423_UQ 0x5551 186*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R423_UR 0x5552 187*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R423_UT 0x5554 188*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64VT 0x5654 189*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64VU 0x5655 190*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_MACH64VV 0x5656 191*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS300_5834 0x5834 192*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS300_5835 0x5835 193*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS300_5836 0x5836 194*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS300_5837 0x5837 195*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B60 0x5B60 196*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B61 0x5B61 197*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B62 0x5B62 198*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B63 0x5B63 199*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B64 0x5B64 200*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B65 0x5B65 201*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B66 0x5B66 202*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B67 0x5B67 203*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5960 0x5960 204*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5961 0x5961 205*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5962 0x5962 206*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5964 0x5964 207*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5C61 0x5C61 208*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5C63 0x5C63 209*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R423_5D57 0x5D57 210*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS350_7834 0x7834 211*352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RS350_7835 0x7835 212