xref: /rk3399_rockchip-uboot/drivers/video/Kconfig (revision 801ab9e93c228b30bb526bb1b431e042d46ba2e8)
16b1ba984SSimon Glassconfig VIDEO_VESA
26b1ba984SSimon Glass	bool "Enable VESA video driver support"
36b1ba984SSimon Glass	default n
46b1ba984SSimon Glass	help
56b1ba984SSimon Glass	  Turn on this option to enable a very simple driver which uses vesa
66b1ba984SSimon Glass	  to discover the video mode and then provides a frame buffer for use
76b1ba984SSimon Glass	  by U-Boot. This can in principle be used with any platform that
86b1ba984SSimon Glass	  supports PCI and video cards that support VESA BIOS Extension (VBE).
96b1ba984SSimon Glass
106bde2dc5SBin Mengconfig FRAMEBUFFER_SET_VESA_MODE
116bde2dc5SBin Meng	bool "Set framebuffer graphics resolution"
126bde2dc5SBin Meng	depends on VIDEO_VESA
136bde2dc5SBin Meng	help
146bde2dc5SBin Meng	  Set VESA/native framebuffer mode (needed for bootsplash and graphical
156bde2dc5SBin Meng	  framebuffer console)
166bde2dc5SBin Meng
176bde2dc5SBin Mengchoice
186bde2dc5SBin Meng	prompt "framebuffer graphics resolution"
196bde2dc5SBin Meng	default FRAMEBUFFER_VESA_MODE_117
206bde2dc5SBin Meng	depends on FRAMEBUFFER_SET_VESA_MODE
216bde2dc5SBin Meng	help
226bde2dc5SBin Meng	  This option sets the resolution used for the U-Boot framebuffer (and
236bde2dc5SBin Meng	  bootsplash screen).
246bde2dc5SBin Meng
256bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_100
266bde2dc5SBin Meng	bool "640x400 256-color"
276bde2dc5SBin Meng
286bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_101
296bde2dc5SBin Meng	bool "640x480 256-color"
306bde2dc5SBin Meng
316bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_102
326bde2dc5SBin Meng	bool "800x600 16-color"
336bde2dc5SBin Meng
346bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_103
356bde2dc5SBin Meng	bool "800x600 256-color"
366bde2dc5SBin Meng
376bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_104
386bde2dc5SBin Meng	bool "1024x768 16-color"
396bde2dc5SBin Meng
406bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_105
416bde2dc5SBin Meng	bool "1024x7686 256-color"
426bde2dc5SBin Meng
436bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_106
446bde2dc5SBin Meng	bool "1280x1024 16-color"
456bde2dc5SBin Meng
466bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_107
476bde2dc5SBin Meng	bool "1280x1024 256-color"
486bde2dc5SBin Meng
496bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_108
506bde2dc5SBin Meng	bool "80x60 text"
516bde2dc5SBin Meng
526bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_109
536bde2dc5SBin Meng	bool "132x25 text"
546bde2dc5SBin Meng
556bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10A
566bde2dc5SBin Meng	bool "132x43 text"
576bde2dc5SBin Meng
586bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10B
596bde2dc5SBin Meng	bool "132x50 text"
606bde2dc5SBin Meng
616bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10C
626bde2dc5SBin Meng	bool "132x60 text"
636bde2dc5SBin Meng
646bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10D
656bde2dc5SBin Meng	bool "320x200 32k-color (1:5:5:5)"
666bde2dc5SBin Meng
676bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10E
686bde2dc5SBin Meng	bool "320x200 64k-color (5:6:5)"
696bde2dc5SBin Meng
706bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10F
716bde2dc5SBin Meng	bool "320x200 16.8M-color (8:8:8)"
726bde2dc5SBin Meng
736bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_110
746bde2dc5SBin Meng	bool "640x480 32k-color (1:5:5:5)"
756bde2dc5SBin Meng
766bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_111
776bde2dc5SBin Meng	bool "640x480 64k-color (5:6:5)"
786bde2dc5SBin Meng
796bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_112
806bde2dc5SBin Meng	bool "640x480 16.8M-color (8:8:8)"
816bde2dc5SBin Meng
826bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_113
836bde2dc5SBin Meng	bool "800x600 32k-color (1:5:5:5)"
846bde2dc5SBin Meng
856bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_114
866bde2dc5SBin Meng	bool "800x600 64k-color (5:6:5)"
876bde2dc5SBin Meng
886bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_115
896bde2dc5SBin Meng	bool "800x600 16.8M-color (8:8:8)"
906bde2dc5SBin Meng
916bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_116
926bde2dc5SBin Meng	bool "1024x768 32k-color (1:5:5:5)"
936bde2dc5SBin Meng
946bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_117
956bde2dc5SBin Meng	bool "1024x768 64k-color (5:6:5)"
966bde2dc5SBin Meng
976bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_118
986bde2dc5SBin Meng	bool "1024x768 16.8M-color (8:8:8)"
996bde2dc5SBin Meng
1006bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_119
1016bde2dc5SBin Meng	bool "1280x1024 32k-color (1:5:5:5)"
1026bde2dc5SBin Meng
1036bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_11A
1046bde2dc5SBin Meng	bool "1280x1024 64k-color (5:6:5)"
1056bde2dc5SBin Meng
1066bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_11B
1076bde2dc5SBin Meng	bool "1280x1024 16.8M-color (8:8:8)"
1086bde2dc5SBin Meng
1096bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_USER
1106bde2dc5SBin Meng	bool "Manually select VESA mode"
1116bde2dc5SBin Meng
1126bde2dc5SBin Mengendchoice
1136bde2dc5SBin Meng
1146bde2dc5SBin Meng# Map the config names to an integer (KB).
1156bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE
1166bde2dc5SBin Meng	prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
1176bde2dc5SBin Meng	hex
1186bde2dc5SBin Meng	default 0x100 if FRAMEBUFFER_VESA_MODE_100
1196bde2dc5SBin Meng	default 0x101 if FRAMEBUFFER_VESA_MODE_101
1206bde2dc5SBin Meng	default 0x102 if FRAMEBUFFER_VESA_MODE_102
1216bde2dc5SBin Meng	default 0x103 if FRAMEBUFFER_VESA_MODE_103
1226bde2dc5SBin Meng	default 0x104 if FRAMEBUFFER_VESA_MODE_104
1236bde2dc5SBin Meng	default 0x105 if FRAMEBUFFER_VESA_MODE_105
1246bde2dc5SBin Meng	default 0x106 if FRAMEBUFFER_VESA_MODE_106
1256bde2dc5SBin Meng	default 0x107 if FRAMEBUFFER_VESA_MODE_107
1266bde2dc5SBin Meng	default 0x108 if FRAMEBUFFER_VESA_MODE_108
1276bde2dc5SBin Meng	default 0x109 if FRAMEBUFFER_VESA_MODE_109
1286bde2dc5SBin Meng	default 0x10A if FRAMEBUFFER_VESA_MODE_10A
1296bde2dc5SBin Meng	default 0x10B if FRAMEBUFFER_VESA_MODE_10B
1306bde2dc5SBin Meng	default 0x10C if FRAMEBUFFER_VESA_MODE_10C
1316bde2dc5SBin Meng	default 0x10D if FRAMEBUFFER_VESA_MODE_10D
1326bde2dc5SBin Meng	default 0x10E if FRAMEBUFFER_VESA_MODE_10E
1336bde2dc5SBin Meng	default 0x10F if FRAMEBUFFER_VESA_MODE_10F
1346bde2dc5SBin Meng	default 0x110 if FRAMEBUFFER_VESA_MODE_110
1356bde2dc5SBin Meng	default 0x111 if FRAMEBUFFER_VESA_MODE_111
1366bde2dc5SBin Meng	default 0x112 if FRAMEBUFFER_VESA_MODE_112
1376bde2dc5SBin Meng	default 0x113 if FRAMEBUFFER_VESA_MODE_113
1386bde2dc5SBin Meng	default 0x114 if FRAMEBUFFER_VESA_MODE_114
1396bde2dc5SBin Meng	default 0x115 if FRAMEBUFFER_VESA_MODE_115
1406bde2dc5SBin Meng	default 0x116 if FRAMEBUFFER_VESA_MODE_116
1416bde2dc5SBin Meng	default 0x117 if FRAMEBUFFER_VESA_MODE_117
1426bde2dc5SBin Meng	default 0x118 if FRAMEBUFFER_VESA_MODE_118
1436bde2dc5SBin Meng	default 0x119 if FRAMEBUFFER_VESA_MODE_119
1446bde2dc5SBin Meng	default 0x11A if FRAMEBUFFER_VESA_MODE_11A
1456bde2dc5SBin Meng	default 0x11B if FRAMEBUFFER_VESA_MODE_11B
1466bde2dc5SBin Meng	default 0x117 if FRAMEBUFFER_VESA_MODE_USER
1476bde2dc5SBin Meng
148b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828
149b8329acfSSiarhei Siamashka	bool "SSD2828 bridge chip"
150b8329acfSSiarhei Siamashka	default n
151b8329acfSSiarhei Siamashka	---help---
152b8329acfSSiarhei Siamashka	Support for the SSD2828 bridge chip, which can take pixel data coming
153b8329acfSSiarhei Siamashka	from a parallel LCD interface and translate it on the fly into MIPI DSI
154b8329acfSSiarhei Siamashka	interface for driving a MIPI compatible LCD panel. It uses SPI for
155b8329acfSSiarhei Siamashka	configuration.
156b8329acfSSiarhei Siamashka
157b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828_TX_CLK
158b8329acfSSiarhei Siamashka	int "SSD2828 TX_CLK frequency (in MHz)"
159b8329acfSSiarhei Siamashka	depends on VIDEO_LCD_SSD2828
160dddccd69SSiarhei Siamashka	default 0
161b8329acfSSiarhei Siamashka	---help---
162b8329acfSSiarhei Siamashka	The frequency of the crystal, which is clocking SSD2828. It may be
163b8329acfSSiarhei Siamashka	anything in the 8MHz-30MHz range and the exact value should be
164b8329acfSSiarhei Siamashka	retrieved from the board schematics. Or in the case of Allwinner
165b8329acfSSiarhei Siamashka	hardware, it can be usually found as 'lcd_xtal_freq' variable in
166dddccd69SSiarhei Siamashka	FEX files. It can be also set to 0 for selecting PCLK from the
167dddccd69SSiarhei Siamashka	parallel LCD interface instead of TX_CLK as the PLL clock source.
168b8329acfSSiarhei Siamashka
169b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828_RESET
170b8329acfSSiarhei Siamashka	string "RESET pin of SSD2828"
171b8329acfSSiarhei Siamashka	depends on VIDEO_LCD_SSD2828
172b8329acfSSiarhei Siamashka	default ""
173b8329acfSSiarhei Siamashka	---help---
174b8329acfSSiarhei Siamashka	The reset pin of SSD2828 chip. This takes a string in the format
175b8329acfSSiarhei Siamashka	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
176b8329acfSSiarhei Siamashka
177a5464f2bSHans de Goedeconfig VIDEO_LCD_HITACHI_TX18D42VM
178a5464f2bSHans de Goede	bool "Hitachi tx18d42vm LVDS LCD panel support"
179a5464f2bSHans de Goede	depends on VIDEO
180a5464f2bSHans de Goede	default n
181a5464f2bSHans de Goede	---help---
182a5464f2bSHans de Goede	Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
183a5464f2bSHans de Goede	lcd controller which needs to be initialized over SPI, once that is
184a5464f2bSHans de Goede	done they work like a regular LVDS panel.
185a5464f2bSHans de Goede
186b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_CS
187b8329acfSSiarhei Siamashka	string "SPI CS pin for LCD related config job"
188a5464f2bSHans de Goede	depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
189b8329acfSSiarhei Siamashka	default ""
190b8329acfSSiarhei Siamashka	---help---
191b8329acfSSiarhei Siamashka	This is one of the SPI communication pins, involved in setting up a
192b8329acfSSiarhei Siamashka	working LCD configuration. The exact role of SPI may differ for
193b8329acfSSiarhei Siamashka	different hardware setups. The option takes a string in the format
194b8329acfSSiarhei Siamashka	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
195b8329acfSSiarhei Siamashka
196b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_SCLK
197b8329acfSSiarhei Siamashka	string "SPI SCLK pin for LCD related config job"
198a5464f2bSHans de Goede	depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
199b8329acfSSiarhei Siamashka	default ""
200b8329acfSSiarhei Siamashka	---help---
201b8329acfSSiarhei Siamashka	This is one of the SPI communication pins, involved in setting up a
202b8329acfSSiarhei Siamashka	working LCD configuration. The exact role of SPI may differ for
203b8329acfSSiarhei Siamashka	different hardware setups. The option takes a string in the format
204b8329acfSSiarhei Siamashka	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
205b8329acfSSiarhei Siamashka
206b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_MOSI
207b8329acfSSiarhei Siamashka	string "SPI MOSI pin for LCD related config job"
208a5464f2bSHans de Goede	depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
209b8329acfSSiarhei Siamashka	default ""
210b8329acfSSiarhei Siamashka	---help---
211b8329acfSSiarhei Siamashka	This is one of the SPI communication pins, involved in setting up a
212b8329acfSSiarhei Siamashka	working LCD configuration. The exact role of SPI may differ for
213b8329acfSSiarhei Siamashka	different hardware setups. The option takes a string in the format
214b8329acfSSiarhei Siamashka	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
215b8329acfSSiarhei Siamashka
216b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_MISO
217b8329acfSSiarhei Siamashka	string "SPI MISO pin for LCD related config job (optional)"
218b8329acfSSiarhei Siamashka	depends on VIDEO_LCD_SSD2828
219b8329acfSSiarhei Siamashka	default ""
220b8329acfSSiarhei Siamashka	---help---
221b8329acfSSiarhei Siamashka	This is one of the SPI communication pins, involved in setting up a
222b8329acfSSiarhei Siamashka	working LCD configuration. The exact role of SPI may differ for
223b8329acfSSiarhei Siamashka	different hardware setups. If wired up, this pin may provide additional
224b8329acfSSiarhei Siamashka	useful functionality. Such as bi-directional communication with the
225b8329acfSSiarhei Siamashka	hardware and LCD panel id retrieval (if the panel can report it). The
226b8329acfSSiarhei Siamashka	option takes a string in the format understood by 'name_to_gpio'
227b8329acfSSiarhei Siamashka	function, e.g. PH1 for pin 1 of port H.
22851f2c99eSSimon Glass
22951f2c99eSSimon Glassconfig DISPLAY_PORT
23051f2c99eSSimon Glass	bool "Enable DisplayPort support"
23151f2c99eSSimon Glass	help
23251f2c99eSSimon Glass	   eDP (Embedded DisplayPort) is a standard widely used in laptops
23351f2c99eSSimon Glass	   to drive LCD panels. This framework provides support for enabling
23451f2c99eSSimon Glass	   these displays where supported by the video hardware.
235e7e8823cSSimon Glass
236e7e8823cSSimon Glassconfig VIDEO_TEGRA124
237e7e8823cSSimon Glass	bool "Enable video support on Tegra124"
238e7e8823cSSimon Glass	help
239e7e8823cSSimon Glass	   Tegra124 supports many video output options including eDP and
240e7e8823cSSimon Glass	   HDMI. At present only eDP is supported by U-Boot. This option
241e7e8823cSSimon Glass	   enables this support which can be used on devices which
242e7e8823cSSimon Glass	   have an eDP display connected.
243*801ab9e9SSimon Glass
244*801ab9e9SSimon Glasssource "drivers/video/bridge/Kconfig"
245