1 /* 2 * Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/clock.h> 9 #include <asm/io.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <syscon.h> 13 14 #include "../gadget/dwc2_udc_otg_priv.h" 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 #define BIT_WRITEABLE_SHIFT 16 19 20 struct usb2phy_reg { 21 unsigned int offset; 22 unsigned int bitend; 23 unsigned int bitstart; 24 unsigned int disable; 25 unsigned int enable; 26 }; 27 28 /** 29 * struct rockchip_usb2_phy_cfg: usb-phy port configuration 30 * @port_reset: usb otg per-port reset register 31 * @soft_con: software control usb otg register 32 * @suspend: phy suspend register 33 */ 34 struct rockchip_usb2_phy_cfg { 35 struct usb2phy_reg port_reset; 36 struct usb2phy_reg siddq; 37 struct usb2phy_reg soft_con; 38 struct usb2phy_reg suspend; 39 }; 40 41 struct rockchip_usb2_phy_dt_id { 42 char compatible[128]; 43 const void *data; 44 }; 45 46 static const struct rockchip_usb2_phy_cfg rk3288_pdata = { 47 .port_reset = {0x00, 12, 12, 0, 1}, 48 .siddq = {0x00, 13, 13, 0, 1}, 49 .soft_con = {0x08, 2, 2, 0, 1}, 50 .suspend = {0x0c, 5, 0, 0x01, 0x2A}, 51 }; 52 53 static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = { 54 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata }, 55 {} 56 }; 57 58 static void property_enable(struct dwc2_plat_otg_data *pdata, 59 const struct usb2phy_reg *reg, bool en) 60 { 61 unsigned int val, mask, tmp; 62 63 tmp = en ? reg->enable : reg->disable; 64 mask = GENMASK(reg->bitend, reg->bitstart); 65 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 66 67 writel(val, pdata->regs_phy + reg->offset); 68 } 69 70 int rockchip_u2phy_vbus_detect(void) 71 { 72 u32 val = 0; 73 74 #ifdef CONFIG_ROCKCHIP_RK3288 75 u32 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 76 77 val = readl(grf_base + 0x288); 78 val = (val & BIT(14)) >> 14; 79 #endif 80 81 return val; 82 } 83 84 static int otg_phy_parse(struct dwc2_udc *dev) 85 { 86 int node, phy_node; 87 u32 grf_base, grf_offset; 88 const char *mode; 89 bool matched = false; 90 const void *blob = gd->fdt_blob; 91 struct dwc2_plat_otg_data *pdata = dev->pdata; 92 93 /* Find the usb_otg node */ 94 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 95 while (node > 0) { 96 mode = fdt_getprop(blob, node, "dr_mode", NULL); 97 if (mode && strcmp(mode, "otg") == 0) { 98 matched = true; 99 break; 100 } 101 102 node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2"); 103 } 104 105 if (!matched) { 106 /* 107 * With kernel dtb support, rk3288 dwc2 otg node 108 * use the rockchip legacy dwc2 driver "dwc_otg_310" 109 * with the compatible "rockchip,rk3288_usb20_otg". 110 */ 111 node = fdt_node_offset_by_compatible(blob, -1, 112 "rockchip,rk3288_usb20_otg"); 113 if (node > 0) { 114 matched = true; 115 } else { 116 pr_err("Not found usb_otg device\n"); 117 return -ENODEV; 118 } 119 } 120 121 /* Find the usb phy node */ 122 node = fdtdec_lookup_phandle(blob, node, "phys"); 123 if (node <= 0) { 124 pr_err("Not found usbphy device\n"); 125 return -ENODEV; 126 } 127 128 /* Find the usb otg-phy node */ 129 phy_node = fdt_parent_offset(blob, node); 130 if (phy_node <= 0) { 131 pr_err("Not found sub usbphy device\n"); 132 return -ENODEV; 133 } 134 135 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 136 grf_offset = fdtdec_get_addr(blob, node, "reg"); 137 138 /* Pad dwc2_plat_otg_data related to phy */ 139 pdata->phy_of_node = phy_node; 140 pdata->regs_phy = grf_base + grf_offset; 141 142 return 0; 143 } 144 145 void otg_phy_init(struct dwc2_udc *dev) 146 { 147 struct dwc2_plat_otg_data *pdata = dev->pdata; 148 struct rockchip_usb2_phy_cfg *phy_cfg = NULL; 149 struct rockchip_usb2_phy_dt_id *of_id; 150 int i; 151 152 if (!pdata->regs_phy && otg_phy_parse(dev)) { 153 pr_err("otg-phy parse error\n"); 154 return; 155 } 156 157 for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) { 158 of_id = &rockchip_usb2_phy_dt_ids[i]; 159 if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node, 160 of_id->compatible) == 0) { 161 phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data; 162 break; 163 } 164 } 165 if (!phy_cfg) { 166 debug("Can't find device platform data\n"); 167 168 hang(); 169 return; 170 } 171 pdata->priv = phy_cfg; 172 173 /* power up usb phy analog blocks by set siddq 0 */ 174 property_enable(pdata, &phy_cfg->siddq, false); 175 176 /* disable software control */ 177 property_enable(pdata, &phy_cfg->soft_con, false); 178 179 /* reset otg port */ 180 property_enable(pdata, &phy_cfg->port_reset, true); 181 mdelay(1); 182 property_enable(pdata, &phy_cfg->port_reset, false); 183 udelay(1); 184 } 185 186 void otg_phy_off(struct dwc2_udc *dev) 187 { 188 struct dwc2_plat_otg_data *pdata = dev->pdata; 189 struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv; 190 191 if (!pdata->regs_phy && otg_phy_parse(dev)) { 192 pr_err("otg-phy parse error\n"); 193 return; 194 } 195 196 /* enable software control */ 197 property_enable(pdata, &phy_cfg->soft_con, true); 198 /* enter suspend */ 199 property_enable(pdata, &phy_cfg->suspend, true); 200 } 201