1 /* 2 * Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/clock.h> 9 #include <asm/io.h> 10 #include <fdtdec.h> 11 #include <syscon.h> 12 13 #include "../gadget/dwc2_udc_otg_priv.h" 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #define BIT_WRITEABLE_SHIFT 16 18 19 struct usb2phy_reg { 20 unsigned int offset; 21 unsigned int bitend; 22 unsigned int bitstart; 23 unsigned int disable; 24 unsigned int enable; 25 }; 26 27 /** 28 * struct rockchip_usb2_phy_cfg: usb-phy port configuration 29 * @port_reset: usb otg per-port reset register 30 * @soft_con: software control usb otg register 31 * @suspend: phy suspend register 32 */ 33 struct rockchip_usb2_phy_cfg { 34 struct usb2phy_reg port_reset; 35 struct usb2phy_reg siddq; 36 struct usb2phy_reg soft_con; 37 struct usb2phy_reg suspend; 38 }; 39 40 struct rockchip_usb2_phy_dt_id { 41 char compatible[128]; 42 const void *data; 43 }; 44 45 static const struct rockchip_usb2_phy_cfg rk3288_pdata = { 46 .port_reset = {0x00, 12, 12, 0, 1}, 47 .siddq = {0x00, 13, 13, 0, 1}, 48 .soft_con = {0x08, 2, 2, 0, 1}, 49 .suspend = {0x0c, 5, 0, 0x01, 0x2A}, 50 }; 51 52 static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = { 53 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata }, 54 {} 55 }; 56 57 static void property_enable(struct dwc2_plat_otg_data *pdata, 58 const struct usb2phy_reg *reg, bool en) 59 { 60 unsigned int val, mask, tmp; 61 62 tmp = en ? reg->enable : reg->disable; 63 mask = GENMASK(reg->bitend, reg->bitstart); 64 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 65 66 writel(val, pdata->regs_phy + reg->offset); 67 } 68 69 int rockchip_u2phy_vbus_detect(void) 70 { 71 u32 val = 0; 72 73 #ifdef CONFIG_ROCKCHIP_RK3288 74 u32 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 75 76 val = readl(grf_base + 0x288); 77 val = (val & BIT(14)) >> 14; 78 #endif 79 80 return val; 81 } 82 83 static int otg_phy_parse(struct dwc2_udc *dev) 84 { 85 int node, phy_node; 86 u32 grf_base, grf_offset; 87 const char *mode; 88 bool matched = false; 89 const void *blob = gd->fdt_blob; 90 struct dwc2_plat_otg_data *pdata = dev->pdata; 91 92 /* Find the usb_otg node */ 93 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 94 while (node > 0) { 95 mode = fdt_getprop(blob, node, "dr_mode", NULL); 96 if (mode && strcmp(mode, "otg") == 0) { 97 matched = true; 98 break; 99 } 100 101 node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2"); 102 } 103 104 if (!matched) { 105 /* 106 * With kernel dtb support, rk3288 dwc2 otg node 107 * use the rockchip legacy dwc2 driver "dwc_otg_310" 108 * with the compatible "rockchip,rk3288_usb20_otg". 109 */ 110 node = fdt_node_offset_by_compatible(blob, -1, 111 "rockchip,rk3288_usb20_otg"); 112 if (node > 0) { 113 matched = true; 114 } else { 115 pr_err("Not found usb_otg device\n"); 116 return -ENODEV; 117 } 118 } 119 120 /* Find the usb phy node */ 121 node = fdtdec_lookup_phandle(blob, node, "phys"); 122 if (node <= 0) { 123 pr_err("Not found usbphy device\n"); 124 return -ENODEV; 125 } 126 127 /* Find the usb otg-phy node */ 128 phy_node = fdt_parent_offset(blob, node); 129 if (phy_node <= 0) { 130 pr_err("Not found sub usbphy device\n"); 131 return -ENODEV; 132 } 133 134 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 135 grf_offset = fdtdec_get_addr(blob, node, "reg"); 136 137 /* Pad dwc2_plat_otg_data related to phy */ 138 pdata->phy_of_node = phy_node; 139 pdata->regs_phy = grf_base + grf_offset; 140 141 return 0; 142 } 143 144 void otg_phy_init(struct dwc2_udc *dev) 145 { 146 struct dwc2_plat_otg_data *pdata = dev->pdata; 147 struct rockchip_usb2_phy_cfg *phy_cfg = NULL; 148 struct rockchip_usb2_phy_dt_id *of_id; 149 int i; 150 151 if (!pdata->regs_phy && otg_phy_parse(dev)) { 152 pr_err("otg-phy parse error\n"); 153 return; 154 } 155 156 for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) { 157 of_id = &rockchip_usb2_phy_dt_ids[i]; 158 if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node, 159 of_id->compatible) == 0) { 160 phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data; 161 break; 162 } 163 } 164 if (!phy_cfg) { 165 debug("Can't find device platform data\n"); 166 167 hang(); 168 return; 169 } 170 pdata->priv = phy_cfg; 171 172 /* power up usb phy analog blocks by set siddq 0 */ 173 property_enable(pdata, &phy_cfg->siddq, false); 174 175 /* disable software control */ 176 property_enable(pdata, &phy_cfg->soft_con, false); 177 178 /* reset otg port */ 179 property_enable(pdata, &phy_cfg->port_reset, true); 180 mdelay(1); 181 property_enable(pdata, &phy_cfg->port_reset, false); 182 udelay(1); 183 } 184 185 void otg_phy_off(struct dwc2_udc *dev) 186 { 187 struct dwc2_plat_otg_data *pdata = dev->pdata; 188 struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv; 189 190 if (!pdata->regs_phy && otg_phy_parse(dev)) { 191 pr_err("otg-phy parse error\n"); 192 return; 193 } 194 195 /* enable software control */ 196 property_enable(pdata, &phy_cfg->soft_con, true); 197 /* enter suspend */ 198 property_enable(pdata, &phy_cfg->suspend, true); 199 } 200