1 /* 2 * Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/clock.h> 9 #include <asm/io.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <syscon.h> 13 14 #include "../gadget/dwc2_udc_otg_priv.h" 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 #define BIT_WRITEABLE_SHIFT 16 19 20 struct usb2phy_reg { 21 unsigned int offset; 22 unsigned int bitend; 23 unsigned int bitstart; 24 unsigned int disable; 25 unsigned int enable; 26 }; 27 28 /** 29 * struct rockchip_usb2_phy_cfg: usb-phy port configuration 30 * @port_reset: usb otg per-port reset register 31 * @soft_con: software control usb otg register 32 * @suspend: phy suspend register 33 */ 34 struct rockchip_usb2_phy_cfg { 35 struct usb2phy_reg port_reset; 36 struct usb2phy_reg soft_con; 37 struct usb2phy_reg suspend; 38 }; 39 40 struct rockchip_usb2_phy_dt_id { 41 char compatible[128]; 42 const void *data; 43 }; 44 45 static const struct rockchip_usb2_phy_cfg rk3288_pdata = { 46 .port_reset = {0x00, 12, 12, 0, 1}, 47 .soft_con = {0x08, 2, 2, 0, 1}, 48 .suspend = {0x0c, 5, 0, 0x01, 0x2A}, 49 }; 50 51 static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = { 52 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata }, 53 {} 54 }; 55 56 static void property_enable(struct dwc2_plat_otg_data *pdata, 57 const struct usb2phy_reg *reg, bool en) 58 { 59 unsigned int val, mask, tmp; 60 61 tmp = en ? reg->enable : reg->disable; 62 mask = GENMASK(reg->bitend, reg->bitstart); 63 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 64 65 writel(val, pdata->regs_phy + reg->offset); 66 } 67 68 static int otg_phy_parse(struct dwc2_udc *dev) 69 { 70 int node, phy_node; 71 u32 grf_base, grf_offset; 72 const char *mode; 73 bool matched = false; 74 const void *blob = gd->fdt_blob; 75 struct dwc2_plat_otg_data *pdata = dev->pdata; 76 77 /* Find the usb_otg node */ 78 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 79 while (node > 0) { 80 mode = fdt_getprop(blob, node, "dr_mode", NULL); 81 if (mode && strcmp(mode, "otg") == 0) { 82 matched = true; 83 break; 84 } 85 86 node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2"); 87 } 88 89 if (!matched) { 90 /* 91 * With kernel dtb support, rk3288 dwc2 otg node 92 * use the rockchip legacy dwc2 driver "dwc_otg_310" 93 * with the compatible "rockchip,rk3288_usb20_otg". 94 */ 95 node = fdt_node_offset_by_compatible(blob, -1, 96 "rockchip,rk3288_usb20_otg"); 97 if (node > 0) { 98 matched = true; 99 } else { 100 pr_err("Not found usb_otg device\n"); 101 return -ENODEV; 102 } 103 } 104 105 /* Find the usb phy node */ 106 node = fdtdec_lookup_phandle(blob, node, "phys"); 107 if (node <= 0) { 108 pr_err("Not found usbphy device\n"); 109 return -ENODEV; 110 } 111 112 /* Find the usb otg-phy node */ 113 phy_node = fdt_parent_offset(blob, node); 114 if (phy_node <= 0) { 115 pr_err("Not found sub usbphy device\n"); 116 return -ENODEV; 117 } 118 119 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 120 grf_offset = fdtdec_get_addr(blob, node, "reg"); 121 122 /* Pad dwc2_plat_otg_data related to phy */ 123 pdata->phy_of_node = phy_node; 124 pdata->regs_phy = grf_base + grf_offset; 125 126 return 0; 127 } 128 129 void otg_phy_init(struct dwc2_udc *dev) 130 { 131 struct dwc2_plat_otg_data *pdata = dev->pdata; 132 struct rockchip_usb2_phy_cfg *phy_cfg = NULL; 133 struct rockchip_usb2_phy_dt_id *of_id; 134 int i; 135 136 if (!pdata->regs_phy && otg_phy_parse(dev)) { 137 pr_err("otg-phy parse error\n"); 138 return; 139 } 140 141 for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) { 142 of_id = &rockchip_usb2_phy_dt_ids[i]; 143 if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node, 144 of_id->compatible) == 0) { 145 phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data; 146 break; 147 } 148 } 149 if (!phy_cfg) { 150 debug("Can't find device platform data\n"); 151 152 hang(); 153 return; 154 } 155 pdata->priv = phy_cfg; 156 /* disable software control */ 157 property_enable(pdata, &phy_cfg->soft_con, false); 158 159 /* reset otg port */ 160 property_enable(pdata, &phy_cfg->port_reset, true); 161 mdelay(1); 162 property_enable(pdata, &phy_cfg->port_reset, false); 163 udelay(1); 164 } 165 166 void otg_phy_off(struct dwc2_udc *dev) 167 { 168 struct dwc2_plat_otg_data *pdata = dev->pdata; 169 struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv; 170 171 if (!pdata->regs_phy && otg_phy_parse(dev)) { 172 pr_err("otg-phy parse error\n"); 173 return; 174 } 175 176 /* enable software control */ 177 property_enable(pdata, &phy_cfg->soft_con, true); 178 /* enter suspend */ 179 property_enable(pdata, &phy_cfg->suspend, true); 180 } 181