1 /* 2 * Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/clock.h> 9 #include <asm/io.h> 10 #include <dm.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <syscon.h> 14 15 #include "../gadget/dwc2_udc_otg_priv.h" 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define BIT_WRITEABLE_SHIFT 16 20 21 struct usb2phy_reg { 22 unsigned int offset; 23 unsigned int bitend; 24 unsigned int bitstart; 25 unsigned int disable; 26 unsigned int enable; 27 }; 28 29 /** 30 * struct rockchip_usb2_phy_cfg: usb-phy port configuration 31 * @port_reset: usb otg per-port reset register 32 * @soft_con: software control usb otg register 33 * @suspend: phy suspend register 34 */ 35 struct rockchip_usb2_phy_cfg { 36 struct usb2phy_reg port_reset; 37 struct usb2phy_reg siddq; 38 struct usb2phy_reg soft_con; 39 struct usb2phy_reg suspend; 40 }; 41 42 struct rockchip_usb2_phy_dt_id { 43 char compatible[128]; 44 const void *data; 45 }; 46 47 static const struct rockchip_usb2_phy_cfg rk3288_pdata = { 48 .port_reset = {0x00, 12, 12, 0, 1}, 49 .siddq = {0x00, 13, 13, 0, 1}, 50 .soft_con = {0x08, 2, 2, 0, 1}, 51 .suspend = {0x0c, 5, 0, 0x01, 0x2A}, 52 }; 53 54 static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = { 55 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata }, 56 {} 57 }; 58 59 static void property_enable(struct dwc2_plat_otg_data *pdata, 60 const struct usb2phy_reg *reg, bool en) 61 { 62 unsigned int val, mask, tmp; 63 64 tmp = en ? reg->enable : reg->disable; 65 mask = GENMASK(reg->bitend, reg->bitstart); 66 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 67 68 writel(val, pdata->regs_phy + reg->offset); 69 } 70 71 int rockchip_u2phy_vbus_detect(void) 72 { 73 u32 val = 0; 74 75 #ifdef CONFIG_ROCKCHIP_RK3288 76 u32 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 77 78 val = readl(grf_base + 0x288); 79 val = (val & BIT(14)) >> 14; 80 #endif 81 82 return val; 83 } 84 85 static int otg_phy_parse(struct dwc2_udc *dev) 86 { 87 int node, phy_node; 88 u32 grf_base, grf_offset; 89 const void *blob = gd->fdt_blob; 90 const fdt32_t *reg; 91 fdt_addr_t addr; 92 struct dwc2_plat_otg_data *pdata = dev->pdata; 93 94 /* Find the usb_otg node */ 95 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 96 97 #if defined(CONFIG_ROCKCHIP_RK3288) 98 retry: 99 #endif 100 if (node > 0) { 101 reg = fdt_getprop(blob, node, "reg", NULL); 102 if (!reg) 103 return -EINVAL; 104 105 addr = fdt_translate_address(blob, node, reg); 106 if (addr == OF_BAD_ADDR) { 107 pr_err("Not found usb_otg address\n"); 108 return -EINVAL; 109 } 110 111 #if defined(CONFIG_ROCKCHIP_RK3288) 112 if (addr != 0xff580000) { 113 node = fdt_node_offset_by_compatible(blob, node, 114 "snps,dwc2"); 115 goto retry; 116 } 117 #endif 118 } else { 119 /* 120 * With kernel dtb support, rk3288 dwc2 otg node 121 * use the rockchip legacy dwc2 driver "dwc_otg_310" 122 * with the compatible "rockchip,rk3288_usb20_otg". 123 */ 124 #if defined(CONFIG_ROCKCHIP_RK3288) 125 node = fdt_node_offset_by_compatible(blob, -1, 126 "rockchip,rk3288_usb20_otg"); 127 #endif 128 if (node < 0) { 129 pr_err("Not found usb_otg device\n"); 130 return -ENODEV; 131 } 132 } 133 134 /* Find the usb phy node */ 135 node = fdtdec_lookup_phandle(blob, node, "phys"); 136 if (node <= 0) { 137 pr_err("Not found usbphy device\n"); 138 return -ENODEV; 139 } 140 141 /* Find the usb otg-phy node */ 142 phy_node = fdt_parent_offset(blob, node); 143 if (phy_node <= 0) { 144 pr_err("Not found sub usbphy device\n"); 145 return -ENODEV; 146 } 147 148 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 149 grf_offset = fdtdec_get_addr(blob, node, "reg"); 150 151 /* Pad dwc2_plat_otg_data related to phy */ 152 pdata->phy_of_node = phy_node; 153 pdata->regs_phy = grf_base + grf_offset; 154 155 return 0; 156 } 157 158 void otg_phy_init(struct dwc2_udc *dev) 159 { 160 struct dwc2_plat_otg_data *pdata = dev->pdata; 161 struct rockchip_usb2_phy_cfg *phy_cfg = NULL; 162 struct rockchip_usb2_phy_dt_id *of_id; 163 int i; 164 165 if (!pdata->regs_phy && otg_phy_parse(dev)) { 166 pr_err("otg-phy parse error\n"); 167 return; 168 } 169 170 for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) { 171 of_id = &rockchip_usb2_phy_dt_ids[i]; 172 if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node, 173 of_id->compatible) == 0) { 174 phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data; 175 break; 176 } 177 } 178 if (!phy_cfg) { 179 debug("Can't find device platform data\n"); 180 181 hang(); 182 return; 183 } 184 pdata->priv = phy_cfg; 185 186 /* power up usb phy analog blocks by set siddq 0 */ 187 property_enable(pdata, &phy_cfg->siddq, false); 188 189 /* disable software control */ 190 property_enable(pdata, &phy_cfg->soft_con, false); 191 192 /* reset otg port */ 193 property_enable(pdata, &phy_cfg->port_reset, true); 194 mdelay(1); 195 property_enable(pdata, &phy_cfg->port_reset, false); 196 udelay(1); 197 } 198 199 void otg_phy_off(struct dwc2_udc *dev) 200 { 201 struct dwc2_plat_otg_data *pdata = dev->pdata; 202 struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv; 203 204 if (!pdata->regs_phy && otg_phy_parse(dev)) { 205 pr_err("otg-phy parse error\n"); 206 return; 207 } 208 209 /* enable software control */ 210 property_enable(pdata, &phy_cfg->soft_con, true); 211 /* enter suspend */ 212 property_enable(pdata, &phy_cfg->suspend, true); 213 } 214