1 /* 2 * Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/clock.h> 9 #include <asm/io.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <syscon.h> 13 14 #include "../gadget/dwc2_udc_otg_priv.h" 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 #define BIT_WRITEABLE_SHIFT 16 19 20 struct usb2phy_reg { 21 unsigned int offset; 22 unsigned int bitend; 23 unsigned int bitstart; 24 unsigned int disable; 25 unsigned int enable; 26 }; 27 28 /** 29 * struct rockchip_usb2_phy_cfg: usb-phy port configuration 30 * @port_reset: usb otg per-port reset register 31 * @soft_con: software control usb otg register 32 * @suspend: phy suspend register 33 */ 34 struct rockchip_usb2_phy_cfg { 35 struct usb2phy_reg port_reset; 36 struct usb2phy_reg siddq; 37 struct usb2phy_reg soft_con; 38 struct usb2phy_reg suspend; 39 }; 40 41 struct rockchip_usb2_phy_dt_id { 42 char compatible[128]; 43 const void *data; 44 }; 45 46 static const struct rockchip_usb2_phy_cfg rk3288_pdata = { 47 .port_reset = {0x00, 12, 12, 0, 1}, 48 .siddq = {0x00, 13, 13, 0, 1}, 49 .soft_con = {0x08, 2, 2, 0, 1}, 50 .suspend = {0x0c, 5, 0, 0x01, 0x2A}, 51 }; 52 53 static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = { 54 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata }, 55 {} 56 }; 57 58 static void property_enable(struct dwc2_plat_otg_data *pdata, 59 const struct usb2phy_reg *reg, bool en) 60 { 61 unsigned int val, mask, tmp; 62 63 tmp = en ? reg->enable : reg->disable; 64 mask = GENMASK(reg->bitend, reg->bitstart); 65 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 66 67 writel(val, pdata->regs_phy + reg->offset); 68 } 69 70 static int otg_phy_parse(struct dwc2_udc *dev) 71 { 72 int node, phy_node; 73 u32 grf_base, grf_offset; 74 const char *mode; 75 bool matched = false; 76 const void *blob = gd->fdt_blob; 77 struct dwc2_plat_otg_data *pdata = dev->pdata; 78 79 /* Find the usb_otg node */ 80 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 81 while (node > 0) { 82 mode = fdt_getprop(blob, node, "dr_mode", NULL); 83 if (mode && strcmp(mode, "otg") == 0) { 84 matched = true; 85 break; 86 } 87 88 node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2"); 89 } 90 91 if (!matched) { 92 /* 93 * With kernel dtb support, rk3288 dwc2 otg node 94 * use the rockchip legacy dwc2 driver "dwc_otg_310" 95 * with the compatible "rockchip,rk3288_usb20_otg". 96 */ 97 node = fdt_node_offset_by_compatible(blob, -1, 98 "rockchip,rk3288_usb20_otg"); 99 if (node > 0) { 100 matched = true; 101 } else { 102 pr_err("Not found usb_otg device\n"); 103 return -ENODEV; 104 } 105 } 106 107 /* Find the usb phy node */ 108 node = fdtdec_lookup_phandle(blob, node, "phys"); 109 if (node <= 0) { 110 pr_err("Not found usbphy device\n"); 111 return -ENODEV; 112 } 113 114 /* Find the usb otg-phy node */ 115 phy_node = fdt_parent_offset(blob, node); 116 if (phy_node <= 0) { 117 pr_err("Not found sub usbphy device\n"); 118 return -ENODEV; 119 } 120 121 grf_base = (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 122 grf_offset = fdtdec_get_addr(blob, node, "reg"); 123 124 /* Pad dwc2_plat_otg_data related to phy */ 125 pdata->phy_of_node = phy_node; 126 pdata->regs_phy = grf_base + grf_offset; 127 128 return 0; 129 } 130 131 void otg_phy_init(struct dwc2_udc *dev) 132 { 133 struct dwc2_plat_otg_data *pdata = dev->pdata; 134 struct rockchip_usb2_phy_cfg *phy_cfg = NULL; 135 struct rockchip_usb2_phy_dt_id *of_id; 136 int i; 137 138 if (!pdata->regs_phy && otg_phy_parse(dev)) { 139 pr_err("otg-phy parse error\n"); 140 return; 141 } 142 143 for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) { 144 of_id = &rockchip_usb2_phy_dt_ids[i]; 145 if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node, 146 of_id->compatible) == 0) { 147 phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data; 148 break; 149 } 150 } 151 if (!phy_cfg) { 152 debug("Can't find device platform data\n"); 153 154 hang(); 155 return; 156 } 157 pdata->priv = phy_cfg; 158 159 /* power up usb phy analog blocks by set siddq 0 */ 160 property_enable(pdata, &phy_cfg->siddq, false); 161 162 /* disable software control */ 163 property_enable(pdata, &phy_cfg->soft_con, false); 164 165 /* reset otg port */ 166 property_enable(pdata, &phy_cfg->port_reset, true); 167 mdelay(1); 168 property_enable(pdata, &phy_cfg->port_reset, false); 169 udelay(1); 170 } 171 172 void otg_phy_off(struct dwc2_udc *dev) 173 { 174 struct dwc2_plat_otg_data *pdata = dev->pdata; 175 struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv; 176 177 if (!pdata->regs_phy && otg_phy_parse(dev)) { 178 pr_err("otg-phy parse error\n"); 179 return; 180 } 181 182 /* enable software control */ 183 property_enable(pdata, &phy_cfg->soft_con, true); 184 /* enter suspend */ 185 property_enable(pdata, &phy_cfg->suspend, true); 186 } 187