1*fab33579SXu Ziyuan /* 2*fab33579SXu Ziyuan * Copyright 2016 Rockchip Electronics Co., Ltd 3*fab33579SXu Ziyuan * 4*fab33579SXu Ziyuan * SPDX-License-Identifier: GPL-2.0+ 5*fab33579SXu Ziyuan */ 6*fab33579SXu Ziyuan 7*fab33579SXu Ziyuan #include <common.h> 8*fab33579SXu Ziyuan #include <asm/io.h> 9*fab33579SXu Ziyuan #include <libfdt.h> 10*fab33579SXu Ziyuan 11*fab33579SXu Ziyuan #include "../gadget/dwc2_udc_otg_priv.h" 12*fab33579SXu Ziyuan 13*fab33579SXu Ziyuan DECLARE_GLOBAL_DATA_PTR; 14*fab33579SXu Ziyuan 15*fab33579SXu Ziyuan #define BIT_WRITEABLE_SHIFT 16 16*fab33579SXu Ziyuan 17*fab33579SXu Ziyuan struct usb2phy_reg { 18*fab33579SXu Ziyuan unsigned int offset; 19*fab33579SXu Ziyuan unsigned int bitend; 20*fab33579SXu Ziyuan unsigned int bitstart; 21*fab33579SXu Ziyuan unsigned int disable; 22*fab33579SXu Ziyuan unsigned int enable; 23*fab33579SXu Ziyuan }; 24*fab33579SXu Ziyuan 25*fab33579SXu Ziyuan /** 26*fab33579SXu Ziyuan * struct rockchip_usb2_phy_cfg: usb-phy port configuration 27*fab33579SXu Ziyuan * @port_reset: usb otg per-port reset register 28*fab33579SXu Ziyuan * @soft_con: software control usb otg register 29*fab33579SXu Ziyuan * @suspend: phy suspend register 30*fab33579SXu Ziyuan */ 31*fab33579SXu Ziyuan struct rockchip_usb2_phy_cfg { 32*fab33579SXu Ziyuan struct usb2phy_reg port_reset; 33*fab33579SXu Ziyuan struct usb2phy_reg soft_con; 34*fab33579SXu Ziyuan struct usb2phy_reg suspend; 35*fab33579SXu Ziyuan }; 36*fab33579SXu Ziyuan 37*fab33579SXu Ziyuan struct rockchip_usb2_phy_dt_id { 38*fab33579SXu Ziyuan char compatible[128]; 39*fab33579SXu Ziyuan const void *data; 40*fab33579SXu Ziyuan }; 41*fab33579SXu Ziyuan 42*fab33579SXu Ziyuan static const struct rockchip_usb2_phy_cfg rk3288_pdata = { 43*fab33579SXu Ziyuan .port_reset = {0x00, 12, 12, 0, 1}, 44*fab33579SXu Ziyuan .soft_con = {0x08, 2, 2, 0, 1}, 45*fab33579SXu Ziyuan .suspend = {0x0c, 5, 0, 0x01, 0x2A}, 46*fab33579SXu Ziyuan }; 47*fab33579SXu Ziyuan 48*fab33579SXu Ziyuan static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = { 49*fab33579SXu Ziyuan { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata }, 50*fab33579SXu Ziyuan {} 51*fab33579SXu Ziyuan }; 52*fab33579SXu Ziyuan 53*fab33579SXu Ziyuan static void property_enable(struct dwc2_plat_otg_data *pdata, 54*fab33579SXu Ziyuan const struct usb2phy_reg *reg, bool en) 55*fab33579SXu Ziyuan { 56*fab33579SXu Ziyuan unsigned int val, mask, tmp; 57*fab33579SXu Ziyuan 58*fab33579SXu Ziyuan tmp = en ? reg->enable : reg->disable; 59*fab33579SXu Ziyuan mask = GENMASK(reg->bitend, reg->bitstart); 60*fab33579SXu Ziyuan val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 61*fab33579SXu Ziyuan 62*fab33579SXu Ziyuan writel(val, pdata->regs_phy + reg->offset); 63*fab33579SXu Ziyuan } 64*fab33579SXu Ziyuan 65*fab33579SXu Ziyuan 66*fab33579SXu Ziyuan void otg_phy_init(struct dwc2_udc *dev) 67*fab33579SXu Ziyuan { 68*fab33579SXu Ziyuan struct dwc2_plat_otg_data *pdata = dev->pdata; 69*fab33579SXu Ziyuan struct rockchip_usb2_phy_cfg *phy_cfg = NULL; 70*fab33579SXu Ziyuan struct rockchip_usb2_phy_dt_id *of_id; 71*fab33579SXu Ziyuan int i; 72*fab33579SXu Ziyuan 73*fab33579SXu Ziyuan for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) { 74*fab33579SXu Ziyuan of_id = &rockchip_usb2_phy_dt_ids[i]; 75*fab33579SXu Ziyuan if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node, 76*fab33579SXu Ziyuan of_id->compatible) == 0) { 77*fab33579SXu Ziyuan phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data; 78*fab33579SXu Ziyuan break; 79*fab33579SXu Ziyuan } 80*fab33579SXu Ziyuan } 81*fab33579SXu Ziyuan if (!phy_cfg) { 82*fab33579SXu Ziyuan debug("Can't find device platform data\n"); 83*fab33579SXu Ziyuan 84*fab33579SXu Ziyuan hang(); 85*fab33579SXu Ziyuan return; 86*fab33579SXu Ziyuan } 87*fab33579SXu Ziyuan pdata->priv = phy_cfg; 88*fab33579SXu Ziyuan /* disable software control */ 89*fab33579SXu Ziyuan property_enable(pdata, &phy_cfg->soft_con, false); 90*fab33579SXu Ziyuan 91*fab33579SXu Ziyuan /* reset otg port */ 92*fab33579SXu Ziyuan property_enable(pdata, &phy_cfg->port_reset, true); 93*fab33579SXu Ziyuan mdelay(1); 94*fab33579SXu Ziyuan property_enable(pdata, &phy_cfg->port_reset, false); 95*fab33579SXu Ziyuan udelay(1); 96*fab33579SXu Ziyuan } 97*fab33579SXu Ziyuan 98*fab33579SXu Ziyuan void otg_phy_off(struct dwc2_udc *dev) 99*fab33579SXu Ziyuan { 100*fab33579SXu Ziyuan struct dwc2_plat_otg_data *pdata = dev->pdata; 101*fab33579SXu Ziyuan struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv; 102*fab33579SXu Ziyuan 103*fab33579SXu Ziyuan /* enable software control */ 104*fab33579SXu Ziyuan property_enable(pdata, &phy_cfg->soft_con, true); 105*fab33579SXu Ziyuan /* enter suspend */ 106*fab33579SXu Ziyuan property_enable(pdata, &phy_cfg->suspend, true); 107*fab33579SXu Ziyuan } 108