1 /* 2 * OMAP USB PHY Support 3 * 4 * (C) Copyright 2013 5 * Texas Instruments, <www.ti.com> 6 * 7 * Author: Dan Murphy <dmurphy@ti.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <usb.h> 14 #include <asm-generic/errno.h> 15 #include <asm/omap_common.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/sys_proto.h> 18 19 #include <linux/compat.h> 20 #include <linux/usb/dwc3.h> 21 #include <linux/usb/xhci-omap.h> 22 23 #include "../host/xhci.h" 24 25 struct usb_dpll_params { 26 u16 m; 27 u8 n; 28 u8 freq:3; 29 u8 sd; 30 u32 mf; 31 }; 32 33 #define NUM_USB_CLKS 6 34 35 static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = { 36 {1250, 5, 4, 20, 0}, /* 12 MHz */ 37 {3125, 20, 4, 20, 0}, /* 16.8 MHz */ 38 {1172, 8, 4, 20, 65537}, /* 19.2 MHz */ 39 {1250, 12, 4, 20, 0}, /* 26 MHz */ 40 {3125, 47, 4, 20, 92843}, /* 38.4 MHz */ 41 {1000, 7, 4, 10, 0}, /* 20 MHz */ 42 }; 43 44 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs) 45 { 46 u32 val; 47 48 writel(SET_PLL_GO, &phy_regs->pll_go); 49 do { 50 val = readl(&phy_regs->pll_status); 51 if (val & PLL_LOCK) 52 break; 53 } while (1); 54 } 55 56 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs) 57 { 58 u32 clk_index = get_sys_clk_index(); 59 u32 val; 60 61 val = readl(&phy_regs->pll_config_1); 62 val &= ~PLL_REGN_MASK; 63 val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT; 64 writel(val, &phy_regs->pll_config_1); 65 66 val = readl(&phy_regs->pll_config_2); 67 val &= ~PLL_SELFREQDCO_MASK; 68 val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT; 69 writel(val, &phy_regs->pll_config_2); 70 71 val = readl(&phy_regs->pll_config_1); 72 val &= ~PLL_REGM_MASK; 73 val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT; 74 writel(val, &phy_regs->pll_config_1); 75 76 val = readl(&phy_regs->pll_config_4); 77 val &= ~PLL_REGM_F_MASK; 78 val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT; 79 writel(val, &phy_regs->pll_config_4); 80 81 val = readl(&phy_regs->pll_config_3); 82 val &= ~PLL_SD_MASK; 83 val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT; 84 writel(val, &phy_regs->pll_config_3); 85 86 omap_usb_dpll_relock(phy_regs); 87 } 88 89 static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs) 90 { 91 u32 rate = get_sys_clk_freq()/1000000; 92 u32 val; 93 94 val = readl((*ctrl)->control_phy_power_usb); 95 val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK); 96 val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON); 97 val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT; 98 99 writel(val, (*ctrl)->control_phy_power_usb); 100 } 101 102 void usb3_phy_power(int on) 103 { 104 u32 val; 105 106 val = readl((*ctrl)->control_phy_power_usb); 107 if (on) { 108 val &= ~USB3_PWRCTL_CLK_CMD_MASK; 109 val |= USB3_PHY_TX_RX_POWERON; 110 } else { 111 val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON); 112 } 113 114 writel(val, (*ctrl)->control_phy_power_usb); 115 } 116 117 void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs) 118 { 119 omap_usb_dpll_lock(phy_regs); 120 121 usb3_phy_partial_powerup(phy_regs); 122 /* 123 * Give enough time for the PHY to partially power-up before 124 * powering it up completely. delay value suggested by the HW 125 * team. 126 */ 127 mdelay(100); 128 usb3_phy_power(1); 129 } 130 131 void omap_enable_phy_clocks(struct omap_xhci *omap) 132 { 133 u32 val; 134 135 /* Setting OCP2SCP1 register */ 136 setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl, 137 OCP2SCP1_CLKCTRL_MODULEMODE_HW); 138 139 /* Turn on 32K AON clk */ 140 setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl, 141 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 142 143 /* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */ 144 writel(0x0, (*prcm)->cm_l3init_clkstctrl); 145 146 val = (USBOTGSS_DMADISABLE | 147 USBOTGSS_STANDBYMODE_SMRT_WKUP | 148 USBOTGSS_IDLEMODE_NOIDLE); 149 writel(val, &omap->otg_wrapper->sysconfig); 150 151 /* Clear the utmi OTG status */ 152 val = readl(&omap->otg_wrapper->utmi_otg_status); 153 writel(val, &omap->otg_wrapper->utmi_otg_status); 154 155 /* Enable interrupts */ 156 writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0); 157 val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN | 158 USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN | 159 USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN | 160 USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN | 161 USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN | 162 USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN | 163 USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN | 164 USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN | 165 USBOTGSS_IRQ_SET_1_OEVT_EN); 166 writel(val, &omap->otg_wrapper->irqenable_set_1); 167 168 /* Clear the IRQ status */ 169 val = readl(&omap->otg_wrapper->irqstatus_1); 170 writel(val, &omap->otg_wrapper->irqstatus_1); 171 val = readl(&omap->otg_wrapper->irqstatus_0); 172 writel(val, &omap->otg_wrapper->irqstatus_0); 173 174 /* Enable the USB OTG Super speed clocks */ 175 val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW); 176 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val); 177 178 }; 179 180 void omap_reset_usb_phy(struct dwc3 *dwc3_reg) 181 { 182 /* Assert USB3 PHY reset */ 183 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 184 185 /* Assert USB2 PHY reset */ 186 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 187 188 mdelay(100); 189 190 /* Clear USB3 PHY reset */ 191 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 192 193 /* Clear USB2 PHY reset */ 194 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 195 196 } 197 198