12731b9a8SJean-Christophe PLAGNIOL-VILLARD /* 22731b9a8SJean-Christophe PLAGNIOL-VILLARD * Mentor USB OTG Core host controller driver. 32731b9a8SJean-Christophe PLAGNIOL-VILLARD * 42731b9a8SJean-Christophe PLAGNIOL-VILLARD * Copyright (c) 2008 Texas Instruments 52731b9a8SJean-Christophe PLAGNIOL-VILLARD * 62731b9a8SJean-Christophe PLAGNIOL-VILLARD * This program is free software; you can redistribute it and/or 72731b9a8SJean-Christophe PLAGNIOL-VILLARD * modify it under the terms of the GNU General Public License as 82731b9a8SJean-Christophe PLAGNIOL-VILLARD * published by the Free Software Foundation; either version 2 of 92731b9a8SJean-Christophe PLAGNIOL-VILLARD * the License, or (at your option) any later version. 102731b9a8SJean-Christophe PLAGNIOL-VILLARD * 112731b9a8SJean-Christophe PLAGNIOL-VILLARD * This program is distributed in the hope that it will be useful, 122731b9a8SJean-Christophe PLAGNIOL-VILLARD * but WITHOUT ANY WARRANTY; without even the implied warranty of 132731b9a8SJean-Christophe PLAGNIOL-VILLARD * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 142731b9a8SJean-Christophe PLAGNIOL-VILLARD * GNU General Public License for more details. 152731b9a8SJean-Christophe PLAGNIOL-VILLARD * 162731b9a8SJean-Christophe PLAGNIOL-VILLARD * You should have received a copy of the GNU General Public License 172731b9a8SJean-Christophe PLAGNIOL-VILLARD * along with this program; if not, write to the Free Software 182731b9a8SJean-Christophe PLAGNIOL-VILLARD * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 192731b9a8SJean-Christophe PLAGNIOL-VILLARD * MA 02111-1307 USA 202731b9a8SJean-Christophe PLAGNIOL-VILLARD * 212731b9a8SJean-Christophe PLAGNIOL-VILLARD * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments 222731b9a8SJean-Christophe PLAGNIOL-VILLARD */ 232731b9a8SJean-Christophe PLAGNIOL-VILLARD 242731b9a8SJean-Christophe PLAGNIOL-VILLARD #ifndef __MUSB_HCD_H__ 252731b9a8SJean-Christophe PLAGNIOL-VILLARD #define __MUSB_HCD_H__ 262731b9a8SJean-Christophe PLAGNIOL-VILLARD 272731b9a8SJean-Christophe PLAGNIOL-VILLARD #include "musb_core.h" 282731b9a8SJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_USB_KEYBOARD 2952cb4d4fSJean-Christophe PLAGNIOL-VILLARD #include <stdio_dev.h> 302731b9a8SJean-Christophe PLAGNIOL-VILLARD extern unsigned char new[]; 312731b9a8SJean-Christophe PLAGNIOL-VILLARD #endif 322731b9a8SJean-Christophe PLAGNIOL-VILLARD 33c3a012ceSBryan Wu #ifndef CONFIG_MUSB_TIMEOUT 34c3a012ceSBryan Wu # define CONFIG_MUSB_TIMEOUT 100000 35c3a012ceSBryan Wu #endif 36c3a012ceSBryan Wu 372731b9a8SJean-Christophe PLAGNIOL-VILLARD /* This defines the endpoint number used for control transfers */ 382731b9a8SJean-Christophe PLAGNIOL-VILLARD #define MUSB_CONTROL_EP 0 392731b9a8SJean-Christophe PLAGNIOL-VILLARD 402731b9a8SJean-Christophe PLAGNIOL-VILLARD /* This defines the endpoint number used for bulk transfer */ 41e608f221SBryan Wu #ifndef MUSB_BULK_EP 422731b9a8SJean-Christophe PLAGNIOL-VILLARD # define MUSB_BULK_EP 1 43e608f221SBryan Wu #endif 442731b9a8SJean-Christophe PLAGNIOL-VILLARD 452731b9a8SJean-Christophe PLAGNIOL-VILLARD /* This defines the endpoint number used for interrupt transfer */ 462731b9a8SJean-Christophe PLAGNIOL-VILLARD #define MUSB_INTR_EP 2 472731b9a8SJean-Christophe PLAGNIOL-VILLARD 482731b9a8SJean-Christophe PLAGNIOL-VILLARD /* Determine the operating speed of MUSB core */ 492731b9a8SJean-Christophe PLAGNIOL-VILLARD #define musb_ishighspeed() \ 502731b9a8SJean-Christophe PLAGNIOL-VILLARD ((readb(&musbr->power) & MUSB_POWER_HSMODE) \ 512731b9a8SJean-Christophe PLAGNIOL-VILLARD >> MUSB_POWER_HSMODE_SHIFT) 522731b9a8SJean-Christophe PLAGNIOL-VILLARD 53*321790f6SBryan Wu #define min_t(type, x, y) \ 54*321790f6SBryan Wu ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) 55*321790f6SBryan Wu 56*321790f6SBryan Wu /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ 57*321790f6SBryan Wu 58*321790f6SBryan Wu /* destination of request */ 59*321790f6SBryan Wu #define RH_INTERFACE 0x01 60*321790f6SBryan Wu #define RH_ENDPOINT 0x02 61*321790f6SBryan Wu #define RH_OTHER 0x03 62*321790f6SBryan Wu 63*321790f6SBryan Wu #define RH_CLASS 0x20 64*321790f6SBryan Wu #define RH_VENDOR 0x40 65*321790f6SBryan Wu 66*321790f6SBryan Wu /* Requests: bRequest << 8 | bmRequestType */ 67*321790f6SBryan Wu #define RH_GET_STATUS 0x0080 68*321790f6SBryan Wu #define RH_CLEAR_FEATURE 0x0100 69*321790f6SBryan Wu #define RH_SET_FEATURE 0x0300 70*321790f6SBryan Wu #define RH_SET_ADDRESS 0x0500 71*321790f6SBryan Wu #define RH_GET_DESCRIPTOR 0x0680 72*321790f6SBryan Wu #define RH_SET_DESCRIPTOR 0x0700 73*321790f6SBryan Wu #define RH_GET_CONFIGURATION 0x0880 74*321790f6SBryan Wu #define RH_SET_CONFIGURATION 0x0900 75*321790f6SBryan Wu #define RH_GET_STATE 0x0280 76*321790f6SBryan Wu #define RH_GET_INTERFACE 0x0A80 77*321790f6SBryan Wu #define RH_SET_INTERFACE 0x0B00 78*321790f6SBryan Wu #define RH_SYNC_FRAME 0x0C80 79*321790f6SBryan Wu /* Our Vendor Specific Request */ 80*321790f6SBryan Wu #define RH_SET_EP 0x2000 81*321790f6SBryan Wu 82*321790f6SBryan Wu /* Hub port features */ 83*321790f6SBryan Wu #define RH_PORT_CONNECTION 0x00 84*321790f6SBryan Wu #define RH_PORT_ENABLE 0x01 85*321790f6SBryan Wu #define RH_PORT_SUSPEND 0x02 86*321790f6SBryan Wu #define RH_PORT_OVER_CURRENT 0x03 87*321790f6SBryan Wu #define RH_PORT_RESET 0x04 88*321790f6SBryan Wu #define RH_PORT_POWER 0x08 89*321790f6SBryan Wu #define RH_PORT_LOW_SPEED 0x09 90*321790f6SBryan Wu 91*321790f6SBryan Wu #define RH_C_PORT_CONNECTION 0x10 92*321790f6SBryan Wu #define RH_C_PORT_ENABLE 0x11 93*321790f6SBryan Wu #define RH_C_PORT_SUSPEND 0x12 94*321790f6SBryan Wu #define RH_C_PORT_OVER_CURRENT 0x13 95*321790f6SBryan Wu #define RH_C_PORT_RESET 0x14 96*321790f6SBryan Wu 97*321790f6SBryan Wu /* Hub features */ 98*321790f6SBryan Wu #define RH_C_HUB_LOCAL_POWER 0x00 99*321790f6SBryan Wu #define RH_C_HUB_OVER_CURRENT 0x01 100*321790f6SBryan Wu 101*321790f6SBryan Wu #define RH_DEVICE_REMOTE_WAKEUP 0x00 102*321790f6SBryan Wu #define RH_ENDPOINT_STALL 0x01 103*321790f6SBryan Wu 104*321790f6SBryan Wu #define RH_ACK 0x01 105*321790f6SBryan Wu #define RH_REQ_ERR -1 106*321790f6SBryan Wu #define RH_NACK 0x00 107*321790f6SBryan Wu 1082731b9a8SJean-Christophe PLAGNIOL-VILLARD /* extern functions */ 1092731b9a8SJean-Christophe PLAGNIOL-VILLARD extern int musb_platform_init(void); 1102731b9a8SJean-Christophe PLAGNIOL-VILLARD extern void musb_platform_deinit(void); 1112731b9a8SJean-Christophe PLAGNIOL-VILLARD 1122731b9a8SJean-Christophe PLAGNIOL-VILLARD #endif /* __MUSB_HCD_H__ */ 113