1 /* 2 * Mentor USB OTG Core host controller driver. 3 * 4 * Copyright (c) 2008 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 * 21 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments 22 */ 23 24 #include <common.h> 25 #include "musb_hcd.h" 26 27 /* MSC control transfers */ 28 #define USB_MSC_BBB_RESET 0xFF 29 #define USB_MSC_BBB_GET_MAX_LUN 0xFE 30 31 /* Endpoint configuration information */ 32 static struct musb_epinfo epinfo[3] = { 33 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */ 34 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */ 35 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */ 36 }; 37 38 /* 39 * This function writes the data toggle value. 40 */ 41 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out) 42 { 43 u16 toggle = usb_gettoggle(dev, ep, dir_out); 44 u16 csr; 45 46 if (dir_out) { 47 if (!toggle) 48 writew(MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); 49 else { 50 csr = readw(&musbr->txcsr); 51 csr |= MUSB_TXCSR_H_WR_DATATOGGLE; 52 writew(csr, &musbr->txcsr); 53 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); 54 writew(csr, &musbr->txcsr); 55 } 56 } else { 57 if (!toggle) 58 writew(MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); 59 else { 60 csr = readw(&musbr->rxcsr); 61 csr |= MUSB_RXCSR_H_WR_DATATOGGLE; 62 writew(csr, &musbr->rxcsr); 63 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); 64 writew(csr, &musbr->rxcsr); 65 } 66 } 67 } 68 69 /* 70 * This function checks if RxStall has occured on the endpoint. If a RxStall 71 * has occured, the RxStall is cleared and 1 is returned. If RxStall has 72 * not occured, 0 is returned. 73 */ 74 static u8 check_stall(u8 ep, u8 dir_out) 75 { 76 u16 csr; 77 78 /* For endpoint 0 */ 79 if (!ep) { 80 csr = readw(&musbr->txcsr); 81 if (csr & MUSB_CSR0_H_RXSTALL) { 82 csr &= ~MUSB_CSR0_H_RXSTALL; 83 writew(csr, &musbr->txcsr); 84 return 1; 85 } 86 } else { /* For non-ep0 */ 87 if (dir_out) { /* is it tx ep */ 88 csr = readw(&musbr->txcsr); 89 if (csr & MUSB_TXCSR_H_RXSTALL) { 90 csr &= ~MUSB_TXCSR_H_RXSTALL; 91 writew(csr, &musbr->txcsr); 92 return 1; 93 } 94 } else { /* is it rx ep */ 95 csr = readw(&musbr->rxcsr); 96 if (csr & MUSB_RXCSR_H_RXSTALL) { 97 csr &= ~MUSB_RXCSR_H_RXSTALL; 98 writew(csr, &musbr->rxcsr); 99 return 1; 100 } 101 } 102 } 103 return 0; 104 } 105 106 /* 107 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout 108 * error and -2 for stall. 109 */ 110 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask) 111 { 112 u16 csr; 113 int result = 1; 114 int timeout = CONFIG_MUSB_TIMEOUT; 115 116 while (result > 0) { 117 csr = readw(&musbr->txcsr); 118 if (csr & MUSB_CSR0_H_ERROR) { 119 csr &= ~MUSB_CSR0_H_ERROR; 120 writew(csr, &musbr->txcsr); 121 dev->status = USB_ST_CRC_ERR; 122 result = -1; 123 break; 124 } 125 126 switch (bit_mask) { 127 case MUSB_CSR0_TXPKTRDY: 128 if (!(csr & MUSB_CSR0_TXPKTRDY)) { 129 if (check_stall(MUSB_CONTROL_EP, 0)) { 130 dev->status = USB_ST_STALLED; 131 result = -2; 132 } else 133 result = 0; 134 } 135 break; 136 137 case MUSB_CSR0_RXPKTRDY: 138 if (check_stall(MUSB_CONTROL_EP, 0)) { 139 dev->status = USB_ST_STALLED; 140 result = -2; 141 } else 142 if (csr & MUSB_CSR0_RXPKTRDY) 143 result = 0; 144 break; 145 146 case MUSB_CSR0_H_REQPKT: 147 if (!(csr & MUSB_CSR0_H_REQPKT)) { 148 if (check_stall(MUSB_CONTROL_EP, 0)) { 149 dev->status = USB_ST_STALLED; 150 result = -2; 151 } else 152 result = 0; 153 } 154 break; 155 } 156 157 /* Check the timeout */ 158 if (--timeout) 159 udelay(1); 160 else { 161 dev->status = USB_ST_CRC_ERR; 162 result = -1; 163 break; 164 } 165 } 166 167 return result; 168 } 169 170 /* 171 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error. 172 */ 173 static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) 174 { 175 u16 csr; 176 int timeout = CONFIG_MUSB_TIMEOUT; 177 178 do { 179 if (check_stall(ep, 1)) { 180 dev->status = USB_ST_STALLED; 181 return 0; 182 } 183 184 csr = readw(&musbr->txcsr); 185 if (csr & MUSB_TXCSR_H_ERROR) { 186 dev->status = USB_ST_CRC_ERR; 187 return 0; 188 } 189 190 /* Check the timeout */ 191 if (--timeout) 192 udelay(1); 193 else { 194 dev->status = USB_ST_CRC_ERR; 195 return -1; 196 } 197 198 } while (csr & MUSB_TXCSR_TXPKTRDY); 199 return 1; 200 } 201 202 /* 203 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error. 204 */ 205 static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep) 206 { 207 u16 csr; 208 int timeout = CONFIG_MUSB_TIMEOUT; 209 210 do { 211 if (check_stall(ep, 0)) { 212 dev->status = USB_ST_STALLED; 213 return 0; 214 } 215 216 csr = readw(&musbr->rxcsr); 217 if (csr & MUSB_RXCSR_H_ERROR) { 218 dev->status = USB_ST_CRC_ERR; 219 return 0; 220 } 221 222 /* Check the timeout */ 223 if (--timeout) 224 udelay(1); 225 else { 226 dev->status = USB_ST_CRC_ERR; 227 return -1; 228 } 229 230 } while (!(csr & MUSB_RXCSR_RXPKTRDY)); 231 return 1; 232 } 233 234 /* 235 * This function performs the setup phase of the control transfer 236 */ 237 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup) 238 { 239 int result; 240 u16 csr; 241 242 /* write the control request to ep0 fifo */ 243 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup); 244 245 /* enable transfer of setup packet */ 246 csr = readw(&musbr->txcsr); 247 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); 248 writew(csr, &musbr->txcsr); 249 250 /* wait until the setup packet is transmitted */ 251 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); 252 dev->act_len = 0; 253 return result; 254 } 255 256 /* 257 * This function handles the control transfer in data phase 258 */ 259 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer) 260 { 261 u16 csr; 262 u32 rxlen = 0; 263 u32 nextlen = 0; 264 u8 maxpktsize = (1 << dev->maxpacketsize) * 8; 265 u8 *rxbuff = (u8 *)buffer; 266 u8 rxedlength; 267 int result; 268 269 while (rxlen < len) { 270 /* Determine the next read length */ 271 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen); 272 273 /* Set the ReqPkt bit */ 274 csr = readw(&musbr->txcsr); 275 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr); 276 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY); 277 if (result < 0) 278 return result; 279 280 /* Actual number of bytes received by usb */ 281 rxedlength = readb(&musbr->rxcount); 282 283 /* Read the data from the RxFIFO */ 284 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]); 285 286 /* Clear the RxPktRdy Bit */ 287 csr = readw(&musbr->txcsr); 288 csr &= ~MUSB_CSR0_RXPKTRDY; 289 writew(csr, &musbr->txcsr); 290 291 /* short packet? */ 292 if (rxedlength != nextlen) { 293 dev->act_len += rxedlength; 294 break; 295 } 296 rxlen += nextlen; 297 dev->act_len = rxlen; 298 } 299 return 0; 300 } 301 302 /* 303 * This function handles the control transfer out data phase 304 */ 305 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) 306 { 307 u16 csr; 308 u32 txlen = 0; 309 u32 nextlen = 0; 310 u8 maxpktsize = (1 << dev->maxpacketsize) * 8; 311 u8 *txbuff = (u8 *)buffer; 312 int result = 0; 313 314 while (txlen < len) { 315 /* Determine the next write length */ 316 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen); 317 318 /* Load the data to send in FIFO */ 319 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]); 320 321 /* Set TXPKTRDY bit */ 322 csr = readw(&musbr->txcsr); 323 writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY, 324 &musbr->txcsr); 325 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); 326 if (result < 0) 327 break; 328 329 txlen += nextlen; 330 dev->act_len = txlen; 331 } 332 return result; 333 } 334 335 /* 336 * This function handles the control transfer out status phase 337 */ 338 static int ctrlreq_out_status_phase(struct usb_device *dev) 339 { 340 u16 csr; 341 int result; 342 343 /* Set the StatusPkt bit */ 344 csr = readw(&musbr->txcsr); 345 csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY | 346 MUSB_CSR0_H_STATUSPKT); 347 writew(csr, &musbr->txcsr); 348 349 /* Wait until TXPKTRDY bit is cleared */ 350 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); 351 return result; 352 } 353 354 /* 355 * This function handles the control transfer in status phase 356 */ 357 static int ctrlreq_in_status_phase(struct usb_device *dev) 358 { 359 u16 csr; 360 int result; 361 362 /* Set the StatusPkt bit and ReqPkt bit */ 363 csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; 364 writew(csr, &musbr->txcsr); 365 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); 366 367 /* clear StatusPkt bit and RxPktRdy bit */ 368 csr = readw(&musbr->txcsr); 369 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); 370 writew(csr, &musbr->txcsr); 371 return result; 372 } 373 374 /* 375 * determines the speed of the device (High/Full/Slow) 376 */ 377 static u8 get_dev_speed(struct usb_device *dev) 378 { 379 return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH : 380 ((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW : 381 MUSB_TYPE_SPEED_FULL); 382 } 383 384 /* 385 * configure the hub address and the port address. 386 */ 387 static void config_hub_port(struct usb_device *dev, u8 ep) 388 { 389 u8 chid; 390 u8 hub; 391 392 /* Find out the nearest parent which is high speed */ 393 while (dev->parent->parent != NULL) 394 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH) 395 dev = dev->parent; 396 else 397 break; 398 399 /* determine the port address at that hub */ 400 hub = dev->parent->devnum; 401 for (chid = 0; chid < USB_MAXCHILDREN; chid++) 402 if (dev->parent->children[chid] == dev) 403 break; 404 405 #ifndef MUSB_NO_MULTIPOINT 406 /* configure the hub address and the port address */ 407 writeb(hub, &musbr->tar[ep].txhubaddr); 408 writeb((chid + 1), &musbr->tar[ep].txhubport); 409 writeb(hub, &musbr->tar[ep].rxhubaddr); 410 writeb((chid + 1), &musbr->tar[ep].rxhubport); 411 #endif 412 } 413 414 /* 415 * do a control transfer 416 */ 417 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 418 int len, struct devrequest *setup) 419 { 420 #ifndef MUSB_NO_MULTIPOINT 421 int devnum = usb_pipedevice(pipe); 422 #endif 423 u16 csr; 424 u8 devspeed; 425 426 /* select control endpoint */ 427 writeb(MUSB_CONTROL_EP, &musbr->index); 428 csr = readw(&musbr->txcsr); 429 430 #ifndef MUSB_NO_MULTIPOINT 431 /* target addr and (for multipoint) hub addr/port */ 432 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr); 433 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr); 434 #endif 435 436 /* configure the hub address and the port number as required */ 437 devspeed = get_dev_speed(dev); 438 if ((musb_ishighspeed()) && (dev->parent != NULL) && 439 (devspeed != MUSB_TYPE_SPEED_HIGH)) { 440 config_hub_port(dev, MUSB_CONTROL_EP); 441 writeb(devspeed << 6, &musbr->txtype); 442 } else { 443 writeb(musb_cfg.musb_speed << 6, &musbr->txtype); 444 #ifndef MUSB_NO_MULTIPOINT 445 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr); 446 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport); 447 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr); 448 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport); 449 #endif 450 } 451 452 /* Control transfer setup phase */ 453 if (ctrlreq_setup_phase(dev, setup) < 0) 454 return 0; 455 456 switch (setup->request) { 457 case USB_REQ_GET_DESCRIPTOR: 458 case USB_REQ_GET_CONFIGURATION: 459 case USB_REQ_GET_INTERFACE: 460 case USB_REQ_GET_STATUS: 461 case USB_MSC_BBB_GET_MAX_LUN: 462 /* control transfer in-data-phase */ 463 if (ctrlreq_in_data_phase(dev, len, buffer) < 0) 464 return 0; 465 /* control transfer out-status-phase */ 466 if (ctrlreq_out_status_phase(dev) < 0) 467 return 0; 468 break; 469 470 case USB_REQ_SET_ADDRESS: 471 case USB_REQ_SET_CONFIGURATION: 472 case USB_REQ_SET_FEATURE: 473 case USB_REQ_SET_INTERFACE: 474 case USB_REQ_CLEAR_FEATURE: 475 case USB_MSC_BBB_RESET: 476 /* control transfer in status phase */ 477 if (ctrlreq_in_status_phase(dev) < 0) 478 return 0; 479 break; 480 481 case USB_REQ_SET_DESCRIPTOR: 482 /* control transfer out data phase */ 483 if (ctrlreq_out_data_phase(dev, len, buffer) < 0) 484 return 0; 485 /* control transfer in status phase */ 486 if (ctrlreq_in_status_phase(dev) < 0) 487 return 0; 488 break; 489 490 default: 491 /* unhandled control transfer */ 492 return -1; 493 } 494 495 dev->status = 0; 496 dev->act_len = len; 497 return len; 498 } 499 500 /* 501 * do a bulk transfer 502 */ 503 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, 504 void *buffer, int len) 505 { 506 int dir_out = usb_pipeout(pipe); 507 int ep = usb_pipeendpoint(pipe); 508 #ifndef MUSB_NO_MULTIPOINT 509 int devnum = usb_pipedevice(pipe); 510 #endif 511 u8 type; 512 u16 csr; 513 u32 txlen = 0; 514 u32 nextlen = 0; 515 u8 devspeed; 516 517 /* select bulk endpoint */ 518 writeb(MUSB_BULK_EP, &musbr->index); 519 520 #ifndef MUSB_NO_MULTIPOINT 521 /* write the address of the device */ 522 if (dir_out) 523 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr); 524 else 525 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr); 526 #endif 527 528 /* configure the hub address and the port number as required */ 529 devspeed = get_dev_speed(dev); 530 if ((musb_ishighspeed()) && (dev->parent != NULL) && 531 (devspeed != MUSB_TYPE_SPEED_HIGH)) { 532 /* 533 * MUSB is in high speed and the destination device is full 534 * speed device. So configure the hub address and port 535 * address registers. 536 */ 537 config_hub_port(dev, MUSB_BULK_EP); 538 } else { 539 #ifndef MUSB_NO_MULTIPOINT 540 if (dir_out) { 541 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr); 542 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport); 543 } else { 544 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr); 545 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport); 546 } 547 #endif 548 devspeed = musb_cfg.musb_speed; 549 } 550 551 /* Write the saved toggle bit value */ 552 write_toggle(dev, ep, dir_out); 553 554 if (dir_out) { /* bulk-out transfer */ 555 /* Program the TxType register */ 556 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | 557 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | 558 (ep & MUSB_TYPE_REMOTE_END); 559 writeb(type, &musbr->txtype); 560 561 /* Write maximum packet size to the TxMaxp register */ 562 writew(dev->epmaxpacketout[ep], &musbr->txmaxp); 563 while (txlen < len) { 564 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ? 565 (len-txlen) : dev->epmaxpacketout[ep]; 566 567 /* Write the data to the FIFO */ 568 write_fifo(MUSB_BULK_EP, nextlen, 569 (void *)(((u8 *)buffer) + txlen)); 570 571 /* Set the TxPktRdy bit */ 572 csr = readw(&musbr->txcsr); 573 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); 574 575 /* Wait until the TxPktRdy bit is cleared */ 576 if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) { 577 readw(&musbr->txcsr); 578 usb_settoggle(dev, ep, dir_out, 579 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); 580 dev->act_len = txlen; 581 return 0; 582 } 583 txlen += nextlen; 584 } 585 586 /* Keep a copy of the data toggle bit */ 587 csr = readw(&musbr->txcsr); 588 usb_settoggle(dev, ep, dir_out, 589 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); 590 } else { /* bulk-in transfer */ 591 /* Write the saved toggle bit value */ 592 write_toggle(dev, ep, dir_out); 593 594 /* Program the RxType register */ 595 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | 596 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | 597 (ep & MUSB_TYPE_REMOTE_END); 598 writeb(type, &musbr->rxtype); 599 600 /* Write the maximum packet size to the RxMaxp register */ 601 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); 602 while (txlen < len) { 603 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? 604 (len-txlen) : dev->epmaxpacketin[ep]; 605 606 /* Set the ReqPkt bit */ 607 csr = readw(&musbr->rxcsr); 608 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); 609 610 /* Wait until the RxPktRdy bit is set */ 611 if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) { 612 csr = readw(&musbr->rxcsr); 613 usb_settoggle(dev, ep, dir_out, 614 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 615 csr &= ~MUSB_RXCSR_RXPKTRDY; 616 writew(csr, &musbr->rxcsr); 617 dev->act_len = txlen; 618 return 0; 619 } 620 621 /* Read the data from the FIFO */ 622 read_fifo(MUSB_BULK_EP, nextlen, 623 (void *)(((u8 *)buffer) + txlen)); 624 625 /* Clear the RxPktRdy bit */ 626 csr = readw(&musbr->rxcsr); 627 csr &= ~MUSB_RXCSR_RXPKTRDY; 628 writew(csr, &musbr->rxcsr); 629 txlen += nextlen; 630 } 631 632 /* Keep a copy of the data toggle bit */ 633 csr = readw(&musbr->rxcsr); 634 usb_settoggle(dev, ep, dir_out, 635 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 636 } 637 638 /* bulk transfer is complete */ 639 dev->status = 0; 640 dev->act_len = len; 641 return 0; 642 } 643 644 /* 645 * This function initializes the usb controller module. 646 */ 647 int usb_lowlevel_init(void) 648 { 649 u8 power; 650 u32 timeout; 651 652 if (musb_platform_init() == -1) 653 return -1; 654 655 /* Configure all the endpoint FIFO's and start usb controller */ 656 musbr = musb_cfg.regs; 657 musb_configure_ep(&epinfo[0], 658 sizeof(epinfo) / sizeof(struct musb_epinfo)); 659 musb_start(); 660 661 /* 662 * Wait until musb is enabled in host mode with a timeout. There 663 * should be a usb device connected. 664 */ 665 timeout = musb_cfg.timeout; 666 while (timeout--) 667 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM) 668 break; 669 670 /* if musb core is not in host mode, then return */ 671 if (!timeout) 672 return -1; 673 674 /* start usb bus reset */ 675 power = readb(&musbr->power); 676 writeb(power | MUSB_POWER_RESET, &musbr->power); 677 678 /* After initiating a usb reset, wait for about 20ms to 30ms */ 679 udelay(30000); 680 681 /* stop usb bus reset */ 682 power = readb(&musbr->power); 683 power &= ~MUSB_POWER_RESET; 684 writeb(power, &musbr->power); 685 686 /* Determine if the connected device is a high/full/low speed device */ 687 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ? 688 MUSB_TYPE_SPEED_HIGH : 689 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ? 690 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW); 691 return 0; 692 } 693 694 /* 695 * This function stops the operation of the davinci usb module. 696 */ 697 int usb_lowlevel_stop(void) 698 { 699 /* Reset the USB module */ 700 musb_platform_deinit(); 701 writeb(0, &musbr->devctl); 702 return 0; 703 } 704 705 /* 706 * This function supports usb interrupt transfers. Currently, usb interrupt 707 * transfers are not supported. 708 */ 709 int submit_int_msg(struct usb_device *dev, unsigned long pipe, 710 void *buffer, int len, int interval) 711 { 712 int dir_out = usb_pipeout(pipe); 713 int ep = usb_pipeendpoint(pipe); 714 #ifndef MUSB_NO_MULTIPOINT 715 int devnum = usb_pipedevice(pipe); 716 #endif 717 u8 type; 718 u16 csr; 719 u32 txlen = 0; 720 u32 nextlen = 0; 721 u8 devspeed; 722 723 /* select interrupt endpoint */ 724 writeb(MUSB_INTR_EP, &musbr->index); 725 726 #ifndef MUSB_NO_MULTIPOINT 727 /* write the address of the device */ 728 if (dir_out) 729 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr); 730 else 731 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr); 732 #endif 733 734 /* configure the hub address and the port number as required */ 735 devspeed = get_dev_speed(dev); 736 if ((musb_ishighspeed()) && (dev->parent != NULL) && 737 (devspeed != MUSB_TYPE_SPEED_HIGH)) { 738 /* 739 * MUSB is in high speed and the destination device is full 740 * speed device. So configure the hub address and port 741 * address registers. 742 */ 743 config_hub_port(dev, MUSB_INTR_EP); 744 } else { 745 #ifndef MUSB_NO_MULTIPOINT 746 if (dir_out) { 747 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr); 748 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport); 749 } else { 750 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr); 751 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport); 752 } 753 #endif 754 devspeed = musb_cfg.musb_speed; 755 } 756 757 /* Write the saved toggle bit value */ 758 write_toggle(dev, ep, dir_out); 759 760 if (!dir_out) { /* intrrupt-in transfer */ 761 /* Write the saved toggle bit value */ 762 write_toggle(dev, ep, dir_out); 763 writeb(interval, &musbr->rxinterval); 764 765 /* Program the RxType register */ 766 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | 767 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) | 768 (ep & MUSB_TYPE_REMOTE_END); 769 writeb(type, &musbr->rxtype); 770 771 /* Write the maximum packet size to the RxMaxp register */ 772 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); 773 774 while (txlen < len) { 775 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? 776 (len-txlen) : dev->epmaxpacketin[ep]; 777 778 /* Set the ReqPkt bit */ 779 csr = readw(&musbr->rxcsr); 780 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); 781 782 /* Wait until the RxPktRdy bit is set */ 783 if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) { 784 csr = readw(&musbr->rxcsr); 785 usb_settoggle(dev, ep, dir_out, 786 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 787 csr &= ~MUSB_RXCSR_RXPKTRDY; 788 writew(csr, &musbr->rxcsr); 789 dev->act_len = txlen; 790 return 0; 791 } 792 793 /* Read the data from the FIFO */ 794 read_fifo(MUSB_INTR_EP, nextlen, 795 (void *)(((u8 *)buffer) + txlen)); 796 797 /* Clear the RxPktRdy bit */ 798 csr = readw(&musbr->rxcsr); 799 csr &= ~MUSB_RXCSR_RXPKTRDY; 800 writew(csr, &musbr->rxcsr); 801 txlen += nextlen; 802 } 803 804 /* Keep a copy of the data toggle bit */ 805 csr = readw(&musbr->rxcsr); 806 usb_settoggle(dev, ep, dir_out, 807 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 808 } 809 810 /* interrupt transfer is complete */ 811 dev->irq_status = 0; 812 dev->irq_act_len = len; 813 dev->irq_handle(dev); 814 dev->status = 0; 815 dev->act_len = len; 816 return 0; 817 } 818 819 820 #ifdef CONFIG_SYS_USB_EVENT_POLL 821 /* 822 * This function polls for USB keyboard data. 823 */ 824 void usb_event_poll() 825 { 826 struct stdio_dev *dev; 827 struct usb_device *usb_kbd_dev; 828 struct usb_interface *iface; 829 struct usb_endpoint_descriptor *ep; 830 int pipe; 831 int maxp; 832 833 /* Get the pointer to USB Keyboard device pointer */ 834 dev = stdio_get_by_name("usbkbd"); 835 usb_kbd_dev = (struct usb_device *)dev->priv; 836 iface = &usb_kbd_dev->config.if_desc[0]; 837 ep = &iface->ep_desc[0]; 838 pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress); 839 840 /* Submit a interrupt transfer request */ 841 maxp = usb_maxpacket(usb_kbd_dev, pipe); 842 usb_submit_int_msg(usb_kbd_dev, pipe, &new[0], 843 maxp > 8 ? 8 : maxp, ep->bInterval); 844 } 845 #endif /* CONFIG_SYS_USB_EVENT_POLL */ 846