xref: /rk3399_rockchip-uboot/drivers/usb/musb/musb_hcd.c (revision 93ceb4790d8daea992cdebf2c75434d73df9c028)
12731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
22731b9a8SJean-Christophe PLAGNIOL-VILLARD  * Mentor USB OTG Core host controller driver.
32731b9a8SJean-Christophe PLAGNIOL-VILLARD  *
42731b9a8SJean-Christophe PLAGNIOL-VILLARD  * Copyright (c) 2008 Texas Instruments
52731b9a8SJean-Christophe PLAGNIOL-VILLARD  *
62731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This program is free software; you can redistribute it and/or
72731b9a8SJean-Christophe PLAGNIOL-VILLARD  * modify it under the terms of the GNU General Public License as
82731b9a8SJean-Christophe PLAGNIOL-VILLARD  * published by the Free Software Foundation; either version 2 of
92731b9a8SJean-Christophe PLAGNIOL-VILLARD  * the License, or (at your option) any later version.
102731b9a8SJean-Christophe PLAGNIOL-VILLARD  *
112731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This program is distributed in the hope that it will be useful,
122731b9a8SJean-Christophe PLAGNIOL-VILLARD  * but WITHOUT ANY WARRANTY; without even the implied warranty of
132731b9a8SJean-Christophe PLAGNIOL-VILLARD  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
142731b9a8SJean-Christophe PLAGNIOL-VILLARD  * GNU General Public License for more details.
152731b9a8SJean-Christophe PLAGNIOL-VILLARD  *
162731b9a8SJean-Christophe PLAGNIOL-VILLARD  * You should have received a copy of the GNU General Public License
172731b9a8SJean-Christophe PLAGNIOL-VILLARD  * along with this program; if not, write to the Free Software
182731b9a8SJean-Christophe PLAGNIOL-VILLARD  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
192731b9a8SJean-Christophe PLAGNIOL-VILLARD  * MA 02111-1307 USA
202731b9a8SJean-Christophe PLAGNIOL-VILLARD  *
212731b9a8SJean-Christophe PLAGNIOL-VILLARD  * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
222731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
232731b9a8SJean-Christophe PLAGNIOL-VILLARD 
242731b9a8SJean-Christophe PLAGNIOL-VILLARD #include <common.h>
252731b9a8SJean-Christophe PLAGNIOL-VILLARD #include "musb_hcd.h"
262731b9a8SJean-Christophe PLAGNIOL-VILLARD 
272731b9a8SJean-Christophe PLAGNIOL-VILLARD /* MSC control transfers */
282731b9a8SJean-Christophe PLAGNIOL-VILLARD #define USB_MSC_BBB_RESET 	0xFF
292731b9a8SJean-Christophe PLAGNIOL-VILLARD #define USB_MSC_BBB_GET_MAX_LUN	0xFE
302731b9a8SJean-Christophe PLAGNIOL-VILLARD 
312731b9a8SJean-Christophe PLAGNIOL-VILLARD /* Endpoint configuration information */
322731b9a8SJean-Christophe PLAGNIOL-VILLARD static struct musb_epinfo epinfo[3] = {
332731b9a8SJean-Christophe PLAGNIOL-VILLARD 	{MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
342731b9a8SJean-Christophe PLAGNIOL-VILLARD 	{MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In  - 512 Bytes */
352731b9a8SJean-Christophe PLAGNIOL-VILLARD 	{MUSB_INTR_EP, 0, 64}   /* EP2 - Interrupt IN - 64 Bytes */
362731b9a8SJean-Christophe PLAGNIOL-VILLARD };
372731b9a8SJean-Christophe PLAGNIOL-VILLARD 
38321790f6SBryan Wu /* --- Virtual Root Hub ---------------------------------------------------- */
39321790f6SBryan Wu #ifdef MUSB_NO_MULTIPOINT
40321790f6SBryan Wu static int rh_devnum;
41321790f6SBryan Wu static u32 port_status;
42321790f6SBryan Wu 
43321790f6SBryan Wu /* Device descriptor */
44321790f6SBryan Wu static u8 root_hub_dev_des[] = {
45321790f6SBryan Wu 	0x12,			/*  __u8  bLength; */
46321790f6SBryan Wu 	0x01,			/*  __u8  bDescriptorType; Device */
47321790f6SBryan Wu 	0x00,			/*  __u16 bcdUSB; v1.1 */
48321790f6SBryan Wu 	0x02,
49321790f6SBryan Wu 	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
50321790f6SBryan Wu 	0x00,			/*  __u8  bDeviceSubClass; */
51321790f6SBryan Wu 	0x00,			/*  __u8  bDeviceProtocol; */
52321790f6SBryan Wu 	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
53321790f6SBryan Wu 	0x00,			/*  __u16 idVendor; */
54321790f6SBryan Wu 	0x00,
55321790f6SBryan Wu 	0x00,			/*  __u16 idProduct; */
56321790f6SBryan Wu 	0x00,
57321790f6SBryan Wu 	0x00,			/*  __u16 bcdDevice; */
58321790f6SBryan Wu 	0x00,
59321790f6SBryan Wu 	0x00,			/*  __u8  iManufacturer; */
60321790f6SBryan Wu 	0x01,			/*  __u8  iProduct; */
61321790f6SBryan Wu 	0x00,			/*  __u8  iSerialNumber; */
62321790f6SBryan Wu 	0x01			/*  __u8  bNumConfigurations; */
63321790f6SBryan Wu };
64321790f6SBryan Wu 
65321790f6SBryan Wu /* Configuration descriptor */
66321790f6SBryan Wu static u8 root_hub_config_des[] = {
67321790f6SBryan Wu 	0x09,			/*  __u8  bLength; */
68321790f6SBryan Wu 	0x02,			/*  __u8  bDescriptorType; Configuration */
69321790f6SBryan Wu 	0x19,			/*  __u16 wTotalLength; */
70321790f6SBryan Wu 	0x00,
71321790f6SBryan Wu 	0x01,			/*  __u8  bNumInterfaces; */
72321790f6SBryan Wu 	0x01,			/*  __u8  bConfigurationValue; */
73321790f6SBryan Wu 	0x00,			/*  __u8  iConfiguration; */
74321790f6SBryan Wu 	0x40,			/*  __u8  bmAttributes;
75321790f6SBryan Wu 				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
76321790f6SBryan Wu 	0x00,			/*  __u8  MaxPower; */
77321790f6SBryan Wu 
78321790f6SBryan Wu 	/* interface */
79321790f6SBryan Wu 	0x09,			/*  __u8  if_bLength; */
80321790f6SBryan Wu 	0x04,			/*  __u8  if_bDescriptorType; Interface */
81321790f6SBryan Wu 	0x00,			/*  __u8  if_bInterfaceNumber; */
82321790f6SBryan Wu 	0x00,			/*  __u8  if_bAlternateSetting; */
83321790f6SBryan Wu 	0x01,			/*  __u8  if_bNumEndpoints; */
84321790f6SBryan Wu 	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
85321790f6SBryan Wu 	0x00,			/*  __u8  if_bInterfaceSubClass; */
86321790f6SBryan Wu 	0x00,			/*  __u8  if_bInterfaceProtocol; */
87321790f6SBryan Wu 	0x00,			/*  __u8  if_iInterface; */
88321790f6SBryan Wu 
89321790f6SBryan Wu 	/* endpoint */
90321790f6SBryan Wu 	0x07,			/*  __u8  ep_bLength; */
91321790f6SBryan Wu 	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
92321790f6SBryan Wu 	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
93321790f6SBryan Wu 	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
94321790f6SBryan Wu 	0x00,			/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
95321790f6SBryan Wu 	0x02,
96321790f6SBryan Wu 	0xff			/*  __u8  ep_bInterval; 255 ms */
97321790f6SBryan Wu };
98321790f6SBryan Wu 
99321790f6SBryan Wu static unsigned char root_hub_str_index0[] = {
100321790f6SBryan Wu 	0x04,			/*  __u8  bLength; */
101321790f6SBryan Wu 	0x03,			/*  __u8  bDescriptorType; String-descriptor */
102321790f6SBryan Wu 	0x09,			/*  __u8  lang ID */
103321790f6SBryan Wu 	0x04,			/*  __u8  lang ID */
104321790f6SBryan Wu };
105321790f6SBryan Wu 
106321790f6SBryan Wu static unsigned char root_hub_str_index1[] = {
107321790f6SBryan Wu 	0x1c,			/*  __u8  bLength; */
108321790f6SBryan Wu 	0x03,			/*  __u8  bDescriptorType; String-descriptor */
109321790f6SBryan Wu 	'M',			/*  __u8  Unicode */
110321790f6SBryan Wu 	0,			/*  __u8  Unicode */
111321790f6SBryan Wu 	'U',			/*  __u8  Unicode */
112321790f6SBryan Wu 	0,			/*  __u8  Unicode */
113321790f6SBryan Wu 	'S',			/*  __u8  Unicode */
114321790f6SBryan Wu 	0,			/*  __u8  Unicode */
115321790f6SBryan Wu 	'B',			/*  __u8  Unicode */
116321790f6SBryan Wu 	0,			/*  __u8  Unicode */
117321790f6SBryan Wu 	' ',			/*  __u8  Unicode */
118321790f6SBryan Wu 	0,			/*  __u8  Unicode */
119321790f6SBryan Wu 	'R',			/*  __u8  Unicode */
120321790f6SBryan Wu 	0,			/*  __u8  Unicode */
121321790f6SBryan Wu 	'o',			/*  __u8  Unicode */
122321790f6SBryan Wu 	0,			/*  __u8  Unicode */
123321790f6SBryan Wu 	'o',			/*  __u8  Unicode */
124321790f6SBryan Wu 	0,			/*  __u8  Unicode */
125321790f6SBryan Wu 	't',			/*  __u8  Unicode */
126321790f6SBryan Wu 	0,			/*  __u8  Unicode */
127321790f6SBryan Wu 	' ',			/*  __u8  Unicode */
128321790f6SBryan Wu 	0,			/*  __u8  Unicode */
129321790f6SBryan Wu 	'H',			/*  __u8  Unicode */
130321790f6SBryan Wu 	0,			/*  __u8  Unicode */
131321790f6SBryan Wu 	'u',			/*  __u8  Unicode */
132321790f6SBryan Wu 	0,			/*  __u8  Unicode */
133321790f6SBryan Wu 	'b',			/*  __u8  Unicode */
134321790f6SBryan Wu 	0,			/*  __u8  Unicode */
135321790f6SBryan Wu };
136321790f6SBryan Wu #endif
137321790f6SBryan Wu 
1382731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
1392731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function writes the data toggle value.
1402731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
1412731b9a8SJean-Christophe PLAGNIOL-VILLARD static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
1422731b9a8SJean-Christophe PLAGNIOL-VILLARD {
1432731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 toggle = usb_gettoggle(dev, ep, dir_out);
1442731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
1452731b9a8SJean-Christophe PLAGNIOL-VILLARD 
1462731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if (dir_out) {
1472731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (!toggle)
1482731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
1492731b9a8SJean-Christophe PLAGNIOL-VILLARD 		else {
1502731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr = readw(&musbr->txcsr);
1512731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
1522731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(csr, &musbr->txcsr);
1532731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
1542731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(csr, &musbr->txcsr);
1552731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
1562731b9a8SJean-Christophe PLAGNIOL-VILLARD 	} else {
1572731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (!toggle)
1582731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
1592731b9a8SJean-Christophe PLAGNIOL-VILLARD 		else {
1602731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr = readw(&musbr->rxcsr);
1612731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
1622731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(csr, &musbr->rxcsr);
1632731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
1642731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(csr, &musbr->rxcsr);
1652731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
1662731b9a8SJean-Christophe PLAGNIOL-VILLARD 	}
1672731b9a8SJean-Christophe PLAGNIOL-VILLARD }
1682731b9a8SJean-Christophe PLAGNIOL-VILLARD 
1692731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
1702731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function checks if RxStall has occured on the endpoint. If a RxStall
1712731b9a8SJean-Christophe PLAGNIOL-VILLARD  * has occured, the RxStall is cleared and 1 is returned. If RxStall has
1722731b9a8SJean-Christophe PLAGNIOL-VILLARD  * not occured, 0 is returned.
1732731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
1742731b9a8SJean-Christophe PLAGNIOL-VILLARD static u8 check_stall(u8 ep, u8 dir_out)
1752731b9a8SJean-Christophe PLAGNIOL-VILLARD {
1762731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
1772731b9a8SJean-Christophe PLAGNIOL-VILLARD 
1782731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* For endpoint 0 */
1792731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if (!ep) {
1802731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr = readw(&musbr->txcsr);
1812731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (csr & MUSB_CSR0_H_RXSTALL) {
1822731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr &= ~MUSB_CSR0_H_RXSTALL;
1832731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(csr, &musbr->txcsr);
1842731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return 1;
1852731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
1862731b9a8SJean-Christophe PLAGNIOL-VILLARD 	} else { /* For non-ep0 */
1872731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (dir_out) { /* is it tx ep */
1882731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr = readw(&musbr->txcsr);
1892731b9a8SJean-Christophe PLAGNIOL-VILLARD 			if (csr & MUSB_TXCSR_H_RXSTALL) {
1902731b9a8SJean-Christophe PLAGNIOL-VILLARD 				csr &= ~MUSB_TXCSR_H_RXSTALL;
1912731b9a8SJean-Christophe PLAGNIOL-VILLARD 				writew(csr, &musbr->txcsr);
1922731b9a8SJean-Christophe PLAGNIOL-VILLARD 				return 1;
1932731b9a8SJean-Christophe PLAGNIOL-VILLARD 			}
1942731b9a8SJean-Christophe PLAGNIOL-VILLARD 		} else { /* is it rx ep */
1952731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr = readw(&musbr->rxcsr);
1962731b9a8SJean-Christophe PLAGNIOL-VILLARD 			if (csr & MUSB_RXCSR_H_RXSTALL) {
1972731b9a8SJean-Christophe PLAGNIOL-VILLARD 				csr &= ~MUSB_RXCSR_H_RXSTALL;
1982731b9a8SJean-Christophe PLAGNIOL-VILLARD 				writew(csr, &musbr->rxcsr);
1992731b9a8SJean-Christophe PLAGNIOL-VILLARD 				return 1;
2002731b9a8SJean-Christophe PLAGNIOL-VILLARD 			}
2012731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
2022731b9a8SJean-Christophe PLAGNIOL-VILLARD 	}
2032731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return 0;
2042731b9a8SJean-Christophe PLAGNIOL-VILLARD }
2052731b9a8SJean-Christophe PLAGNIOL-VILLARD 
2062731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
2072731b9a8SJean-Christophe PLAGNIOL-VILLARD  * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
2082731b9a8SJean-Christophe PLAGNIOL-VILLARD  * error and -2 for stall.
2092731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
2102731b9a8SJean-Christophe PLAGNIOL-VILLARD static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
2112731b9a8SJean-Christophe PLAGNIOL-VILLARD {
2122731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
2132731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int result = 1;
214c3a012ceSBryan Wu 	int timeout = CONFIG_MUSB_TIMEOUT;
2152731b9a8SJean-Christophe PLAGNIOL-VILLARD 
2162731b9a8SJean-Christophe PLAGNIOL-VILLARD 	while (result > 0) {
2172731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr = readw(&musbr->txcsr);
2182731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (csr & MUSB_CSR0_H_ERROR) {
2192731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr &= ~MUSB_CSR0_H_ERROR;
2202731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(csr, &musbr->txcsr);
2212731b9a8SJean-Christophe PLAGNIOL-VILLARD 			dev->status = USB_ST_CRC_ERR;
2222731b9a8SJean-Christophe PLAGNIOL-VILLARD 			result = -1;
2232731b9a8SJean-Christophe PLAGNIOL-VILLARD 			break;
2242731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
2252731b9a8SJean-Christophe PLAGNIOL-VILLARD 
2262731b9a8SJean-Christophe PLAGNIOL-VILLARD 		switch (bit_mask) {
2272731b9a8SJean-Christophe PLAGNIOL-VILLARD 		case MUSB_CSR0_TXPKTRDY:
2282731b9a8SJean-Christophe PLAGNIOL-VILLARD 			if (!(csr & MUSB_CSR0_TXPKTRDY)) {
2292731b9a8SJean-Christophe PLAGNIOL-VILLARD 				if (check_stall(MUSB_CONTROL_EP, 0)) {
2302731b9a8SJean-Christophe PLAGNIOL-VILLARD 					dev->status = USB_ST_STALLED;
2312731b9a8SJean-Christophe PLAGNIOL-VILLARD 					result = -2;
2322731b9a8SJean-Christophe PLAGNIOL-VILLARD 				} else
2332731b9a8SJean-Christophe PLAGNIOL-VILLARD 					result = 0;
2342731b9a8SJean-Christophe PLAGNIOL-VILLARD 			}
2352731b9a8SJean-Christophe PLAGNIOL-VILLARD 			break;
2362731b9a8SJean-Christophe PLAGNIOL-VILLARD 
2372731b9a8SJean-Christophe PLAGNIOL-VILLARD 		case MUSB_CSR0_RXPKTRDY:
2382731b9a8SJean-Christophe PLAGNIOL-VILLARD 			if (check_stall(MUSB_CONTROL_EP, 0)) {
2392731b9a8SJean-Christophe PLAGNIOL-VILLARD 				dev->status = USB_ST_STALLED;
2402731b9a8SJean-Christophe PLAGNIOL-VILLARD 				result = -2;
2412731b9a8SJean-Christophe PLAGNIOL-VILLARD 			} else
2422731b9a8SJean-Christophe PLAGNIOL-VILLARD 				if (csr & MUSB_CSR0_RXPKTRDY)
2432731b9a8SJean-Christophe PLAGNIOL-VILLARD 					result = 0;
2442731b9a8SJean-Christophe PLAGNIOL-VILLARD 			break;
2452731b9a8SJean-Christophe PLAGNIOL-VILLARD 
2462731b9a8SJean-Christophe PLAGNIOL-VILLARD 		case MUSB_CSR0_H_REQPKT:
2472731b9a8SJean-Christophe PLAGNIOL-VILLARD 			if (!(csr & MUSB_CSR0_H_REQPKT)) {
2482731b9a8SJean-Christophe PLAGNIOL-VILLARD 				if (check_stall(MUSB_CONTROL_EP, 0)) {
2492731b9a8SJean-Christophe PLAGNIOL-VILLARD 					dev->status = USB_ST_STALLED;
2502731b9a8SJean-Christophe PLAGNIOL-VILLARD 					result = -2;
2512731b9a8SJean-Christophe PLAGNIOL-VILLARD 				} else
2522731b9a8SJean-Christophe PLAGNIOL-VILLARD 					result = 0;
2532731b9a8SJean-Christophe PLAGNIOL-VILLARD 			}
2542731b9a8SJean-Christophe PLAGNIOL-VILLARD 			break;
2552731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
256c3a012ceSBryan Wu 
257c3a012ceSBryan Wu 		/* Check the timeout */
258c3a012ceSBryan Wu 		if (--timeout)
259c3a012ceSBryan Wu 			udelay(1);
260c3a012ceSBryan Wu 		else {
261c3a012ceSBryan Wu 			dev->status = USB_ST_CRC_ERR;
262c3a012ceSBryan Wu 			result = -1;
263c3a012ceSBryan Wu 			break;
2642731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
265c3a012ceSBryan Wu 	}
266c3a012ceSBryan Wu 
2672731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return result;
2682731b9a8SJean-Christophe PLAGNIOL-VILLARD }
2692731b9a8SJean-Christophe PLAGNIOL-VILLARD 
2702731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
2712731b9a8SJean-Christophe PLAGNIOL-VILLARD  * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
2722731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
2732731b9a8SJean-Christophe PLAGNIOL-VILLARD static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
2742731b9a8SJean-Christophe PLAGNIOL-VILLARD {
2752731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
276c3a012ceSBryan Wu 	int timeout = CONFIG_MUSB_TIMEOUT;
2772731b9a8SJean-Christophe PLAGNIOL-VILLARD 
2782731b9a8SJean-Christophe PLAGNIOL-VILLARD 	do {
2792731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (check_stall(ep, 1)) {
2802731b9a8SJean-Christophe PLAGNIOL-VILLARD 			dev->status = USB_ST_STALLED;
2812731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return 0;
2822731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
2832731b9a8SJean-Christophe PLAGNIOL-VILLARD 
2842731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr = readw(&musbr->txcsr);
2852731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (csr & MUSB_TXCSR_H_ERROR) {
2862731b9a8SJean-Christophe PLAGNIOL-VILLARD 			dev->status = USB_ST_CRC_ERR;
2872731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return 0;
2882731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
289c3a012ceSBryan Wu 
290c3a012ceSBryan Wu 		/* Check the timeout */
291c3a012ceSBryan Wu 		if (--timeout)
292c3a012ceSBryan Wu 			udelay(1);
293c3a012ceSBryan Wu 		else {
294c3a012ceSBryan Wu 			dev->status = USB_ST_CRC_ERR;
295c3a012ceSBryan Wu 			return -1;
296c3a012ceSBryan Wu 		}
297c3a012ceSBryan Wu 
2982731b9a8SJean-Christophe PLAGNIOL-VILLARD 	} while (csr & MUSB_TXCSR_TXPKTRDY);
2992731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return 1;
3002731b9a8SJean-Christophe PLAGNIOL-VILLARD }
3012731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3022731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
3032731b9a8SJean-Christophe PLAGNIOL-VILLARD  * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
3042731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
3052731b9a8SJean-Christophe PLAGNIOL-VILLARD static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
3062731b9a8SJean-Christophe PLAGNIOL-VILLARD {
3072731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
308c3a012ceSBryan Wu 	int timeout = CONFIG_MUSB_TIMEOUT;
3092731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3102731b9a8SJean-Christophe PLAGNIOL-VILLARD 	do {
3112731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (check_stall(ep, 0)) {
3122731b9a8SJean-Christophe PLAGNIOL-VILLARD 			dev->status = USB_ST_STALLED;
3132731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return 0;
3142731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
3152731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3162731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr = readw(&musbr->rxcsr);
3172731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (csr & MUSB_RXCSR_H_ERROR) {
3182731b9a8SJean-Christophe PLAGNIOL-VILLARD 			dev->status = USB_ST_CRC_ERR;
3192731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return 0;
3202731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
321c3a012ceSBryan Wu 
322c3a012ceSBryan Wu 		/* Check the timeout */
323c3a012ceSBryan Wu 		if (--timeout)
324c3a012ceSBryan Wu 			udelay(1);
325c3a012ceSBryan Wu 		else {
326c3a012ceSBryan Wu 			dev->status = USB_ST_CRC_ERR;
327c3a012ceSBryan Wu 			return -1;
328c3a012ceSBryan Wu 		}
329c3a012ceSBryan Wu 
3302731b9a8SJean-Christophe PLAGNIOL-VILLARD 	} while (!(csr & MUSB_RXCSR_RXPKTRDY));
3312731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return 1;
3322731b9a8SJean-Christophe PLAGNIOL-VILLARD }
3332731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3342731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
3352731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function performs the setup phase of the control transfer
3362731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
3372731b9a8SJean-Christophe PLAGNIOL-VILLARD static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
3382731b9a8SJean-Christophe PLAGNIOL-VILLARD {
3392731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int result;
3402731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
3412731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3422731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* write the control request to ep0 fifo */
3432731b9a8SJean-Christophe PLAGNIOL-VILLARD 	write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
3442731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3452731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* enable transfer of setup packet */
3462731b9a8SJean-Christophe PLAGNIOL-VILLARD 	csr = readw(&musbr->txcsr);
3472731b9a8SJean-Christophe PLAGNIOL-VILLARD 	csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
3482731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writew(csr, &musbr->txcsr);
3492731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3502731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* wait until the setup packet is transmitted */
3512731b9a8SJean-Christophe PLAGNIOL-VILLARD 	result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
3522731b9a8SJean-Christophe PLAGNIOL-VILLARD 	dev->act_len = 0;
3532731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return result;
3542731b9a8SJean-Christophe PLAGNIOL-VILLARD }
3552731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3562731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
3572731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function handles the control transfer in data phase
3582731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
3592731b9a8SJean-Christophe PLAGNIOL-VILLARD static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
3602731b9a8SJean-Christophe PLAGNIOL-VILLARD {
3612731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
3622731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u32 rxlen = 0;
3632731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u32 nextlen = 0;
3642731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  maxpktsize = (1 << dev->maxpacketsize) * 8;
3652731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  *rxbuff = (u8 *)buffer;
3662731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  rxedlength;
3672731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int result;
3682731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3692731b9a8SJean-Christophe PLAGNIOL-VILLARD 	while (rxlen < len) {
3702731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Determine the next read length */
3712731b9a8SJean-Christophe PLAGNIOL-VILLARD 		nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
3722731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3732731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Set the ReqPkt bit */
3742731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr = readw(&musbr->txcsr);
3752731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
3762731b9a8SJean-Christophe PLAGNIOL-VILLARD 		result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
3772731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (result < 0)
3782731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return result;
3792731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3802731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Actual number of bytes received by usb */
3812731b9a8SJean-Christophe PLAGNIOL-VILLARD 		rxedlength = readb(&musbr->rxcount);
3822731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3832731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Read the data from the RxFIFO */
3842731b9a8SJean-Christophe PLAGNIOL-VILLARD 		read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
3852731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3862731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Clear the RxPktRdy Bit */
3872731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr = readw(&musbr->txcsr);
3882731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr &= ~MUSB_CSR0_RXPKTRDY;
3892731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writew(csr, &musbr->txcsr);
3902731b9a8SJean-Christophe PLAGNIOL-VILLARD 
3912731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* short packet? */
3922731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (rxedlength != nextlen) {
3932731b9a8SJean-Christophe PLAGNIOL-VILLARD 			dev->act_len += rxedlength;
3942731b9a8SJean-Christophe PLAGNIOL-VILLARD 			break;
3952731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
3962731b9a8SJean-Christophe PLAGNIOL-VILLARD 		rxlen += nextlen;
3972731b9a8SJean-Christophe PLAGNIOL-VILLARD 		dev->act_len = rxlen;
3982731b9a8SJean-Christophe PLAGNIOL-VILLARD 	}
3992731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return 0;
4002731b9a8SJean-Christophe PLAGNIOL-VILLARD }
4012731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4022731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
4032731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function handles the control transfer out data phase
4042731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
4052731b9a8SJean-Christophe PLAGNIOL-VILLARD static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
4062731b9a8SJean-Christophe PLAGNIOL-VILLARD {
4072731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
4082731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u32 txlen = 0;
4092731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u32 nextlen = 0;
4102731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  maxpktsize = (1 << dev->maxpacketsize) * 8;
4112731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  *txbuff = (u8 *)buffer;
4122731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int result = 0;
4132731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4142731b9a8SJean-Christophe PLAGNIOL-VILLARD 	while (txlen < len) {
4152731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Determine the next write length */
4162731b9a8SJean-Christophe PLAGNIOL-VILLARD 		nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
4172731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4182731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Load the data to send in FIFO */
4192731b9a8SJean-Christophe PLAGNIOL-VILLARD 		write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
4202731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4212731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Set TXPKTRDY bit */
4222731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr = readw(&musbr->txcsr);
4232731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY,
4242731b9a8SJean-Christophe PLAGNIOL-VILLARD 					&musbr->txcsr);
4252731b9a8SJean-Christophe PLAGNIOL-VILLARD 		result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
4262731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (result < 0)
4272731b9a8SJean-Christophe PLAGNIOL-VILLARD 			break;
4282731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4292731b9a8SJean-Christophe PLAGNIOL-VILLARD 		txlen += nextlen;
4302731b9a8SJean-Christophe PLAGNIOL-VILLARD 		dev->act_len = txlen;
4312731b9a8SJean-Christophe PLAGNIOL-VILLARD 	}
4322731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return result;
4332731b9a8SJean-Christophe PLAGNIOL-VILLARD }
4342731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4352731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
4362731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function handles the control transfer out status phase
4372731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
4382731b9a8SJean-Christophe PLAGNIOL-VILLARD static int ctrlreq_out_status_phase(struct usb_device *dev)
4392731b9a8SJean-Christophe PLAGNIOL-VILLARD {
4402731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
4412731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int result;
4422731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4432731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Set the StatusPkt bit */
4442731b9a8SJean-Christophe PLAGNIOL-VILLARD 	csr = readw(&musbr->txcsr);
4452731b9a8SJean-Christophe PLAGNIOL-VILLARD 	csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY |
4462731b9a8SJean-Christophe PLAGNIOL-VILLARD 			MUSB_CSR0_H_STATUSPKT);
4472731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writew(csr, &musbr->txcsr);
4482731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4492731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Wait until TXPKTRDY bit is cleared */
4502731b9a8SJean-Christophe PLAGNIOL-VILLARD 	result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
4512731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return result;
4522731b9a8SJean-Christophe PLAGNIOL-VILLARD }
4532731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4542731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
4552731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function handles the control transfer in status phase
4562731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
4572731b9a8SJean-Christophe PLAGNIOL-VILLARD static int ctrlreq_in_status_phase(struct usb_device *dev)
4582731b9a8SJean-Christophe PLAGNIOL-VILLARD {
4592731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
4602731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int result;
4612731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4622731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Set the StatusPkt bit and ReqPkt bit */
4632731b9a8SJean-Christophe PLAGNIOL-VILLARD 	csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
4642731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writew(csr, &musbr->txcsr);
4652731b9a8SJean-Christophe PLAGNIOL-VILLARD 	result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
4662731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4672731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* clear StatusPkt bit and RxPktRdy bit */
4682731b9a8SJean-Christophe PLAGNIOL-VILLARD 	csr = readw(&musbr->txcsr);
4692731b9a8SJean-Christophe PLAGNIOL-VILLARD 	csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
4702731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writew(csr, &musbr->txcsr);
4712731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return result;
4722731b9a8SJean-Christophe PLAGNIOL-VILLARD }
4732731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4742731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
4752731b9a8SJean-Christophe PLAGNIOL-VILLARD  * determines the speed of the device (High/Full/Slow)
4762731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
4772731b9a8SJean-Christophe PLAGNIOL-VILLARD static u8 get_dev_speed(struct usb_device *dev)
4782731b9a8SJean-Christophe PLAGNIOL-VILLARD {
4792731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
4802731b9a8SJean-Christophe PLAGNIOL-VILLARD 		((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
4812731b9a8SJean-Christophe PLAGNIOL-VILLARD 						MUSB_TYPE_SPEED_FULL);
4822731b9a8SJean-Christophe PLAGNIOL-VILLARD }
4832731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4842731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
4852731b9a8SJean-Christophe PLAGNIOL-VILLARD  * configure the hub address and the port address.
4862731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
4872731b9a8SJean-Christophe PLAGNIOL-VILLARD static void config_hub_port(struct usb_device *dev, u8 ep)
4882731b9a8SJean-Christophe PLAGNIOL-VILLARD {
4892731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8 chid;
4902731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8 hub;
4912731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4922731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Find out the nearest parent which is high speed */
4932731b9a8SJean-Christophe PLAGNIOL-VILLARD 	while (dev->parent->parent != NULL)
4942731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (get_dev_speed(dev->parent) !=  MUSB_TYPE_SPEED_HIGH)
4952731b9a8SJean-Christophe PLAGNIOL-VILLARD 			dev = dev->parent;
4962731b9a8SJean-Christophe PLAGNIOL-VILLARD 		else
4972731b9a8SJean-Christophe PLAGNIOL-VILLARD 			break;
4982731b9a8SJean-Christophe PLAGNIOL-VILLARD 
4992731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* determine the port address at that hub */
5002731b9a8SJean-Christophe PLAGNIOL-VILLARD 	hub = dev->parent->devnum;
5012731b9a8SJean-Christophe PLAGNIOL-VILLARD 	for (chid = 0; chid < USB_MAXCHILDREN; chid++)
5022731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (dev->parent->children[chid] == dev)
5032731b9a8SJean-Christophe PLAGNIOL-VILLARD 			break;
5042731b9a8SJean-Christophe PLAGNIOL-VILLARD 
5058868fd44SBryan Wu #ifndef MUSB_NO_MULTIPOINT
5062731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* configure the hub address and the port address */
5072731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb(hub, &musbr->tar[ep].txhubaddr);
5082731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb((chid + 1), &musbr->tar[ep].txhubport);
5092731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb(hub, &musbr->tar[ep].rxhubaddr);
5102731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb((chid + 1), &musbr->tar[ep].rxhubport);
5118868fd44SBryan Wu #endif
5122731b9a8SJean-Christophe PLAGNIOL-VILLARD }
5132731b9a8SJean-Christophe PLAGNIOL-VILLARD 
514321790f6SBryan Wu #ifdef MUSB_NO_MULTIPOINT
515321790f6SBryan Wu 
516321790f6SBryan Wu static void musb_port_reset(int do_reset)
517321790f6SBryan Wu {
518321790f6SBryan Wu 	u8 power = readb(&musbr->power);
519321790f6SBryan Wu 
520321790f6SBryan Wu 	if (do_reset) {
521321790f6SBryan Wu 		power &= 0xf0;
522321790f6SBryan Wu 		writeb(power | MUSB_POWER_RESET, &musbr->power);
523321790f6SBryan Wu 		port_status |= USB_PORT_STAT_RESET;
524321790f6SBryan Wu 		port_status &= ~USB_PORT_STAT_ENABLE;
525321790f6SBryan Wu 		udelay(30000);
526321790f6SBryan Wu 	} else {
527321790f6SBryan Wu 		writeb(power & ~MUSB_POWER_RESET, &musbr->power);
528321790f6SBryan Wu 
529321790f6SBryan Wu 		power = readb(&musbr->power);
530321790f6SBryan Wu 		if (power & MUSB_POWER_HSMODE)
531321790f6SBryan Wu 			port_status |= USB_PORT_STAT_HIGH_SPEED;
532321790f6SBryan Wu 
533321790f6SBryan Wu 		port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
534321790f6SBryan Wu 		port_status |= USB_PORT_STAT_ENABLE
535321790f6SBryan Wu 			| (USB_PORT_STAT_C_RESET << 16)
536321790f6SBryan Wu 			| (USB_PORT_STAT_C_ENABLE << 16);
537321790f6SBryan Wu 	}
538321790f6SBryan Wu }
539321790f6SBryan Wu 
540321790f6SBryan Wu /*
541321790f6SBryan Wu  * root hub control
542321790f6SBryan Wu  */
543321790f6SBryan Wu static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
544321790f6SBryan Wu 			      void *buffer, int transfer_len,
545321790f6SBryan Wu 			      struct devrequest *cmd)
546321790f6SBryan Wu {
547321790f6SBryan Wu 	int leni = transfer_len;
548321790f6SBryan Wu 	int len = 0;
549321790f6SBryan Wu 	int stat = 0;
550321790f6SBryan Wu 	u32 datab[4];
551321790f6SBryan Wu 	u8 *data_buf = (u8 *) datab;
552321790f6SBryan Wu 	u16 bmRType_bReq;
553321790f6SBryan Wu 	u16 wValue;
554321790f6SBryan Wu 	u16 wIndex;
555321790f6SBryan Wu 	u16 wLength;
556321790f6SBryan Wu 	u16 int_usb;
557321790f6SBryan Wu 
558321790f6SBryan Wu 	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
559321790f6SBryan Wu 		debug("Root-Hub submit IRQ: NOT implemented\n");
560321790f6SBryan Wu 		return 0;
561321790f6SBryan Wu 	}
562321790f6SBryan Wu 
563321790f6SBryan Wu 	bmRType_bReq = cmd->requesttype | (cmd->request << 8);
564321790f6SBryan Wu 	wValue = swap_16(cmd->value);
565321790f6SBryan Wu 	wIndex = swap_16(cmd->index);
566321790f6SBryan Wu 	wLength = swap_16(cmd->length);
567321790f6SBryan Wu 
568321790f6SBryan Wu 	debug("--- HUB ----------------------------------------\n");
569321790f6SBryan Wu 	debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
570321790f6SBryan Wu 	    bmRType_bReq, wValue, wIndex, wLength);
571321790f6SBryan Wu 	debug("------------------------------------------------\n");
572321790f6SBryan Wu 
573321790f6SBryan Wu 	switch (bmRType_bReq) {
574321790f6SBryan Wu 	case RH_GET_STATUS:
575321790f6SBryan Wu 		debug("RH_GET_STATUS\n");
576321790f6SBryan Wu 
577321790f6SBryan Wu 		*(__u16 *) data_buf = swap_16(1);
578321790f6SBryan Wu 		len = 2;
579321790f6SBryan Wu 		break;
580321790f6SBryan Wu 
581321790f6SBryan Wu 	case RH_GET_STATUS | RH_INTERFACE:
582321790f6SBryan Wu 		debug("RH_GET_STATUS | RH_INTERFACE\n");
583321790f6SBryan Wu 
584321790f6SBryan Wu 		*(__u16 *) data_buf = swap_16(0);
585321790f6SBryan Wu 		len = 2;
586321790f6SBryan Wu 		break;
587321790f6SBryan Wu 
588321790f6SBryan Wu 	case RH_GET_STATUS | RH_ENDPOINT:
589321790f6SBryan Wu 		debug("RH_GET_STATUS | RH_ENDPOINT\n");
590321790f6SBryan Wu 
591321790f6SBryan Wu 		*(__u16 *) data_buf = swap_16(0);
592321790f6SBryan Wu 		len = 2;
593321790f6SBryan Wu 		break;
594321790f6SBryan Wu 
595321790f6SBryan Wu 	case RH_GET_STATUS | RH_CLASS:
596321790f6SBryan Wu 		debug("RH_GET_STATUS | RH_CLASS\n");
597321790f6SBryan Wu 
598321790f6SBryan Wu 		*(__u32 *) data_buf = swap_32(0);
599321790f6SBryan Wu 		len = 4;
600321790f6SBryan Wu 		break;
601321790f6SBryan Wu 
602321790f6SBryan Wu 	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
603321790f6SBryan Wu 		debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
604321790f6SBryan Wu 
605321790f6SBryan Wu 		int_usb = readw(&musbr->intrusb);
606321790f6SBryan Wu 		if (int_usb & MUSB_INTR_CONNECT) {
607321790f6SBryan Wu 			port_status |= USB_PORT_STAT_CONNECTION
608321790f6SBryan Wu 				| (USB_PORT_STAT_C_CONNECTION << 16);
609321790f6SBryan Wu 			port_status |= USB_PORT_STAT_HIGH_SPEED
610321790f6SBryan Wu 				| USB_PORT_STAT_ENABLE;
611321790f6SBryan Wu 		}
612321790f6SBryan Wu 
613321790f6SBryan Wu 		if (port_status & USB_PORT_STAT_RESET)
614321790f6SBryan Wu 			musb_port_reset(0);
615321790f6SBryan Wu 
616321790f6SBryan Wu 		*(__u32 *) data_buf = swap_32(port_status);
617321790f6SBryan Wu 		len = 4;
618321790f6SBryan Wu 		break;
619321790f6SBryan Wu 
620321790f6SBryan Wu 	case RH_CLEAR_FEATURE | RH_ENDPOINT:
621321790f6SBryan Wu 		debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
622321790f6SBryan Wu 
623321790f6SBryan Wu 		switch (wValue) {
624321790f6SBryan Wu 		case RH_ENDPOINT_STALL:
625321790f6SBryan Wu 			debug("C_HUB_ENDPOINT_STALL\n");
626321790f6SBryan Wu 			len = 0;
627321790f6SBryan Wu 			break;
628321790f6SBryan Wu 		}
629321790f6SBryan Wu 		port_status &= ~(1 << wValue);
630321790f6SBryan Wu 		break;
631321790f6SBryan Wu 
632321790f6SBryan Wu 	case RH_CLEAR_FEATURE | RH_CLASS:
633321790f6SBryan Wu 		debug("RH_CLEAR_FEATURE | RH_CLASS\n");
634321790f6SBryan Wu 
635321790f6SBryan Wu 		switch (wValue) {
636321790f6SBryan Wu 		case RH_C_HUB_LOCAL_POWER:
637321790f6SBryan Wu 			debug("C_HUB_LOCAL_POWER\n");
638321790f6SBryan Wu 			len = 0;
639321790f6SBryan Wu 			break;
640321790f6SBryan Wu 
641321790f6SBryan Wu 		case RH_C_HUB_OVER_CURRENT:
642321790f6SBryan Wu 			debug("C_HUB_OVER_CURRENT\n");
643321790f6SBryan Wu 			len = 0;
644321790f6SBryan Wu 			break;
645321790f6SBryan Wu 		}
646321790f6SBryan Wu 		port_status &= ~(1 << wValue);
647321790f6SBryan Wu 		break;
648321790f6SBryan Wu 
649321790f6SBryan Wu 	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
650321790f6SBryan Wu 		debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
651321790f6SBryan Wu 
652321790f6SBryan Wu 		switch (wValue) {
653321790f6SBryan Wu 		case RH_PORT_ENABLE:
654321790f6SBryan Wu 			len = 0;
655321790f6SBryan Wu 			break;
656321790f6SBryan Wu 
657321790f6SBryan Wu 		case RH_PORT_SUSPEND:
658321790f6SBryan Wu 			len = 0;
659321790f6SBryan Wu 			break;
660321790f6SBryan Wu 
661321790f6SBryan Wu 		case RH_PORT_POWER:
662321790f6SBryan Wu 			len = 0;
663321790f6SBryan Wu 			break;
664321790f6SBryan Wu 
665321790f6SBryan Wu 		case RH_C_PORT_CONNECTION:
666321790f6SBryan Wu 			len = 0;
667321790f6SBryan Wu 			break;
668321790f6SBryan Wu 
669321790f6SBryan Wu 		case RH_C_PORT_ENABLE:
670321790f6SBryan Wu 			len = 0;
671321790f6SBryan Wu 			break;
672321790f6SBryan Wu 
673321790f6SBryan Wu 		case RH_C_PORT_SUSPEND:
674321790f6SBryan Wu 			len = 0;
675321790f6SBryan Wu 			break;
676321790f6SBryan Wu 
677321790f6SBryan Wu 		case RH_C_PORT_OVER_CURRENT:
678321790f6SBryan Wu 			len = 0;
679321790f6SBryan Wu 			break;
680321790f6SBryan Wu 
681321790f6SBryan Wu 		case RH_C_PORT_RESET:
682321790f6SBryan Wu 			len = 0;
683321790f6SBryan Wu 			break;
684321790f6SBryan Wu 
685321790f6SBryan Wu 		default:
686321790f6SBryan Wu 			debug("invalid wValue\n");
687321790f6SBryan Wu 			stat = USB_ST_STALLED;
688321790f6SBryan Wu 		}
689321790f6SBryan Wu 
690321790f6SBryan Wu 		port_status &= ~(1 << wValue);
691321790f6SBryan Wu 		break;
692321790f6SBryan Wu 
693321790f6SBryan Wu 	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
694321790f6SBryan Wu 		debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
695321790f6SBryan Wu 
696321790f6SBryan Wu 		switch (wValue) {
697321790f6SBryan Wu 		case RH_PORT_SUSPEND:
698321790f6SBryan Wu 			len = 0;
699321790f6SBryan Wu 			break;
700321790f6SBryan Wu 
701321790f6SBryan Wu 		case RH_PORT_RESET:
702321790f6SBryan Wu 			musb_port_reset(1);
703321790f6SBryan Wu 			len = 0;
704321790f6SBryan Wu 			break;
705321790f6SBryan Wu 
706321790f6SBryan Wu 		case RH_PORT_POWER:
707321790f6SBryan Wu 			len = 0;
708321790f6SBryan Wu 			break;
709321790f6SBryan Wu 
710321790f6SBryan Wu 		case RH_PORT_ENABLE:
711321790f6SBryan Wu 			len = 0;
712321790f6SBryan Wu 			break;
713321790f6SBryan Wu 
714321790f6SBryan Wu 		default:
715321790f6SBryan Wu 			debug("invalid wValue\n");
716321790f6SBryan Wu 			stat = USB_ST_STALLED;
717321790f6SBryan Wu 		}
718321790f6SBryan Wu 
719321790f6SBryan Wu 		port_status |= 1 << wValue;
720321790f6SBryan Wu 		break;
721321790f6SBryan Wu 
722321790f6SBryan Wu 	case RH_SET_ADDRESS:
723321790f6SBryan Wu 		debug("RH_SET_ADDRESS\n");
724321790f6SBryan Wu 
725321790f6SBryan Wu 		rh_devnum = wValue;
726321790f6SBryan Wu 		len = 0;
727321790f6SBryan Wu 		break;
728321790f6SBryan Wu 
729321790f6SBryan Wu 	case RH_GET_DESCRIPTOR:
730321790f6SBryan Wu 		debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
731321790f6SBryan Wu 
732321790f6SBryan Wu 		switch (wValue) {
733321790f6SBryan Wu 		case (USB_DT_DEVICE << 8):	/* device descriptor */
734321790f6SBryan Wu 			len = min_t(unsigned int,
735321790f6SBryan Wu 				    leni, min_t(unsigned int,
736321790f6SBryan Wu 						sizeof(root_hub_dev_des),
737321790f6SBryan Wu 						wLength));
738321790f6SBryan Wu 			data_buf = root_hub_dev_des;
739321790f6SBryan Wu 			break;
740321790f6SBryan Wu 
741321790f6SBryan Wu 		case (USB_DT_CONFIG << 8):	/* configuration descriptor */
742321790f6SBryan Wu 			len = min_t(unsigned int,
743321790f6SBryan Wu 				    leni, min_t(unsigned int,
744321790f6SBryan Wu 						sizeof(root_hub_config_des),
745321790f6SBryan Wu 						wLength));
746321790f6SBryan Wu 			data_buf = root_hub_config_des;
747321790f6SBryan Wu 			break;
748321790f6SBryan Wu 
749321790f6SBryan Wu 		case ((USB_DT_STRING << 8) | 0x00):	/* string 0 descriptors */
750321790f6SBryan Wu 			len = min_t(unsigned int,
751321790f6SBryan Wu 				    leni, min_t(unsigned int,
752321790f6SBryan Wu 						sizeof(root_hub_str_index0),
753321790f6SBryan Wu 						wLength));
754321790f6SBryan Wu 			data_buf = root_hub_str_index0;
755321790f6SBryan Wu 			break;
756321790f6SBryan Wu 
757321790f6SBryan Wu 		case ((USB_DT_STRING << 8) | 0x01):	/* string 1 descriptors */
758321790f6SBryan Wu 			len = min_t(unsigned int,
759321790f6SBryan Wu 				    leni, min_t(unsigned int,
760321790f6SBryan Wu 						sizeof(root_hub_str_index1),
761321790f6SBryan Wu 						wLength));
762321790f6SBryan Wu 			data_buf = root_hub_str_index1;
763321790f6SBryan Wu 			break;
764321790f6SBryan Wu 
765321790f6SBryan Wu 		default:
766321790f6SBryan Wu 			debug("invalid wValue\n");
767321790f6SBryan Wu 			stat = USB_ST_STALLED;
768321790f6SBryan Wu 		}
769321790f6SBryan Wu 
770321790f6SBryan Wu 		break;
771321790f6SBryan Wu 
772321790f6SBryan Wu 	case RH_GET_DESCRIPTOR | RH_CLASS:
773321790f6SBryan Wu 		debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
774321790f6SBryan Wu 
775321790f6SBryan Wu 		data_buf[0] = 0x09;	/* min length; */
776321790f6SBryan Wu 		data_buf[1] = 0x29;
777321790f6SBryan Wu 		data_buf[2] = 0x1;	/* 1 port */
778321790f6SBryan Wu 		data_buf[3] = 0x01;	/* per-port power switching */
779321790f6SBryan Wu 		data_buf[3] |= 0x10;	/* no overcurrent reporting */
780321790f6SBryan Wu 
781321790f6SBryan Wu 		/* Corresponds to data_buf[4-7] */
782321790f6SBryan Wu 		data_buf[4] = 0;
783321790f6SBryan Wu 		data_buf[5] = 5;
784321790f6SBryan Wu 		data_buf[6] = 0;
785321790f6SBryan Wu 		data_buf[7] = 0x02;
786321790f6SBryan Wu 		data_buf[8] = 0xff;
787321790f6SBryan Wu 
788321790f6SBryan Wu 		len = min_t(unsigned int, leni,
789321790f6SBryan Wu 			    min_t(unsigned int, data_buf[0], wLength));
790321790f6SBryan Wu 		break;
791321790f6SBryan Wu 
792321790f6SBryan Wu 	case RH_GET_CONFIGURATION:
793321790f6SBryan Wu 		debug("RH_GET_CONFIGURATION\n");
794321790f6SBryan Wu 
795321790f6SBryan Wu 		*(__u8 *) data_buf = 0x01;
796321790f6SBryan Wu 		len = 1;
797321790f6SBryan Wu 		break;
798321790f6SBryan Wu 
799321790f6SBryan Wu 	case RH_SET_CONFIGURATION:
800321790f6SBryan Wu 		debug("RH_SET_CONFIGURATION\n");
801321790f6SBryan Wu 
802321790f6SBryan Wu 		len = 0;
803321790f6SBryan Wu 		break;
804321790f6SBryan Wu 
805321790f6SBryan Wu 	default:
806321790f6SBryan Wu 		debug("*** *** *** unsupported root hub command *** *** ***\n");
807321790f6SBryan Wu 		stat = USB_ST_STALLED;
808321790f6SBryan Wu 	}
809321790f6SBryan Wu 
810321790f6SBryan Wu 	len = min_t(int, len, leni);
811321790f6SBryan Wu 	if (buffer != data_buf)
812321790f6SBryan Wu 		memcpy(buffer, data_buf, len);
813321790f6SBryan Wu 
814321790f6SBryan Wu 	dev->act_len = len;
815321790f6SBryan Wu 	dev->status = stat;
816321790f6SBryan Wu 	debug("dev act_len %d, status %d\n", dev->act_len, dev->status);
817321790f6SBryan Wu 
818321790f6SBryan Wu 	return stat;
819321790f6SBryan Wu }
820321790f6SBryan Wu 
821321790f6SBryan Wu static void musb_rh_init(void)
822321790f6SBryan Wu {
823321790f6SBryan Wu 	rh_devnum = 0;
824321790f6SBryan Wu 	port_status = 0;
825321790f6SBryan Wu }
826321790f6SBryan Wu 
827321790f6SBryan Wu #else
828321790f6SBryan Wu 
829321790f6SBryan Wu static void musb_rh_init(void) {}
830321790f6SBryan Wu 
831321790f6SBryan Wu #endif
832321790f6SBryan Wu 
8332731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
8342731b9a8SJean-Christophe PLAGNIOL-VILLARD  * do a control transfer
8352731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
8362731b9a8SJean-Christophe PLAGNIOL-VILLARD int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
8372731b9a8SJean-Christophe PLAGNIOL-VILLARD 			int len, struct devrequest *setup)
8382731b9a8SJean-Christophe PLAGNIOL-VILLARD {
8392731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int devnum = usb_pipedevice(pipe);
8402731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
8412731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  devspeed;
8422731b9a8SJean-Christophe PLAGNIOL-VILLARD 
843321790f6SBryan Wu #ifdef MUSB_NO_MULTIPOINT
844321790f6SBryan Wu 	/* Control message is for the HUB? */
845321790f6SBryan Wu 	if (devnum == rh_devnum)
846321790f6SBryan Wu 		return musb_submit_rh_msg(dev, pipe, buffer, len, setup);
847321790f6SBryan Wu #endif
848321790f6SBryan Wu 
8492731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* select control endpoint */
8502731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb(MUSB_CONTROL_EP, &musbr->index);
8512731b9a8SJean-Christophe PLAGNIOL-VILLARD 	csr = readw(&musbr->txcsr);
8522731b9a8SJean-Christophe PLAGNIOL-VILLARD 
8538868fd44SBryan Wu #ifndef MUSB_NO_MULTIPOINT
8542731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* target addr and (for multipoint) hub addr/port */
8552731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
8562731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
8578868fd44SBryan Wu #endif
8582731b9a8SJean-Christophe PLAGNIOL-VILLARD 
8592731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* configure the hub address and the port number as required */
8602731b9a8SJean-Christophe PLAGNIOL-VILLARD 	devspeed = get_dev_speed(dev);
8612731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if ((musb_ishighspeed()) && (dev->parent != NULL) &&
8622731b9a8SJean-Christophe PLAGNIOL-VILLARD 		(devspeed != MUSB_TYPE_SPEED_HIGH)) {
8632731b9a8SJean-Christophe PLAGNIOL-VILLARD 		config_hub_port(dev, MUSB_CONTROL_EP);
8642731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(devspeed << 6, &musbr->txtype);
8652731b9a8SJean-Christophe PLAGNIOL-VILLARD 	} else {
8662731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
8678868fd44SBryan Wu #ifndef MUSB_NO_MULTIPOINT
8682731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
8692731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
8702731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
8712731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
8728868fd44SBryan Wu #endif
8732731b9a8SJean-Christophe PLAGNIOL-VILLARD 	}
8742731b9a8SJean-Christophe PLAGNIOL-VILLARD 
8752731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Control transfer setup phase */
8762731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if (ctrlreq_setup_phase(dev, setup) < 0)
8772731b9a8SJean-Christophe PLAGNIOL-VILLARD 		return 0;
8782731b9a8SJean-Christophe PLAGNIOL-VILLARD 
8792731b9a8SJean-Christophe PLAGNIOL-VILLARD 	switch (setup->request) {
8802731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_REQ_GET_DESCRIPTOR:
8812731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_REQ_GET_CONFIGURATION:
8822731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_REQ_GET_INTERFACE:
8832731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_REQ_GET_STATUS:
8842731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_MSC_BBB_GET_MAX_LUN:
8852731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* control transfer in-data-phase */
8862731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
8872731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return 0;
8882731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* control transfer out-status-phase */
8892731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (ctrlreq_out_status_phase(dev) < 0)
8902731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return 0;
8912731b9a8SJean-Christophe PLAGNIOL-VILLARD 		break;
8922731b9a8SJean-Christophe PLAGNIOL-VILLARD 
8932731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_REQ_SET_ADDRESS:
8942731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_REQ_SET_CONFIGURATION:
8952731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_REQ_SET_FEATURE:
8962731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_REQ_SET_INTERFACE:
8972731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_REQ_CLEAR_FEATURE:
8982731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_MSC_BBB_RESET:
8992731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* control transfer in status phase */
9002731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (ctrlreq_in_status_phase(dev) < 0)
9012731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return 0;
9022731b9a8SJean-Christophe PLAGNIOL-VILLARD 		break;
9032731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9042731b9a8SJean-Christophe PLAGNIOL-VILLARD 	case USB_REQ_SET_DESCRIPTOR:
9052731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* control transfer out data phase */
9062731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
9072731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return 0;
9082731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* control transfer in status phase */
9092731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (ctrlreq_in_status_phase(dev) < 0)
9102731b9a8SJean-Christophe PLAGNIOL-VILLARD 			return 0;
9112731b9a8SJean-Christophe PLAGNIOL-VILLARD 		break;
9122731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9132731b9a8SJean-Christophe PLAGNIOL-VILLARD 	default:
9142731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* unhandled control transfer */
9152731b9a8SJean-Christophe PLAGNIOL-VILLARD 		return -1;
9162731b9a8SJean-Christophe PLAGNIOL-VILLARD 	}
9172731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9182731b9a8SJean-Christophe PLAGNIOL-VILLARD 	dev->status = 0;
9192731b9a8SJean-Christophe PLAGNIOL-VILLARD 	dev->act_len = len;
920*93ceb479SBryan Wu 
921*93ceb479SBryan Wu #ifdef MUSB_NO_MULTIPOINT
922*93ceb479SBryan Wu 	/* Set device address to USB_FADDR register */
923*93ceb479SBryan Wu 	if (setup->request == USB_REQ_SET_ADDRESS)
924*93ceb479SBryan Wu 		writeb(dev->devnum, &musbr->faddr);
925*93ceb479SBryan Wu #endif
926*93ceb479SBryan Wu 
9272731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return len;
9282731b9a8SJean-Christophe PLAGNIOL-VILLARD }
9292731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9302731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
9312731b9a8SJean-Christophe PLAGNIOL-VILLARD  * do a bulk transfer
9322731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
9332731b9a8SJean-Christophe PLAGNIOL-VILLARD int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
9342731b9a8SJean-Christophe PLAGNIOL-VILLARD 					void *buffer, int len)
9352731b9a8SJean-Christophe PLAGNIOL-VILLARD {
9362731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int dir_out = usb_pipeout(pipe);
9372731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int ep = usb_pipeendpoint(pipe);
9388868fd44SBryan Wu #ifndef MUSB_NO_MULTIPOINT
9392731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int devnum = usb_pipedevice(pipe);
9408868fd44SBryan Wu #endif
9412731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  type;
9422731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
9432731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u32 txlen = 0;
9442731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u32 nextlen = 0;
9452731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  devspeed;
9462731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9472731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* select bulk endpoint */
9482731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb(MUSB_BULK_EP, &musbr->index);
9492731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9508868fd44SBryan Wu #ifndef MUSB_NO_MULTIPOINT
9512731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* write the address of the device */
9522731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if (dir_out)
9532731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
9542731b9a8SJean-Christophe PLAGNIOL-VILLARD 	else
9552731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
9568868fd44SBryan Wu #endif
9572731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9582731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* configure the hub address and the port number as required */
9592731b9a8SJean-Christophe PLAGNIOL-VILLARD 	devspeed = get_dev_speed(dev);
9602731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if ((musb_ishighspeed()) && (dev->parent != NULL) &&
9612731b9a8SJean-Christophe PLAGNIOL-VILLARD 		(devspeed != MUSB_TYPE_SPEED_HIGH)) {
9622731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/*
9632731b9a8SJean-Christophe PLAGNIOL-VILLARD 		 * MUSB is in high speed and the destination device is full
9642731b9a8SJean-Christophe PLAGNIOL-VILLARD 		 * speed device. So configure the hub address and port
9652731b9a8SJean-Christophe PLAGNIOL-VILLARD 		 * address registers.
9662731b9a8SJean-Christophe PLAGNIOL-VILLARD 		 */
9672731b9a8SJean-Christophe PLAGNIOL-VILLARD 		config_hub_port(dev, MUSB_BULK_EP);
9682731b9a8SJean-Christophe PLAGNIOL-VILLARD 	} else {
9698868fd44SBryan Wu #ifndef MUSB_NO_MULTIPOINT
9702731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (dir_out) {
9712731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
9722731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
9732731b9a8SJean-Christophe PLAGNIOL-VILLARD 		} else {
9742731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
9752731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
9762731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
9778868fd44SBryan Wu #endif
9782731b9a8SJean-Christophe PLAGNIOL-VILLARD 		devspeed = musb_cfg.musb_speed;
9792731b9a8SJean-Christophe PLAGNIOL-VILLARD 	}
9802731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9812731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Write the saved toggle bit value */
9822731b9a8SJean-Christophe PLAGNIOL-VILLARD 	write_toggle(dev, ep, dir_out);
9832731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9842731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if (dir_out) { /* bulk-out transfer */
9852731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Program the TxType register */
9862731b9a8SJean-Christophe PLAGNIOL-VILLARD 		type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
9872731b9a8SJean-Christophe PLAGNIOL-VILLARD 			   (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
9882731b9a8SJean-Christophe PLAGNIOL-VILLARD 			   (ep & MUSB_TYPE_REMOTE_END);
9892731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(type, &musbr->txtype);
9902731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9912731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Write maximum packet size to the TxMaxp register */
9922731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
9932731b9a8SJean-Christophe PLAGNIOL-VILLARD 		while (txlen < len) {
9942731b9a8SJean-Christophe PLAGNIOL-VILLARD 			nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
9952731b9a8SJean-Christophe PLAGNIOL-VILLARD 					(len-txlen) : dev->epmaxpacketout[ep];
9962731b9a8SJean-Christophe PLAGNIOL-VILLARD 
9978dd7a230SBryan Wu #ifdef CONFIG_USB_BLACKFIN
9988dd7a230SBryan Wu 			/* Set the transfer data size */
9998dd7a230SBryan Wu 			writew(nextlen, &musbr->txcount);
10008dd7a230SBryan Wu #endif
10018dd7a230SBryan Wu 
10022731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Write the data to the FIFO */
10032731b9a8SJean-Christophe PLAGNIOL-VILLARD 			write_fifo(MUSB_BULK_EP, nextlen,
10042731b9a8SJean-Christophe PLAGNIOL-VILLARD 					(void *)(((u8 *)buffer) + txlen));
10052731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10062731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Set the TxPktRdy bit */
10072731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr = readw(&musbr->txcsr);
10082731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
10092731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10102731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Wait until the TxPktRdy bit is cleared */
10112731b9a8SJean-Christophe PLAGNIOL-VILLARD 			if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) {
10122731b9a8SJean-Christophe PLAGNIOL-VILLARD 				readw(&musbr->txcsr);
10132731b9a8SJean-Christophe PLAGNIOL-VILLARD 				usb_settoggle(dev, ep, dir_out,
10142731b9a8SJean-Christophe PLAGNIOL-VILLARD 				(csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
10152731b9a8SJean-Christophe PLAGNIOL-VILLARD 				dev->act_len = txlen;
10162731b9a8SJean-Christophe PLAGNIOL-VILLARD 				return 0;
10172731b9a8SJean-Christophe PLAGNIOL-VILLARD 			}
10182731b9a8SJean-Christophe PLAGNIOL-VILLARD 			txlen += nextlen;
10192731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
10202731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10212731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Keep a copy of the data toggle bit */
10222731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr = readw(&musbr->txcsr);
10232731b9a8SJean-Christophe PLAGNIOL-VILLARD 		usb_settoggle(dev, ep, dir_out,
10242731b9a8SJean-Christophe PLAGNIOL-VILLARD 				(csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
10252731b9a8SJean-Christophe PLAGNIOL-VILLARD 	} else { /* bulk-in transfer */
10262731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Write the saved toggle bit value */
10272731b9a8SJean-Christophe PLAGNIOL-VILLARD 		write_toggle(dev, ep, dir_out);
10282731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10292731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Program the RxType register */
10302731b9a8SJean-Christophe PLAGNIOL-VILLARD 		type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
10312731b9a8SJean-Christophe PLAGNIOL-VILLARD 			   (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
10322731b9a8SJean-Christophe PLAGNIOL-VILLARD 			   (ep & MUSB_TYPE_REMOTE_END);
10332731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(type, &musbr->rxtype);
10342731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10352731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Write the maximum packet size to the RxMaxp register */
10362731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
10372731b9a8SJean-Christophe PLAGNIOL-VILLARD 		while (txlen < len) {
10382731b9a8SJean-Christophe PLAGNIOL-VILLARD 			nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
10392731b9a8SJean-Christophe PLAGNIOL-VILLARD 					(len-txlen) : dev->epmaxpacketin[ep];
10402731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10412731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Set the ReqPkt bit */
1042bc72a919SBryan Wu 			csr = readw(&musbr->rxcsr);
1043bc72a919SBryan Wu 			writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
10442731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10452731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Wait until the RxPktRdy bit is set */
10462731b9a8SJean-Christophe PLAGNIOL-VILLARD 			if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) {
10472731b9a8SJean-Christophe PLAGNIOL-VILLARD 				csr = readw(&musbr->rxcsr);
10482731b9a8SJean-Christophe PLAGNIOL-VILLARD 				usb_settoggle(dev, ep, dir_out,
10492731b9a8SJean-Christophe PLAGNIOL-VILLARD 				(csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
10502731b9a8SJean-Christophe PLAGNIOL-VILLARD 				csr &= ~MUSB_RXCSR_RXPKTRDY;
10512731b9a8SJean-Christophe PLAGNIOL-VILLARD 				writew(csr, &musbr->rxcsr);
10522731b9a8SJean-Christophe PLAGNIOL-VILLARD 				dev->act_len = txlen;
10532731b9a8SJean-Christophe PLAGNIOL-VILLARD 				return 0;
10542731b9a8SJean-Christophe PLAGNIOL-VILLARD 			}
10552731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10562731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Read the data from the FIFO */
10572731b9a8SJean-Christophe PLAGNIOL-VILLARD 			read_fifo(MUSB_BULK_EP, nextlen,
10582731b9a8SJean-Christophe PLAGNIOL-VILLARD 					(void *)(((u8 *)buffer) + txlen));
10592731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10602731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Clear the RxPktRdy bit */
10612731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr =  readw(&musbr->rxcsr);
10622731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr &= ~MUSB_RXCSR_RXPKTRDY;
10632731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(csr, &musbr->rxcsr);
10642731b9a8SJean-Christophe PLAGNIOL-VILLARD 			txlen += nextlen;
10652731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
10662731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10672731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Keep a copy of the data toggle bit */
10682731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr = readw(&musbr->rxcsr);
10692731b9a8SJean-Christophe PLAGNIOL-VILLARD 		usb_settoggle(dev, ep, dir_out,
10702731b9a8SJean-Christophe PLAGNIOL-VILLARD 				(csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
10712731b9a8SJean-Christophe PLAGNIOL-VILLARD 	}
10722731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10732731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* bulk transfer is complete */
10742731b9a8SJean-Christophe PLAGNIOL-VILLARD 	dev->status = 0;
10752731b9a8SJean-Christophe PLAGNIOL-VILLARD 	dev->act_len = len;
10762731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return 0;
10772731b9a8SJean-Christophe PLAGNIOL-VILLARD }
10782731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10792731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
10802731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function initializes the usb controller module.
10812731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
10822731b9a8SJean-Christophe PLAGNIOL-VILLARD int usb_lowlevel_init(void)
10832731b9a8SJean-Christophe PLAGNIOL-VILLARD {
10842731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  power;
10852731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u32 timeout;
10862731b9a8SJean-Christophe PLAGNIOL-VILLARD 
1087321790f6SBryan Wu 	musb_rh_init();
1088321790f6SBryan Wu 
10892731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if (musb_platform_init() == -1)
10902731b9a8SJean-Christophe PLAGNIOL-VILLARD 		return -1;
10912731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10922731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Configure all the endpoint FIFO's and start usb controller */
10932731b9a8SJean-Christophe PLAGNIOL-VILLARD 	musbr = musb_cfg.regs;
10942731b9a8SJean-Christophe PLAGNIOL-VILLARD 	musb_configure_ep(&epinfo[0],
10952731b9a8SJean-Christophe PLAGNIOL-VILLARD 			sizeof(epinfo) / sizeof(struct musb_epinfo));
10962731b9a8SJean-Christophe PLAGNIOL-VILLARD 	musb_start();
10972731b9a8SJean-Christophe PLAGNIOL-VILLARD 
10982731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/*
10992731b9a8SJean-Christophe PLAGNIOL-VILLARD 	 * Wait until musb is enabled in host mode with a timeout. There
11002731b9a8SJean-Christophe PLAGNIOL-VILLARD 	 * should be a usb device connected.
11012731b9a8SJean-Christophe PLAGNIOL-VILLARD 	 */
11022731b9a8SJean-Christophe PLAGNIOL-VILLARD 	timeout = musb_cfg.timeout;
11032731b9a8SJean-Christophe PLAGNIOL-VILLARD 	while (timeout--)
11042731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
11052731b9a8SJean-Christophe PLAGNIOL-VILLARD 			break;
11062731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11072731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* if musb core is not in host mode, then return */
11082731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if (!timeout)
11092731b9a8SJean-Christophe PLAGNIOL-VILLARD 		return -1;
11102731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11112731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* start usb bus reset */
11122731b9a8SJean-Christophe PLAGNIOL-VILLARD 	power = readb(&musbr->power);
11132731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb(power | MUSB_POWER_RESET, &musbr->power);
11142731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11152731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* After initiating a usb reset, wait for about 20ms to 30ms */
11162731b9a8SJean-Christophe PLAGNIOL-VILLARD 	udelay(30000);
11172731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11182731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* stop usb bus reset */
11192731b9a8SJean-Christophe PLAGNIOL-VILLARD 	power = readb(&musbr->power);
11202731b9a8SJean-Christophe PLAGNIOL-VILLARD 	power &= ~MUSB_POWER_RESET;
11212731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb(power, &musbr->power);
11222731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11232731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Determine if the connected device is a high/full/low speed device */
11242731b9a8SJean-Christophe PLAGNIOL-VILLARD 	musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
11252731b9a8SJean-Christophe PLAGNIOL-VILLARD 			MUSB_TYPE_SPEED_HIGH :
11262731b9a8SJean-Christophe PLAGNIOL-VILLARD 			((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
11272731b9a8SJean-Christophe PLAGNIOL-VILLARD 			MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
11282731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return 0;
11292731b9a8SJean-Christophe PLAGNIOL-VILLARD }
11302731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11312731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
11322731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function stops the operation of the davinci usb module.
11332731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
11342731b9a8SJean-Christophe PLAGNIOL-VILLARD int usb_lowlevel_stop(void)
11352731b9a8SJean-Christophe PLAGNIOL-VILLARD {
11362731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Reset the USB module */
11372731b9a8SJean-Christophe PLAGNIOL-VILLARD 	musb_platform_deinit();
11382731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb(0, &musbr->devctl);
11392731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return 0;
11402731b9a8SJean-Christophe PLAGNIOL-VILLARD }
11412731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11422731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
11432731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function supports usb interrupt transfers. Currently, usb interrupt
11442731b9a8SJean-Christophe PLAGNIOL-VILLARD  * transfers are not supported.
11452731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
11462731b9a8SJean-Christophe PLAGNIOL-VILLARD int submit_int_msg(struct usb_device *dev, unsigned long pipe,
11472731b9a8SJean-Christophe PLAGNIOL-VILLARD 				void *buffer, int len, int interval)
11482731b9a8SJean-Christophe PLAGNIOL-VILLARD {
11492731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int dir_out = usb_pipeout(pipe);
11502731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int ep = usb_pipeendpoint(pipe);
11518868fd44SBryan Wu #ifndef MUSB_NO_MULTIPOINT
11522731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int devnum = usb_pipedevice(pipe);
11538868fd44SBryan Wu #endif
11542731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  type;
11552731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u16 csr;
11562731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u32 txlen = 0;
11572731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u32 nextlen = 0;
11582731b9a8SJean-Christophe PLAGNIOL-VILLARD 	u8  devspeed;
11592731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11602731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* select interrupt endpoint */
11612731b9a8SJean-Christophe PLAGNIOL-VILLARD 	writeb(MUSB_INTR_EP, &musbr->index);
11622731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11638868fd44SBryan Wu #ifndef MUSB_NO_MULTIPOINT
11642731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* write the address of the device */
11652731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if (dir_out)
11662731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
11672731b9a8SJean-Christophe PLAGNIOL-VILLARD 	else
11682731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
11698868fd44SBryan Wu #endif
11702731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11712731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* configure the hub address and the port number as required */
11722731b9a8SJean-Christophe PLAGNIOL-VILLARD 	devspeed = get_dev_speed(dev);
11732731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if ((musb_ishighspeed()) && (dev->parent != NULL) &&
11742731b9a8SJean-Christophe PLAGNIOL-VILLARD 		(devspeed != MUSB_TYPE_SPEED_HIGH)) {
11752731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/*
11762731b9a8SJean-Christophe PLAGNIOL-VILLARD 		 * MUSB is in high speed and the destination device is full
11772731b9a8SJean-Christophe PLAGNIOL-VILLARD 		 * speed device. So configure the hub address and port
11782731b9a8SJean-Christophe PLAGNIOL-VILLARD 		 * address registers.
11792731b9a8SJean-Christophe PLAGNIOL-VILLARD 		 */
11802731b9a8SJean-Christophe PLAGNIOL-VILLARD 		config_hub_port(dev, MUSB_INTR_EP);
11812731b9a8SJean-Christophe PLAGNIOL-VILLARD 	} else {
11828868fd44SBryan Wu #ifndef MUSB_NO_MULTIPOINT
11832731b9a8SJean-Christophe PLAGNIOL-VILLARD 		if (dir_out) {
11842731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
11852731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
11862731b9a8SJean-Christophe PLAGNIOL-VILLARD 		} else {
11872731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
11882731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
11892731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
11908868fd44SBryan Wu #endif
11912731b9a8SJean-Christophe PLAGNIOL-VILLARD 		devspeed = musb_cfg.musb_speed;
11922731b9a8SJean-Christophe PLAGNIOL-VILLARD 	}
11932731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11942731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Write the saved toggle bit value */
11952731b9a8SJean-Christophe PLAGNIOL-VILLARD 	write_toggle(dev, ep, dir_out);
11962731b9a8SJean-Christophe PLAGNIOL-VILLARD 
11972731b9a8SJean-Christophe PLAGNIOL-VILLARD 	if (!dir_out) { /* intrrupt-in transfer */
11982731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Write the saved toggle bit value */
11992731b9a8SJean-Christophe PLAGNIOL-VILLARD 		write_toggle(dev, ep, dir_out);
12002731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(interval, &musbr->rxinterval);
12012731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12022731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Program the RxType register */
12032731b9a8SJean-Christophe PLAGNIOL-VILLARD 		type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
12042731b9a8SJean-Christophe PLAGNIOL-VILLARD 			   (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
12052731b9a8SJean-Christophe PLAGNIOL-VILLARD 			   (ep & MUSB_TYPE_REMOTE_END);
12062731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writeb(type, &musbr->rxtype);
12072731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12082731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Write the maximum packet size to the RxMaxp register */
12092731b9a8SJean-Christophe PLAGNIOL-VILLARD 		writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
12102731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12112731b9a8SJean-Christophe PLAGNIOL-VILLARD 		while (txlen < len) {
12122731b9a8SJean-Christophe PLAGNIOL-VILLARD 			nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
12132731b9a8SJean-Christophe PLAGNIOL-VILLARD 					(len-txlen) : dev->epmaxpacketin[ep];
12142731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12152731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Set the ReqPkt bit */
1216bc72a919SBryan Wu 			csr = readw(&musbr->rxcsr);
1217bc72a919SBryan Wu 			writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
12182731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12192731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Wait until the RxPktRdy bit is set */
12202731b9a8SJean-Christophe PLAGNIOL-VILLARD 			if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) {
12212731b9a8SJean-Christophe PLAGNIOL-VILLARD 				csr = readw(&musbr->rxcsr);
12222731b9a8SJean-Christophe PLAGNIOL-VILLARD 				usb_settoggle(dev, ep, dir_out,
12232731b9a8SJean-Christophe PLAGNIOL-VILLARD 				(csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
12242731b9a8SJean-Christophe PLAGNIOL-VILLARD 				csr &= ~MUSB_RXCSR_RXPKTRDY;
12252731b9a8SJean-Christophe PLAGNIOL-VILLARD 				writew(csr, &musbr->rxcsr);
12262731b9a8SJean-Christophe PLAGNIOL-VILLARD 				dev->act_len = txlen;
12272731b9a8SJean-Christophe PLAGNIOL-VILLARD 				return 0;
12282731b9a8SJean-Christophe PLAGNIOL-VILLARD 			}
12292731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12302731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Read the data from the FIFO */
12312731b9a8SJean-Christophe PLAGNIOL-VILLARD 			read_fifo(MUSB_INTR_EP, nextlen,
12322731b9a8SJean-Christophe PLAGNIOL-VILLARD 					(void *)(((u8 *)buffer) + txlen));
12332731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12342731b9a8SJean-Christophe PLAGNIOL-VILLARD 			/* Clear the RxPktRdy bit */
12352731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr =  readw(&musbr->rxcsr);
12362731b9a8SJean-Christophe PLAGNIOL-VILLARD 			csr &= ~MUSB_RXCSR_RXPKTRDY;
12372731b9a8SJean-Christophe PLAGNIOL-VILLARD 			writew(csr, &musbr->rxcsr);
12382731b9a8SJean-Christophe PLAGNIOL-VILLARD 			txlen += nextlen;
12392731b9a8SJean-Christophe PLAGNIOL-VILLARD 		}
12402731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12412731b9a8SJean-Christophe PLAGNIOL-VILLARD 		/* Keep a copy of the data toggle bit */
12422731b9a8SJean-Christophe PLAGNIOL-VILLARD 		csr = readw(&musbr->rxcsr);
12432731b9a8SJean-Christophe PLAGNIOL-VILLARD 		usb_settoggle(dev, ep, dir_out,
12442731b9a8SJean-Christophe PLAGNIOL-VILLARD 				(csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
12452731b9a8SJean-Christophe PLAGNIOL-VILLARD 	}
12462731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12472731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* interrupt transfer is complete */
12482731b9a8SJean-Christophe PLAGNIOL-VILLARD 	dev->irq_status = 0;
12492731b9a8SJean-Christophe PLAGNIOL-VILLARD 	dev->irq_act_len = len;
12502731b9a8SJean-Christophe PLAGNIOL-VILLARD 	dev->irq_handle(dev);
12512731b9a8SJean-Christophe PLAGNIOL-VILLARD 	dev->status = 0;
12522731b9a8SJean-Christophe PLAGNIOL-VILLARD 	dev->act_len = len;
12532731b9a8SJean-Christophe PLAGNIOL-VILLARD 	return 0;
12542731b9a8SJean-Christophe PLAGNIOL-VILLARD }
12552731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12562731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12572731b9a8SJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_USB_EVENT_POLL
12582731b9a8SJean-Christophe PLAGNIOL-VILLARD /*
12592731b9a8SJean-Christophe PLAGNIOL-VILLARD  * This function polls for USB keyboard data.
12602731b9a8SJean-Christophe PLAGNIOL-VILLARD  */
12612731b9a8SJean-Christophe PLAGNIOL-VILLARD void usb_event_poll()
12622731b9a8SJean-Christophe PLAGNIOL-VILLARD {
126352cb4d4fSJean-Christophe PLAGNIOL-VILLARD 	struct stdio_dev *dev;
12642731b9a8SJean-Christophe PLAGNIOL-VILLARD 	struct usb_device *usb_kbd_dev;
12658f8bd565STom Rix 	struct usb_interface *iface;
12662731b9a8SJean-Christophe PLAGNIOL-VILLARD 	struct usb_endpoint_descriptor *ep;
12672731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int pipe;
12682731b9a8SJean-Christophe PLAGNIOL-VILLARD 	int maxp;
12692731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12702731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Get the pointer to USB Keyboard device pointer */
127152cb4d4fSJean-Christophe PLAGNIOL-VILLARD 	dev = stdio_get_by_name("usbkbd");
12722731b9a8SJean-Christophe PLAGNIOL-VILLARD 	usb_kbd_dev = (struct usb_device *)dev->priv;
12732731b9a8SJean-Christophe PLAGNIOL-VILLARD 	iface = &usb_kbd_dev->config.if_desc[0];
12742731b9a8SJean-Christophe PLAGNIOL-VILLARD 	ep = &iface->ep_desc[0];
12752731b9a8SJean-Christophe PLAGNIOL-VILLARD 	pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress);
12762731b9a8SJean-Christophe PLAGNIOL-VILLARD 
12772731b9a8SJean-Christophe PLAGNIOL-VILLARD 	/* Submit a interrupt transfer request */
12782731b9a8SJean-Christophe PLAGNIOL-VILLARD 	maxp = usb_maxpacket(usb_kbd_dev, pipe);
12792731b9a8SJean-Christophe PLAGNIOL-VILLARD 	usb_submit_int_msg(usb_kbd_dev, pipe, &new[0],
12802731b9a8SJean-Christophe PLAGNIOL-VILLARD 			maxp > 8 ? 8 : maxp, ep->bInterval);
12812731b9a8SJean-Christophe PLAGNIOL-VILLARD }
12822731b9a8SJean-Christophe PLAGNIOL-VILLARD #endif /* CONFIG_SYS_USB_EVENT_POLL */
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