1 /****************************************************************** 2 * Copyright 2008 Mentor Graphics Corporation 3 * Copyright (C) 2008 by Texas Instruments 4 * 5 * This file is part of the Inventra Controller Driver for Linux. 6 * 7 * The Inventra Controller Driver for Linux is free software; you 8 * can redistribute it and/or modify it under the terms of the GNU 9 * General Public License version 2 as published by the Free Software 10 * Foundation. 11 * 12 * The Inventra Controller Driver for Linux is distributed in 13 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 14 * without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 * License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with The Inventra Controller Driver for Linux ; if not, 20 * write to the Free Software Foundation, Inc., 59 Temple Place, 21 * Suite 330, Boston, MA 02111-1307 USA 22 * 23 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION 24 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE 25 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS 26 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER. 27 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES 28 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND 29 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT 30 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR 31 * GRAPHICS SUPPORT CUSTOMER. 32 ******************************************************************/ 33 34 #ifndef __MUSB_HDRC_DEFS_H__ 35 #define __MUSB_HDRC_DEFS_H__ 36 37 #include <usb.h> 38 #include <usb_defs.h> 39 #include <asm/io.h> 40 41 #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ 42 43 /* EP0 */ 44 struct musb_ep0_regs { 45 u16 reserved4; 46 u16 csr0; 47 u16 reserved5; 48 u16 reserved6; 49 u16 count0; 50 u8 host_type0; 51 u8 host_naklimit0; 52 u8 reserved7; 53 u8 reserved8; 54 u8 reserved9; 55 u8 configdata; 56 }; 57 58 /* EP 1-15 */ 59 struct musb_epN_regs { 60 u16 txmaxp; 61 u16 txcsr; 62 u16 rxmaxp; 63 u16 rxcsr; 64 u16 rxcount; 65 u8 txtype; 66 u8 txinterval; 67 u8 rxtype; 68 u8 rxinterval; 69 u8 reserved0; 70 u8 fifosize; 71 }; 72 73 /* Mentor USB core register overlay structure */ 74 struct musb_regs { 75 /* common registers */ 76 u8 faddr; 77 u8 power; 78 u16 intrtx; 79 u16 intrrx; 80 u16 intrtxe; 81 u16 intrrxe; 82 u8 intrusb; 83 u8 intrusbe; 84 u16 frame; 85 u8 index; 86 u8 testmode; 87 /* indexed registers */ 88 u16 txmaxp; 89 u16 txcsr; 90 u16 rxmaxp; 91 u16 rxcsr; 92 u16 rxcount; 93 u8 txtype; 94 u8 txinterval; 95 u8 rxtype; 96 u8 rxinterval; 97 u8 reserved0; 98 u8 fifosize; 99 /* fifo */ 100 u32 fifox[16]; 101 /* OTG, dynamic FIFO, version & vendor registers */ 102 u8 devctl; 103 u8 reserved1; 104 u8 txfifosz; 105 u8 rxfifosz; 106 u16 txfifoadd; 107 u16 rxfifoadd; 108 u32 vcontrol; 109 u16 hwvers; 110 u16 reserved2[5]; 111 u8 epinfo; 112 u8 raminfo; 113 u8 linkinfo; 114 u8 vplen; 115 u8 hseof1; 116 u8 fseof1; 117 u8 lseof1; 118 u8 reserved3; 119 /* target address registers */ 120 struct musb_tar_regs { 121 u8 txfuncaddr; 122 u8 reserved0; 123 u8 txhubaddr; 124 u8 txhubport; 125 u8 rxfuncaddr; 126 u8 reserved1; 127 u8 rxhubaddr; 128 u8 rxhubport; 129 } tar[16]; 130 /* 131 * end point registers 132 * ep0 elements are valid when array index is 0 133 * otherwise epN is valid 134 */ 135 union musb_ep_regs { 136 struct musb_ep0_regs ep0; 137 struct musb_epN_regs epN; 138 } ep[16]; 139 140 } __attribute__((aligned(32))); 141 142 /* 143 * MUSB Register bits 144 */ 145 146 /* POWER */ 147 #define MUSB_POWER_ISOUPDATE 0x80 148 #define MUSB_POWER_SOFTCONN 0x40 149 #define MUSB_POWER_HSENAB 0x20 150 #define MUSB_POWER_HSMODE 0x10 151 #define MUSB_POWER_RESET 0x08 152 #define MUSB_POWER_RESUME 0x04 153 #define MUSB_POWER_SUSPENDM 0x02 154 #define MUSB_POWER_ENSUSPEND 0x01 155 #define MUSB_POWER_HSMODE_SHIFT 4 156 157 /* INTRUSB */ 158 #define MUSB_INTR_SUSPEND 0x01 159 #define MUSB_INTR_RESUME 0x02 160 #define MUSB_INTR_RESET 0x04 161 #define MUSB_INTR_BABBLE 0x04 162 #define MUSB_INTR_SOF 0x08 163 #define MUSB_INTR_CONNECT 0x10 164 #define MUSB_INTR_DISCONNECT 0x20 165 #define MUSB_INTR_SESSREQ 0x40 166 #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ 167 168 /* DEVCTL */ 169 #define MUSB_DEVCTL_BDEVICE 0x80 170 #define MUSB_DEVCTL_FSDEV 0x40 171 #define MUSB_DEVCTL_LSDEV 0x20 172 #define MUSB_DEVCTL_VBUS 0x18 173 #define MUSB_DEVCTL_VBUS_SHIFT 3 174 #define MUSB_DEVCTL_HM 0x04 175 #define MUSB_DEVCTL_HR 0x02 176 #define MUSB_DEVCTL_SESSION 0x01 177 178 /* TESTMODE */ 179 #define MUSB_TEST_FORCE_HOST 0x80 180 #define MUSB_TEST_FIFO_ACCESS 0x40 181 #define MUSB_TEST_FORCE_FS 0x20 182 #define MUSB_TEST_FORCE_HS 0x10 183 #define MUSB_TEST_PACKET 0x08 184 #define MUSB_TEST_K 0x04 185 #define MUSB_TEST_J 0x02 186 #define MUSB_TEST_SE0_NAK 0x01 187 188 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ 189 #define MUSB_FIFOSZ_DPB 0x10 190 /* Allocation size (8, 16, 32, ... 4096) */ 191 #define MUSB_FIFOSZ_SIZE 0x0f 192 193 /* CSR0 */ 194 #define MUSB_CSR0_FLUSHFIFO 0x0100 195 #define MUSB_CSR0_TXPKTRDY 0x0002 196 #define MUSB_CSR0_RXPKTRDY 0x0001 197 198 /* CSR0 in Peripheral mode */ 199 #define MUSB_CSR0_P_SVDSETUPEND 0x0080 200 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 201 #define MUSB_CSR0_P_SENDSTALL 0x0020 202 #define MUSB_CSR0_P_SETUPEND 0x0010 203 #define MUSB_CSR0_P_DATAEND 0x0008 204 #define MUSB_CSR0_P_SENTSTALL 0x0004 205 206 /* CSR0 in Host mode */ 207 #define MUSB_CSR0_H_DIS_PING 0x0800 208 #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ 209 #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ 210 #define MUSB_CSR0_H_NAKTIMEOUT 0x0080 211 #define MUSB_CSR0_H_STATUSPKT 0x0040 212 #define MUSB_CSR0_H_REQPKT 0x0020 213 #define MUSB_CSR0_H_ERROR 0x0010 214 #define MUSB_CSR0_H_SETUPPKT 0x0008 215 #define MUSB_CSR0_H_RXSTALL 0x0004 216 217 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ 218 #define MUSB_CSR0_P_WZC_BITS \ 219 (MUSB_CSR0_P_SENTSTALL) 220 #define MUSB_CSR0_H_WZC_BITS \ 221 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ 222 | MUSB_CSR0_RXPKTRDY) 223 224 /* TxType/RxType */ 225 #define MUSB_TYPE_SPEED 0xc0 226 #define MUSB_TYPE_SPEED_SHIFT 6 227 #define MUSB_TYPE_SPEED_HIGH 1 228 #define MUSB_TYPE_SPEED_FULL 2 229 #define MUSB_TYPE_SPEED_LOW 3 230 #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ 231 #define MUSB_TYPE_PROTO_SHIFT 4 232 #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ 233 #define MUSB_TYPE_PROTO_BULK 2 234 #define MUSB_TYPE_PROTO_INTR 3 235 236 /* CONFIGDATA */ 237 #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ 238 #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ 239 #define MUSB_CONFIGDATA_BIGENDIAN 0x20 240 #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ 241 #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ 242 #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ 243 #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ 244 #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ 245 246 /* TXCSR in Peripheral and Host mode */ 247 #define MUSB_TXCSR_AUTOSET 0x8000 248 #define MUSB_TXCSR_MODE 0x2000 249 #define MUSB_TXCSR_DMAENAB 0x1000 250 #define MUSB_TXCSR_FRCDATATOG 0x0800 251 #define MUSB_TXCSR_DMAMODE 0x0400 252 #define MUSB_TXCSR_CLRDATATOG 0x0040 253 #define MUSB_TXCSR_FLUSHFIFO 0x0008 254 #define MUSB_TXCSR_FIFONOTEMPTY 0x0002 255 #define MUSB_TXCSR_TXPKTRDY 0x0001 256 257 /* TXCSR in Peripheral mode */ 258 #define MUSB_TXCSR_P_ISO 0x4000 259 #define MUSB_TXCSR_P_INCOMPTX 0x0080 260 #define MUSB_TXCSR_P_SENTSTALL 0x0020 261 #define MUSB_TXCSR_P_SENDSTALL 0x0010 262 #define MUSB_TXCSR_P_UNDERRUN 0x0004 263 264 /* TXCSR in Host mode */ 265 #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 266 #define MUSB_TXCSR_H_DATATOGGLE 0x0100 267 #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 268 #define MUSB_TXCSR_H_RXSTALL 0x0020 269 #define MUSB_TXCSR_H_ERROR 0x0004 270 #define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8 271 272 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 273 #define MUSB_TXCSR_P_WZC_BITS \ 274 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ 275 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) 276 #define MUSB_TXCSR_H_WZC_BITS \ 277 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ 278 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) 279 280 /* RXCSR in Peripheral and Host mode */ 281 #define MUSB_RXCSR_AUTOCLEAR 0x8000 282 #define MUSB_RXCSR_DMAENAB 0x2000 283 #define MUSB_RXCSR_DISNYET 0x1000 284 #define MUSB_RXCSR_PID_ERR 0x1000 285 #define MUSB_RXCSR_DMAMODE 0x0800 286 #define MUSB_RXCSR_INCOMPRX 0x0100 287 #define MUSB_RXCSR_CLRDATATOG 0x0080 288 #define MUSB_RXCSR_FLUSHFIFO 0x0010 289 #define MUSB_RXCSR_DATAERROR 0x0008 290 #define MUSB_RXCSR_FIFOFULL 0x0002 291 #define MUSB_RXCSR_RXPKTRDY 0x0001 292 293 /* RXCSR in Peripheral mode */ 294 #define MUSB_RXCSR_P_ISO 0x4000 295 #define MUSB_RXCSR_P_SENTSTALL 0x0040 296 #define MUSB_RXCSR_P_SENDSTALL 0x0020 297 #define MUSB_RXCSR_P_OVERRUN 0x0004 298 299 /* RXCSR in Host mode */ 300 #define MUSB_RXCSR_H_AUTOREQ 0x4000 301 #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 302 #define MUSB_RXCSR_H_DATATOGGLE 0x0200 303 #define MUSB_RXCSR_H_RXSTALL 0x0040 304 #define MUSB_RXCSR_H_REQPKT 0x0020 305 #define MUSB_RXCSR_H_ERROR 0x0004 306 #define MUSB_S_RXCSR_H_DATATOGGLE 9 307 308 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 309 #define MUSB_RXCSR_P_WZC_BITS \ 310 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ 311 | MUSB_RXCSR_RXPKTRDY) 312 #define MUSB_RXCSR_H_WZC_BITS \ 313 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ 314 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) 315 316 /* HUBADDR */ 317 #define MUSB_HUBADDR_MULTI_TT 0x80 318 319 /* Endpoint configuration information. Note: The value of endpoint fifo size 320 * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other 321 * values are not supported 322 */ 323 struct musb_epinfo { 324 u8 epnum; /* endpoint number */ 325 u8 epdir; /* endpoint direction */ 326 u16 epsize; /* endpoint FIFO size */ 327 }; 328 329 /* 330 * Platform specific MUSB configuration. Any platform using the musb 331 * functionality should create one instance of this structure in the 332 * platform specific file. 333 */ 334 struct musb_config { 335 struct musb_regs *regs; 336 u32 timeout; 337 u8 musb_speed; 338 }; 339 340 /* externally defined data */ 341 extern struct musb_config musb_cfg; 342 extern struct musb_regs *musbr; 343 344 /* exported functions */ 345 extern void musb_start(void); 346 extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt); 347 extern void write_fifo(u8 ep, u32 length, void *fifo_data); 348 extern void read_fifo(u8 ep, u32 length, void *fifo_data); 349 350 #endif /* __MUSB_HDRC_DEFS_H__ */ 351