1316328f5SSimon Glass /* 2316328f5SSimon Glass * Copyright (c) 2015, Google, Inc 3316328f5SSimon Glass * Written by Simon Glass <sjg@chromium.org> 4316328f5SSimon Glass * All rights reserved. 5316328f5SSimon Glass * 6316328f5SSimon Glass * SPDX-License-Identifier: GPL-2.0 7316328f5SSimon Glass */ 8316328f5SSimon Glass 9316328f5SSimon Glass #include <common.h> 10555a3472SStefan Roese #include <dm.h> 11316328f5SSimon Glass #include <pci.h> 12316328f5SSimon Glass #include <usb.h> 13316328f5SSimon Glass #include "xhci.h" 14316328f5SSimon Glass 15555a3472SStefan Roese static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, 16555a3472SStefan Roese struct xhci_hcor **ret_hcor) 17555a3472SStefan Roese { 18555a3472SStefan Roese struct xhci_hccr *hccr; 19555a3472SStefan Roese struct xhci_hcor *hcor; 20555a3472SStefan Roese u32 cmd; 21555a3472SStefan Roese 22555a3472SStefan Roese hccr = (struct xhci_hccr *)dm_pci_map_bar(dev, 23555a3472SStefan Roese PCI_BASE_ADDRESS_0, PCI_REGION_MEM); 24555a3472SStefan Roese hcor = (struct xhci_hcor *)((uintptr_t) hccr + 25555a3472SStefan Roese HC_LENGTH(xhci_readl(&hccr->cr_capbase))); 26555a3472SStefan Roese 27555a3472SStefan Roese debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", 28555a3472SStefan Roese (u32)hccr, (u32)hcor, 29555a3472SStefan Roese (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase))); 30555a3472SStefan Roese 31555a3472SStefan Roese *ret_hccr = hccr; 32555a3472SStefan Roese *ret_hcor = hcor; 33555a3472SStefan Roese 34555a3472SStefan Roese /* enable busmaster */ 35555a3472SStefan Roese dm_pci_read_config32(dev, PCI_COMMAND, &cmd); 36555a3472SStefan Roese cmd |= PCI_COMMAND_MASTER; 37555a3472SStefan Roese dm_pci_write_config32(dev, PCI_COMMAND, cmd); 38555a3472SStefan Roese } 39555a3472SStefan Roese 40555a3472SStefan Roese static int xhci_pci_probe(struct udevice *dev) 41555a3472SStefan Roese { 42555a3472SStefan Roese struct xhci_hccr *hccr; 43555a3472SStefan Roese struct xhci_hcor *hcor; 44555a3472SStefan Roese 45555a3472SStefan Roese xhci_pci_init(dev, &hccr, &hcor); 46555a3472SStefan Roese 47555a3472SStefan Roese return xhci_register(dev, hccr, hcor); 48555a3472SStefan Roese } 49555a3472SStefan Roese 50555a3472SStefan Roese static const struct udevice_id xhci_pci_ids[] = { 51555a3472SStefan Roese { .compatible = "xhci-pci" }, 52555a3472SStefan Roese { } 53555a3472SStefan Roese }; 54555a3472SStefan Roese 55555a3472SStefan Roese U_BOOT_DRIVER(xhci_pci) = { 56555a3472SStefan Roese .name = "xhci_pci", 57555a3472SStefan Roese .id = UCLASS_USB, 58555a3472SStefan Roese .probe = xhci_pci_probe, 59*5e941943SBin Meng .remove = xhci_deregister, 60555a3472SStefan Roese .of_match = xhci_pci_ids, 61555a3472SStefan Roese .ops = &xhci_usb_ops, 62555a3472SStefan Roese .platdata_auto_alloc_size = sizeof(struct usb_platdata), 63*5e941943SBin Meng .priv_auto_alloc_size = sizeof(struct xhci_ctrl), 64555a3472SStefan Roese .flags = DM_FLAG_ALLOC_PRIV_DMA, 65555a3472SStefan Roese }; 66555a3472SStefan Roese 67555a3472SStefan Roese static struct pci_device_id xhci_pci_supported[] = { 68555a3472SStefan Roese { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0) }, 69555a3472SStefan Roese {}, 70555a3472SStefan Roese }; 71555a3472SStefan Roese 72555a3472SStefan Roese U_BOOT_PCI_DEVICE(xhci_pci, xhci_pci_supported); 73