1 /* 2 * USB 3.0 DRD Controller 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <watchdog.h> 12 #include <usb.h> 13 #include <asm/arch/psc_defs.h> 14 #include <asm/io.h> 15 #include <linux/usb/dwc3.h> 16 #include <asm/arch/xhci-keystone.h> 17 #include <asm-generic/errno.h> 18 #include <linux/list.h> 19 #include "xhci.h" 20 21 struct kdwc3_irq_regs { 22 u32 revision; /* 0x000 */ 23 u32 rsvd0[3]; 24 u32 sysconfig; /* 0x010 */ 25 u32 rsvd1[1]; 26 u32 irq_eoi; 27 u32 rsvd2[1]; 28 struct { 29 u32 raw_status; 30 u32 status; 31 u32 enable_set; 32 u32 enable_clr; 33 } irqs[16]; 34 }; 35 36 struct keystone_xhci { 37 struct xhci_hccr *hcd; 38 struct dwc3 *dwc3_reg; 39 struct xhci_hcor *hcor; 40 struct kdwc3_irq_regs *usbss; 41 struct keystone_xhci_phy *phy; 42 }; 43 44 struct keystone_xhci keystone; 45 46 static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy) 47 { 48 u32 val; 49 50 /* 51 * VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't. 52 * It should always be cleared because our USB PHY has an onchip VBUS 53 * analog comparator. 54 */ 55 val = readl(&phy->phy_clock); 56 /* quit selecting the vbusvldextsel by default! */ 57 val &= ~USB3_PHY_OTG_VBUSVLDECTSEL; 58 writel(val, &phy->phy_clock); 59 } 60 61 static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy) 62 { 63 u32 val; 64 65 /* Disable the PHY REFCLK clock gate */ 66 val = readl(&phy->phy_clock); 67 val &= ~USB3_PHY_REF_SSP_EN; 68 writel(val, &phy->phy_clock); 69 } 70 71 static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 72 { 73 clrsetbits_le32(&dwc3_reg->g_ctl, 74 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 75 DWC3_GCTL_PRTCAPDIR(mode)); 76 } 77 78 static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 79 { 80 /* Before Resetting PHY, put Core in Reset */ 81 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 82 83 /* Assert USB3 PHY reset */ 84 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 85 86 /* Assert USB2 PHY reset */ 87 setbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST); 88 89 mdelay(100); 90 91 /* Clear USB3 PHY reset */ 92 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 93 94 /* Clear USB2 PHY reset */ 95 clrbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST); 96 97 /* After PHYs are stable we can take Core out of reset state */ 98 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 99 } 100 101 static int dwc3_core_init(struct dwc3 *dwc3_reg) 102 { 103 u32 revision, val; 104 unsigned long t_rst; 105 unsigned int dwc3_hwparams1; 106 107 revision = readl(&dwc3_reg->g_snpsid); 108 /* This should read as U3 followed by revision number */ 109 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 110 puts("this is not a DesignWare USB3 DRD Core\n"); 111 return -EINVAL; 112 } 113 114 /* issue device SoftReset too */ 115 writel(DWC3_DCTL_CSFTRST, &dwc3_reg->d_ctl); 116 117 t_rst = get_timer(0); 118 do { 119 val = readl(&dwc3_reg->d_ctl); 120 if (!(val & DWC3_DCTL_CSFTRST)) 121 break; 122 WATCHDOG_RESET(); 123 } while (get_timer(t_rst) < 500); 124 125 if (val & DWC3_DCTL_CSFTRST) { 126 debug("Reset timed out\n"); 127 return -2; 128 } 129 130 dwc3_core_soft_reset(dwc3_reg); 131 132 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 133 134 val = readl(&dwc3_reg->g_ctl); 135 val &= ~DWC3_GCTL_SCALEDOWN_MASK; 136 val &= ~DWC3_GCTL_DISSCRAMBLE; 137 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 138 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 139 val &= ~DWC3_GCTL_DSBLCLKGTNG; 140 break; 141 default: 142 printf("No power optimization available\n"); 143 } 144 145 /* 146 * WORKAROUND: DWC3 revisions <1.90a have a bug 147 * where the device can fail to connect at SuperSpeed 148 * and falls back to high-speed mode which causes 149 * the device to enter a Connect/Disconnect loop 150 */ 151 if ((revision & DWC3_REVISION_MASK) < 0x190a) 152 val |= DWC3_GCTL_U2RSTECN; 153 154 writel(val, &dwc3_reg->g_ctl); 155 156 return 0; 157 } 158 159 static int keystone_xhci_core_init(struct dwc3 *dwc3_reg) 160 { 161 int ret; 162 163 ret = dwc3_core_init(dwc3_reg); 164 if (ret) { 165 debug("failed to initialize core\n"); 166 return -EINVAL; 167 } 168 169 /* We are hard-coding DWC3 core to Host Mode */ 170 dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 171 172 return 0; 173 } 174 175 int xhci_hcd_init(int index, 176 struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor) 177 { 178 u32 val; 179 int ret; 180 struct xhci_hccr *hcd; 181 struct xhci_hcor *hcor; 182 struct kdwc3_irq_regs *usbss; 183 struct keystone_xhci_phy *phy; 184 185 usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE; 186 phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE; 187 188 /* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */ 189 val = readl(&(phy->phy_clock)); 190 val |= USB3_PHY_REF_SSP_EN; 191 writel(val, &phy->phy_clock); 192 193 mdelay(100); 194 195 /* Release USB from reset */ 196 ret = psc_enable_module(KS2_LPSC_USB); 197 if (ret) { 198 puts("Cannot enable USB module"); 199 return -1; 200 } 201 202 mdelay(100); 203 204 /* Initialize usb phy */ 205 keystone_xhci_phy_set(phy); 206 207 /* soft reset usbss */ 208 writel(1, &usbss->sysconfig); 209 while (readl(&usbss->sysconfig) & 1) 210 ; 211 212 val = readl(&usbss->revision); 213 debug("usbss revision %x\n", val); 214 215 /* Initialize usb core */ 216 hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE; 217 keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE + 218 DWC3_REG_OFFSET); 219 220 keystone_xhci_core_init(keystone.dwc3_reg); 221 222 /* set register addresses */ 223 hcor = (struct xhci_hcor *)((uint32_t)hcd + 224 HC_LENGTH(readl(&hcd->cr_capbase))); 225 226 debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n", 227 (u32)hcd, (u32)hcor, 228 (u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase))); 229 230 keystone.usbss = usbss; 231 keystone.phy = phy; 232 keystone.hcd = hcd; 233 keystone.hcor = hcor; 234 235 *ret_hccr = hcd; 236 *ret_hcor = hcor; 237 238 return 0; 239 } 240 241 static int keystone_xhci_phy_suspend(void) 242 { 243 int loop_cnt = 0; 244 struct xhci_hcor *hcor; 245 uint32_t *portsc_1 = NULL; 246 uint32_t *portsc_2 = NULL; 247 u32 val, usb2_pls, usb3_pls, event_q; 248 struct dwc3 *dwc3_reg = keystone.dwc3_reg; 249 250 /* set register addresses */ 251 hcor = keystone.hcor; 252 253 /* Bypass Scrambling and Set Shorter Training sequence for simulation */ 254 val = DWC3_GCTL_PWRDNSCALE(0x4b0) | DWC3_GCTL_PRTCAPDIR(0x2); 255 writel(val, &dwc3_reg->g_ctl); 256 257 /* GUSB2PHYCFG */ 258 val = readl(&dwc3_reg->g_usb2phycfg[0]); 259 260 /* assert bit 6 (SusPhy) */ 261 val |= DWC3_GUSB2PHYCFG_SUSPHY; 262 writel(val, &dwc3_reg->g_usb2phycfg[0]); 263 264 /* GUSB3PIPECTL */ 265 val = readl(&dwc3_reg->g_usb3pipectl[0]); 266 267 /* 268 * assert bit 29 to allow PHY to go to suspend when idle 269 * and cause the USB3 SS PHY to enter suspend mode 270 */ 271 val |= (BIT(29) | DWC3_GUSB3PIPECTL_SUSPHY); 272 writel(val, &dwc3_reg->g_usb3pipectl[0]); 273 274 /* 275 * Steps necessary to allow controller to suspend even when 276 * VBUS is HIGH: 277 * - Init DCFG[2:0] (DevSpd) to: 1=FS 278 * - Init GEVNTADR0 to point to an eventQ 279 * - Init GEVNTSIZ0 to 0x0100 to specify the size of the eventQ 280 * - Init DCTL::Run_nStop = 1 281 */ 282 writel(0x00020001, &dwc3_reg->d_cfg); 283 /* TODO: local2global( (Uint32) eventQ )? */ 284 writel((u32)&event_q, &dwc3_reg->g_evnt_buf[0].g_evntadrlo); 285 writel(0, &dwc3_reg->g_evnt_buf[0].g_evntadrhi); 286 writel(0x4, &dwc3_reg->g_evnt_buf[0].g_evntsiz); 287 /* Run */ 288 writel(DWC3_DCTL_RUN_STOP, &dwc3_reg->d_ctl); 289 290 mdelay(100); 291 292 /* Wait for USB2 & USB3 PORTSC::PortLinkState to indicate suspend */ 293 portsc_1 = (uint32_t *)(&hcor->portregs[0].or_portsc); 294 portsc_2 = (uint32_t *)(&hcor->portregs[1].or_portsc); 295 usb2_pls = 0; 296 usb3_pls = 0; 297 do { 298 ++loop_cnt; 299 usb2_pls = (readl(portsc_1) & PORT_PLS_MASK) >> 5; 300 usb3_pls = (readl(portsc_2) & PORT_PLS_MASK) >> 5; 301 } while (((usb2_pls != 0x4) || (usb3_pls != 0x4)) && loop_cnt < 1000); 302 303 if (usb2_pls != 0x4 || usb3_pls != 0x4) { 304 debug("USB suspend failed - PLS USB2=%02x, USB3=%02x\n", 305 usb2_pls, usb3_pls); 306 return -1; 307 } 308 309 debug("USB2 and USB3 PLS - Disabled, loop_cnt=%d\n", loop_cnt); 310 return 0; 311 } 312 313 void xhci_hcd_stop(int index) 314 { 315 /* Disable USB */ 316 if (keystone_xhci_phy_suspend()) 317 return; 318 319 if (psc_disable_module(KS2_LPSC_USB)) { 320 debug("PSC disable module USB failed!\n"); 321 return; 322 } 323 324 /* Disable PHY */ 325 keystone_xhci_phy_unset(keystone.phy); 326 327 /* memset(&keystone, 0, sizeof(struct keystone_xhci)); */ 328 debug("xhci_hcd_stop OK.\n"); 329 } 330