1 /* 2 * SAMSUNG EXYNOS5 USB HOST XHCI Controller 3 * 4 * Copyright (C) 2012 Samsung Electronics Co.Ltd 5 * Vivek Gautam <gautam.vivek@samsung.com> 6 * Vikas Sajjan <vikas.sajjan@samsung.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * This file is a conglomeration for DWC3-init sequence and further 13 * exynos5 specific PHY-init sequence. 14 */ 15 16 #include <common.h> 17 #include <fdtdec.h> 18 #include <libfdt.h> 19 #include <malloc.h> 20 #include <usb.h> 21 #include <watchdog.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/power.h> 24 #include <asm/arch/xhci-exynos.h> 25 #include <asm-generic/errno.h> 26 #include <linux/compat.h> 27 #include <linux/usb/dwc3.h> 28 29 #include "xhci.h" 30 31 /* Declare global data pointer */ 32 DECLARE_GLOBAL_DATA_PTR; 33 34 /** 35 * Contains pointers to register base addresses 36 * for the usb controller. 37 */ 38 struct exynos_xhci { 39 struct exynos_usb3_phy *usb3_phy; 40 struct xhci_hccr *hcd; 41 struct dwc3 *dwc3_reg; 42 }; 43 44 static struct exynos_xhci exynos; 45 46 #ifdef CONFIG_OF_CONTROL 47 static int exynos_usb3_parse_dt(const void *blob, struct exynos_xhci *exynos) 48 { 49 fdt_addr_t addr; 50 unsigned int node; 51 int depth; 52 53 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_XHCI); 54 if (node <= 0) { 55 debug("XHCI: Can't get device node for xhci\n"); 56 return -ENODEV; 57 } 58 59 /* 60 * Get the base address for XHCI controller from the device node 61 */ 62 addr = fdtdec_get_addr(blob, node, "reg"); 63 if (addr == FDT_ADDR_T_NONE) { 64 debug("Can't get the XHCI register base address\n"); 65 return -ENXIO; 66 } 67 exynos->hcd = (struct xhci_hccr *)addr; 68 69 depth = 0; 70 node = fdtdec_next_compatible_subnode(blob, node, 71 COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth); 72 if (node <= 0) { 73 debug("XHCI: Can't get device node for usb3-phy controller\n"); 74 return -ENODEV; 75 } 76 77 /* 78 * Get the base address for usbphy from the device node 79 */ 80 exynos->usb3_phy = (struct exynos_usb3_phy *)fdtdec_get_addr(blob, node, 81 "reg"); 82 if (exynos->usb3_phy == NULL) { 83 debug("Can't get the usbphy register address\n"); 84 return -ENXIO; 85 } 86 87 return 0; 88 } 89 #endif 90 91 static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy) 92 { 93 u32 reg; 94 95 /* enabling usb_drd phy */ 96 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN); 97 98 /* Reset USB 3.0 PHY */ 99 writel(0x0, &phy->phy_reg0); 100 101 clrbits_le32(&phy->phy_param0, 102 /* Select PHY CLK source */ 103 PHYPARAM0_REF_USE_PAD | 104 /* Set Loss-of-Signal Detector sensitivity */ 105 PHYPARAM0_REF_LOSLEVEL_MASK); 106 setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL); 107 108 writel(0x0, &phy->phy_resume); 109 110 /* 111 * Setting the Frame length Adj value[6:1] to default 0x20 112 * See xHCI 1.0 spec, 5.2.4 113 */ 114 setbits_le32(&phy->link_system, 115 LINKSYSTEM_XHCI_VERSION_CONTROL | 116 LINKSYSTEM_FLADJ(0x20)); 117 118 /* Set Tx De-Emphasis level */ 119 clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK); 120 setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH); 121 122 setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL); 123 124 /* PHYTEST POWERDOWN Control */ 125 clrbits_le32(&phy->phy_test, 126 PHYTEST_POWERDOWN_SSP | 127 PHYTEST_POWERDOWN_HSP); 128 129 /* UTMI Power Control */ 130 writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi); 131 132 /* Use core clock from main PLL */ 133 reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK | 134 /* Default 24Mhz crystal clock */ 135 PHYCLKRST_FSEL(FSEL_CLKSEL_24M) | 136 PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | 137 PHYCLKRST_SSC_REFCLKSEL(0x88) | 138 /* Force PortReset of PHY */ 139 PHYCLKRST_PORTRESET | 140 /* Digital power supply in normal operating mode */ 141 PHYCLKRST_RETENABLEN | 142 /* Enable ref clock for SS function */ 143 PHYCLKRST_REF_SSP_EN | 144 /* Enable spread spectrum */ 145 PHYCLKRST_SSC_EN | 146 /* Power down HS Bias and PLL blocks in suspend mode */ 147 PHYCLKRST_COMMONONN; 148 149 writel(reg, &phy->phy_clk_rst); 150 151 /* giving time to Phy clock to settle before resetting */ 152 udelay(10); 153 154 reg &= ~PHYCLKRST_PORTRESET; 155 writel(reg, &phy->phy_clk_rst); 156 } 157 158 static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy) 159 { 160 setbits_le32(&phy->phy_utmi, 161 PHYUTMI_OTGDISABLE | 162 PHYUTMI_FORCESUSPEND | 163 PHYUTMI_FORCESLEEP); 164 165 clrbits_le32(&phy->phy_clk_rst, 166 PHYCLKRST_REF_SSP_EN | 167 PHYCLKRST_SSC_EN | 168 PHYCLKRST_COMMONONN); 169 170 /* PHYTEST POWERDOWN Control to remove leakage current */ 171 setbits_le32(&phy->phy_test, 172 PHYTEST_POWERDOWN_SSP | 173 PHYTEST_POWERDOWN_HSP); 174 175 /* disabling usb_drd phy */ 176 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE); 177 } 178 179 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 180 { 181 clrsetbits_le32(&dwc3_reg->g_ctl, 182 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 183 DWC3_GCTL_PRTCAPDIR(mode)); 184 } 185 186 static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 187 { 188 /* Before Resetting PHY, put Core in Reset */ 189 setbits_le32(&dwc3_reg->g_ctl, 190 DWC3_GCTL_CORESOFTRESET); 191 192 /* Assert USB3 PHY reset */ 193 setbits_le32(&dwc3_reg->g_usb3pipectl[0], 194 DWC3_GUSB3PIPECTL_PHYSOFTRST); 195 196 /* Assert USB2 PHY reset */ 197 setbits_le32(&dwc3_reg->g_usb2phycfg, 198 DWC3_GUSB2PHYCFG_PHYSOFTRST); 199 200 mdelay(100); 201 202 /* Clear USB3 PHY reset */ 203 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], 204 DWC3_GUSB3PIPECTL_PHYSOFTRST); 205 206 /* Clear USB2 PHY reset */ 207 clrbits_le32(&dwc3_reg->g_usb2phycfg, 208 DWC3_GUSB2PHYCFG_PHYSOFTRST); 209 210 /* After PHYs are stable we can take Core out of reset state */ 211 clrbits_le32(&dwc3_reg->g_ctl, 212 DWC3_GCTL_CORESOFTRESET); 213 } 214 215 static int dwc3_core_init(struct dwc3 *dwc3_reg) 216 { 217 u32 reg; 218 u32 revision; 219 unsigned int dwc3_hwparams1; 220 221 revision = readl(&dwc3_reg->g_snpsid); 222 /* This should read as U3 followed by revision number */ 223 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 224 puts("this is not a DesignWare USB3 DRD Core\n"); 225 return -EINVAL; 226 } 227 228 dwc3_core_soft_reset(dwc3_reg); 229 230 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 231 232 reg = readl(&dwc3_reg->g_ctl); 233 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 234 reg &= ~DWC3_GCTL_DISSCRAMBLE; 235 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 236 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 237 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 238 break; 239 default: 240 debug("No power optimization available\n"); 241 } 242 243 /* 244 * WORKAROUND: DWC3 revisions <1.90a have a bug 245 * where the device can fail to connect at SuperSpeed 246 * and falls back to high-speed mode which causes 247 * the device to enter a Connect/Disconnect loop 248 */ 249 if ((revision & DWC3_REVISION_MASK) < 0x190a) 250 reg |= DWC3_GCTL_U2RSTECN; 251 252 writel(reg, &dwc3_reg->g_ctl); 253 254 return 0; 255 } 256 257 static int exynos_xhci_core_init(struct exynos_xhci *exynos) 258 { 259 int ret; 260 261 exynos5_usb3_phy_init(exynos->usb3_phy); 262 263 ret = dwc3_core_init(exynos->dwc3_reg); 264 if (ret) { 265 debug("failed to initialize core\n"); 266 return -EINVAL; 267 } 268 269 /* We are hard-coding DWC3 core to Host Mode */ 270 dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 271 272 return 0; 273 } 274 275 static void exynos_xhci_core_exit(struct exynos_xhci *exynos) 276 { 277 exynos5_usb3_phy_exit(exynos->usb3_phy); 278 } 279 280 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) 281 { 282 struct exynos_xhci *ctx = &exynos; 283 int ret; 284 285 #ifdef CONFIG_OF_CONTROL 286 exynos_usb3_parse_dt(gd->fdt_blob, ctx); 287 #else 288 ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy(); 289 ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci(); 290 #endif 291 292 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 293 294 ret = exynos_xhci_core_init(ctx); 295 if (ret) { 296 puts("XHCI: failed to initialize controller\n"); 297 return -EINVAL; 298 } 299 300 *hccr = (ctx->hcd); 301 *hcor = (struct xhci_hcor *)((uint32_t) *hccr 302 + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); 303 304 debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d\n", 305 (uint32_t)*hccr, (uint32_t)*hcor, 306 (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); 307 308 return 0; 309 } 310 311 void xhci_hcd_stop(int index) 312 { 313 struct exynos_xhci *ctx = &exynos; 314 315 exynos_xhci_core_exit(ctx); 316 } 317