1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * DWC3 controller driver 5 * 6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <fdtdec.h> 14 #include <generic-phy.h> 15 #include <usb.h> 16 17 #include "xhci.h" 18 #include <asm/io.h> 19 #include <linux/usb/dwc3.h> 20 #include <linux/usb/otg.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 struct xhci_dwc3_platdata { 25 struct phy *usb_phys; 26 int num_phys; 27 }; 28 29 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 30 { 31 clrsetbits_le32(&dwc3_reg->g_ctl, 32 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 33 DWC3_GCTL_PRTCAPDIR(mode)); 34 } 35 36 static void dwc3_phy_reset(struct dwc3 *dwc3_reg) 37 { 38 /* Assert USB3 PHY reset */ 39 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 40 41 /* Assert USB2 PHY reset */ 42 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 43 44 mdelay(100); 45 46 /* Clear USB3 PHY reset */ 47 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 48 49 /* Clear USB2 PHY reset */ 50 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 51 } 52 53 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 54 { 55 /* Before Resetting PHY, put Core in Reset */ 56 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 57 58 /* reset USB3 phy - if required */ 59 dwc3_phy_reset(dwc3_reg); 60 61 mdelay(100); 62 63 /* After PHYs are stable we can take Core out of reset state */ 64 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 65 } 66 67 int dwc3_core_init(struct dwc3 *dwc3_reg) 68 { 69 u32 reg; 70 u32 revision; 71 unsigned int dwc3_hwparams1; 72 73 revision = readl(&dwc3_reg->g_snpsid); 74 /* This should read as U3 followed by revision number */ 75 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 76 puts("this is not a DesignWare USB3 DRD Core\n"); 77 return -1; 78 } 79 80 dwc3_core_soft_reset(dwc3_reg); 81 82 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 83 84 reg = readl(&dwc3_reg->g_ctl); 85 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 86 reg &= ~DWC3_GCTL_DISSCRAMBLE; 87 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 88 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 89 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 90 break; 91 default: 92 debug("No power optimization available\n"); 93 } 94 95 /* 96 * WORKAROUND: DWC3 revisions <1.90a have a bug 97 * where the device can fail to connect at SuperSpeed 98 * and falls back to high-speed mode which causes 99 * the device to enter a Connect/Disconnect loop 100 */ 101 if ((revision & DWC3_REVISION_MASK) < 0x190a) 102 reg |= DWC3_GCTL_U2RSTECN; 103 104 writel(reg, &dwc3_reg->g_ctl); 105 106 return 0; 107 } 108 109 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) 110 { 111 setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL | 112 GFLADJ_30MHZ(val)); 113 } 114 115 #ifdef CONFIG_DM_USB 116 static int xhci_dwc3_setup_phy(struct udevice *dev) 117 { 118 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 119 int i, ret, count; 120 121 /* Return if no phy declared */ 122 if (!dev_read_prop(dev, "phys", NULL)) 123 return 0; 124 125 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); 126 if (count <= 0) 127 return count; 128 129 plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), 130 GFP_KERNEL); 131 if (!plat->usb_phys) 132 return -ENOMEM; 133 134 for (i = 0; i < count; i++) { 135 ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]); 136 if (ret && ret != -ENOENT) { 137 pr_err("Failed to get USB PHY%d for %s\n", 138 i, dev->name); 139 return ret; 140 } 141 142 ++plat->num_phys; 143 } 144 145 for (i = 0; i < plat->num_phys; i++) { 146 ret = generic_phy_init(&plat->usb_phys[i]); 147 if (ret) { 148 pr_err("Can't init USB PHY%d for %s\n", 149 i, dev->name); 150 goto phys_init_err; 151 } 152 } 153 154 for (i = 0; i < plat->num_phys; i++) { 155 ret = generic_phy_power_on(&plat->usb_phys[i]); 156 if (ret) { 157 pr_err("Can't power USB PHY%d for %s\n", 158 i, dev->name); 159 goto phys_poweron_err; 160 } 161 } 162 163 return 0; 164 165 phys_poweron_err: 166 for (; i >= 0; i--) 167 generic_phy_power_off(&plat->usb_phys[i]); 168 169 for (i = 0; i < plat->num_phys; i++) 170 generic_phy_exit(&plat->usb_phys[i]); 171 172 return ret; 173 174 phys_init_err: 175 for (; i >= 0; i--) 176 generic_phy_exit(&plat->usb_phys[i]); 177 178 return ret; 179 } 180 181 static int xhci_dwc3_shutdown_phy(struct udevice *dev) 182 { 183 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 184 int i, ret; 185 186 for (i = 0; i < plat->num_phys; i++) { 187 if (!generic_phy_valid(&plat->usb_phys[i])) 188 continue; 189 190 ret = generic_phy_power_off(&plat->usb_phys[i]); 191 ret |= generic_phy_exit(&plat->usb_phys[i]); 192 if (ret) { 193 pr_err("Can't shutdown USB PHY%d for %s\n", 194 i, dev->name); 195 } 196 } 197 198 return 0; 199 } 200 201 static int xhci_dwc3_probe(struct udevice *dev) 202 { 203 struct xhci_hcor *hcor; 204 struct xhci_hccr *hccr; 205 struct dwc3 *dwc3_reg; 206 enum usb_dr_mode dr_mode; 207 int ret; 208 209 hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev)); 210 hcor = (struct xhci_hcor *)((uintptr_t)hccr + 211 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); 212 213 ret = xhci_dwc3_setup_phy(dev); 214 if (ret) 215 return ret; 216 217 dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET); 218 219 dwc3_core_init(dwc3_reg); 220 221 dr_mode = usb_get_dr_mode(dev_of_offset(dev)); 222 if (dr_mode == USB_DR_MODE_UNKNOWN) 223 /* by default set dual role mode to HOST */ 224 dr_mode = USB_DR_MODE_HOST; 225 226 dwc3_set_mode(dwc3_reg, dr_mode); 227 228 return xhci_register(dev, hccr, hcor); 229 } 230 231 static int xhci_dwc3_remove(struct udevice *dev) 232 { 233 xhci_dwc3_shutdown_phy(dev); 234 235 return xhci_deregister(dev); 236 } 237 238 static const struct udevice_id xhci_dwc3_ids[] = { 239 { .compatible = "snps,dwc3" }, 240 { } 241 }; 242 243 U_BOOT_DRIVER(xhci_dwc3) = { 244 .name = "xhci-dwc3", 245 .id = UCLASS_USB, 246 .of_match = xhci_dwc3_ids, 247 .probe = xhci_dwc3_probe, 248 .remove = xhci_dwc3_remove, 249 .ops = &xhci_usb_ops, 250 .priv_auto_alloc_size = sizeof(struct xhci_ctrl), 251 .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata), 252 .flags = DM_FLAG_ALLOC_PRIV_DMA, 253 }; 254 #endif 255