1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * DWC3 controller driver 5 * 6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <fdtdec.h> 14 #include <generic-phy.h> 15 #include <usb.h> 16 #include <dwc3-uboot.h> 17 18 #include <usb/xhci.h> 19 #include <asm/io.h> 20 #include <linux/usb/dwc3.h> 21 #include <linux/usb/otg.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 struct xhci_dwc3_platdata { 26 struct phy *usb_phys; 27 int num_phys; 28 }; 29 30 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 31 { 32 clrsetbits_le32(&dwc3_reg->g_ctl, 33 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 34 DWC3_GCTL_PRTCAPDIR(mode)); 35 } 36 37 static void dwc3_phy_reset(struct dwc3 *dwc3_reg) 38 { 39 /* Assert USB3 PHY reset */ 40 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 41 42 /* Assert USB2 PHY reset */ 43 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 44 45 mdelay(100); 46 47 /* Clear USB3 PHY reset */ 48 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 49 50 /* Clear USB2 PHY reset */ 51 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 52 } 53 54 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 55 { 56 /* Before Resetting PHY, put Core in Reset */ 57 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 58 59 /* reset USB3 phy - if required */ 60 dwc3_phy_reset(dwc3_reg); 61 62 mdelay(100); 63 64 /* After PHYs are stable we can take Core out of reset state */ 65 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 66 } 67 68 int dwc3_core_init(struct dwc3 *dwc3_reg) 69 { 70 u32 reg; 71 u32 revision; 72 unsigned int dwc3_hwparams1; 73 74 revision = readl(&dwc3_reg->g_snpsid); 75 /* This should read as U3 followed by revision number */ 76 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 77 puts("this is not a DesignWare USB3 DRD Core\n"); 78 return -1; 79 } 80 81 dwc3_core_soft_reset(dwc3_reg); 82 83 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 84 85 reg = readl(&dwc3_reg->g_ctl); 86 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 87 reg &= ~DWC3_GCTL_DISSCRAMBLE; 88 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 89 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 90 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 91 break; 92 default: 93 debug("No power optimization available\n"); 94 } 95 96 /* 97 * WORKAROUND: DWC3 revisions <1.90a have a bug 98 * where the device can fail to connect at SuperSpeed 99 * and falls back to high-speed mode which causes 100 * the device to enter a Connect/Disconnect loop 101 */ 102 if ((revision & DWC3_REVISION_MASK) < 0x190a) 103 reg |= DWC3_GCTL_U2RSTECN; 104 105 writel(reg, &dwc3_reg->g_ctl); 106 107 return 0; 108 } 109 110 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) 111 { 112 setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL | 113 GFLADJ_30MHZ(val)); 114 } 115 116 #if CONFIG_IS_ENABLED(DM_USB) 117 static int xhci_dwc3_probe(struct udevice *dev) 118 { 119 struct xhci_hcor *hcor; 120 struct xhci_hccr *hccr; 121 struct dwc3 *dwc3_reg; 122 enum usb_dr_mode dr_mode; 123 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 124 const char *phy; 125 u32 reg; 126 int ret; 127 128 hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev)); 129 hcor = (struct xhci_hcor *)((uintptr_t)hccr + 130 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); 131 132 ret = dwc3_setup_phy(dev, &plat->usb_phys, &plat->num_phys); 133 if (ret && (ret != -ENOTSUPP)) 134 return ret; 135 136 dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET); 137 138 dwc3_core_init(dwc3_reg); 139 140 /* Set dwc3 usb2 phy config */ 141 reg = readl(&dwc3_reg->g_usb2phycfg[0]); 142 143 phy = dev_read_string(dev, "phy_type"); 144 if (phy && strcmp(phy, "utmi_wide") == 0) { 145 reg |= DWC3_GUSB2PHYCFG_PHYIF; 146 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 147 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; 148 } 149 150 if (dev_read_bool(dev, "snps,dis_enblslpm-quirk")) 151 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 152 153 if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk")) 154 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 155 156 if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk")) 157 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 158 159 writel(reg, &dwc3_reg->g_usb2phycfg[0]); 160 161 dr_mode = usb_get_dr_mode(dev_of_offset(dev)); 162 if (dr_mode == USB_DR_MODE_UNKNOWN) 163 /* by default set dual role mode to HOST */ 164 dr_mode = USB_DR_MODE_HOST; 165 166 dwc3_set_mode(dwc3_reg, dr_mode); 167 168 return xhci_register(dev, hccr, hcor); 169 } 170 171 static int xhci_dwc3_remove(struct udevice *dev) 172 { 173 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 174 175 dwc3_shutdown_phy(dev, plat->usb_phys, plat->num_phys); 176 177 return xhci_deregister(dev); 178 } 179 180 static const struct udevice_id xhci_dwc3_ids[] = { 181 { .compatible = "snps,dwc3" }, 182 { } 183 }; 184 185 U_BOOT_DRIVER(xhci_dwc3) = { 186 .name = "xhci-dwc3", 187 .id = UCLASS_USB, 188 .of_match = xhci_dwc3_ids, 189 .probe = xhci_dwc3_probe, 190 .remove = xhci_dwc3_remove, 191 .ops = &xhci_usb_ops, 192 .priv_auto_alloc_size = sizeof(struct xhci_ctrl), 193 .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata), 194 .flags = DM_FLAG_ALLOC_PRIV_DMA, 195 }; 196 #endif 197