xref: /rk3399_rockchip-uboot/drivers/usb/host/utmi-armada100.c (revision c7c47ca246205ca9c534230b0278507488c5cec3)
1732c7c24SAjay Bhargav /*
2732c7c24SAjay Bhargav  * (C) Copyright 2012
3732c7c24SAjay Bhargav  * eInfochips Ltd. <www.einfochips.com>
4*c7c47ca2SAjay Bhargav  * Written-by: Ajay Bhargav <contact@8051projects.net>
5732c7c24SAjay Bhargav  *
6732c7c24SAjay Bhargav  * (C) Copyright 2009
7732c7c24SAjay Bhargav  * Marvell Semiconductor <www.marvell.com>
8732c7c24SAjay Bhargav  *
91a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
10732c7c24SAjay Bhargav  */
11732c7c24SAjay Bhargav 
12732c7c24SAjay Bhargav #include <common.h>
13732c7c24SAjay Bhargav #include <asm/io.h>
14732c7c24SAjay Bhargav #include <usb.h>
15732c7c24SAjay Bhargav #include <asm/arch/cpu.h>
16732c7c24SAjay Bhargav #include <asm/arch/armada100.h>
17732c7c24SAjay Bhargav #include <asm/arch/utmi-armada100.h>
18732c7c24SAjay Bhargav 
utmi_phy_init(void)19732c7c24SAjay Bhargav static int utmi_phy_init(void)
20732c7c24SAjay Bhargav {
21732c7c24SAjay Bhargav 	struct armd1usb_phy_reg *phy_regs =
22732c7c24SAjay Bhargav 		(struct armd1usb_phy_reg *)UTMI_PHY_BASE;
23732c7c24SAjay Bhargav 	int timeout;
24732c7c24SAjay Bhargav 
25732c7c24SAjay Bhargav 	setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
26732c7c24SAjay Bhargav 	udelay(1000);
27732c7c24SAjay Bhargav 	setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
28732c7c24SAjay Bhargav 
29732c7c24SAjay Bhargav 	clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
30732c7c24SAjay Bhargav 	setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
31732c7c24SAjay Bhargav 
32732c7c24SAjay Bhargav 	setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
33732c7c24SAjay Bhargav 
34732c7c24SAjay Bhargav 	/* Calibrate pll */
35732c7c24SAjay Bhargav 	timeout = 10000;
36732c7c24SAjay Bhargav 	while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
37732c7c24SAjay Bhargav 		;
38732c7c24SAjay Bhargav 	if (!timeout)
39732c7c24SAjay Bhargav 		return -1;
40732c7c24SAjay Bhargav 
41732c7c24SAjay Bhargav 	udelay(200);
42732c7c24SAjay Bhargav 	setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
43732c7c24SAjay Bhargav 	udelay(400);
44732c7c24SAjay Bhargav 	clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
45732c7c24SAjay Bhargav 
46732c7c24SAjay Bhargav 	udelay(200);
47732c7c24SAjay Bhargav 	setbits_le32(&phy_regs->utmi_tx, RCAL_START);
48732c7c24SAjay Bhargav 	udelay(400);
49732c7c24SAjay Bhargav 	clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
50732c7c24SAjay Bhargav 
51732c7c24SAjay Bhargav 	timeout = 10000;
52732c7c24SAjay Bhargav 	while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
53732c7c24SAjay Bhargav 		;
54732c7c24SAjay Bhargav 	if (!timeout)
55732c7c24SAjay Bhargav 		return -1;
56732c7c24SAjay Bhargav 
57732c7c24SAjay Bhargav 	return 0;
58732c7c24SAjay Bhargav }
59732c7c24SAjay Bhargav 
60732c7c24SAjay Bhargav /*
61732c7c24SAjay Bhargav  * Initialize USB host controller's UTMI Physical interface
62732c7c24SAjay Bhargav  */
utmi_init(void)63732c7c24SAjay Bhargav int utmi_init(void)
64732c7c24SAjay Bhargav {
65732c7c24SAjay Bhargav 	struct armd1mpmu_registers *mpmu_regs =
66732c7c24SAjay Bhargav 		(struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
67732c7c24SAjay Bhargav 
68732c7c24SAjay Bhargav 	struct armd1apmu_registers *apmu_regs =
69732c7c24SAjay Bhargav 		(struct armd1apmu_registers *)ARMD1_APMU_BASE;
70732c7c24SAjay Bhargav 
71732c7c24SAjay Bhargav 	/* Turn on 26Mhz ref clock for UTMI PLL */
72732c7c24SAjay Bhargav 	setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
73732c7c24SAjay Bhargav 
74732c7c24SAjay Bhargav 	/* USB Clock reset */
75732c7c24SAjay Bhargav 	writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
76732c7c24SAjay Bhargav 	writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
77732c7c24SAjay Bhargav 
78732c7c24SAjay Bhargav 	/* Initialize UTMI transceiver */
79732c7c24SAjay Bhargav 	return utmi_phy_init();
80732c7c24SAjay Bhargav }
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