1 /* 2 * R8A66597 HCD (Host Controller Driver) for u-boot 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #ifndef __R8A66597_H__ 10 #define __R8A66597_H__ 11 12 #define SYSCFG0 0x00 13 #define SYSCFG1 0x02 14 #define SYSSTS0 0x04 15 #define SYSSTS1 0x06 16 #define DVSTCTR0 0x08 17 #define DVSTCTR1 0x0A 18 #define TESTMODE 0x0C 19 #define PINCFG 0x0E 20 #define DMA0CFG 0x10 21 #define DMA1CFG 0x12 22 #define CFIFO 0x14 23 #define D0FIFO 0x18 24 #define D1FIFO 0x1C 25 #define CFIFOSEL 0x20 26 #define CFIFOCTR 0x22 27 #define CFIFOSIE 0x24 28 #define D0FIFOSEL 0x28 29 #define D0FIFOCTR 0x2A 30 #define D1FIFOSEL 0x2C 31 #define D1FIFOCTR 0x2E 32 #define INTENB0 0x30 33 #define INTENB1 0x32 34 #define INTENB2 0x34 35 #define BRDYENB 0x36 36 #define NRDYENB 0x38 37 #define BEMPENB 0x3A 38 #define SOFCFG 0x3C 39 #define INTSTS0 0x40 40 #define INTSTS1 0x42 41 #define INTSTS2 0x44 42 #define BRDYSTS 0x46 43 #define NRDYSTS 0x48 44 #define BEMPSTS 0x4A 45 #define FRMNUM 0x4C 46 #define UFRMNUM 0x4E 47 #define USBADDR 0x50 48 #define USBREQ 0x54 49 #define USBVAL 0x56 50 #define USBINDX 0x58 51 #define USBLENG 0x5A 52 #define DCPCFG 0x5C 53 #define DCPMAXP 0x5E 54 #define DCPCTR 0x60 55 #define PIPESEL 0x64 56 #define PIPECFG 0x68 57 #define PIPEBUF 0x6A 58 #define PIPEMAXP 0x6C 59 #define PIPEPERI 0x6E 60 #define PIPE1CTR 0x70 61 #define PIPE2CTR 0x72 62 #define PIPE3CTR 0x74 63 #define PIPE4CTR 0x76 64 #define PIPE5CTR 0x78 65 #define PIPE6CTR 0x7A 66 #define PIPE7CTR 0x7C 67 #define PIPE8CTR 0x7E 68 #define PIPE9CTR 0x80 69 #define PIPE1TRE 0x90 70 #define PIPE1TRN 0x92 71 #define PIPE2TRE 0x94 72 #define PIPE2TRN 0x96 73 #define PIPE3TRE 0x98 74 #define PIPE3TRN 0x9A 75 #define PIPE4TRE 0x9C 76 #define PIPE4TRN 0x9E 77 #define PIPE5TRE 0xA0 78 #define PIPE5TRN 0xA2 79 #define DEVADD0 0xD0 80 #define DEVADD1 0xD2 81 #define DEVADD2 0xD4 82 #define DEVADD3 0xD6 83 #define DEVADD4 0xD8 84 #define DEVADD5 0xDA 85 #define DEVADD6 0xDC 86 #define DEVADD7 0xDE 87 #define DEVADD8 0xE0 88 #define DEVADD9 0xE2 89 #define DEVADDA 0xE4 90 #define SUSPMODE0 0x102 /* RZ/A only */ 91 92 /* System Configuration Control Register */ 93 #define HSE 0x0080 /* b7: Hi-speed enable */ 94 #define DCFM 0x0040 /* b6: Controller function select */ 95 #define DRPD 0x0020 /* b5: D+/- pull down control */ 96 #define DPRPU 0x0010 /* b4: D+ pull up control */ 97 #define XTAL 0x0004 /* b2: Crystal selection */ 98 #define XTAL12 0x0004 /* 12MHz */ 99 #define XTAL48 0x0000 /* 48MHz */ 100 #define UPLLE 0x0002 /* b1: internal PLL control */ 101 #define USBE 0x0001 /* b0: USB module operation enable */ 102 103 /* System Configuration Status Register */ 104 #define OVCBIT 0x8000 /* b15-14: Over-current bit */ 105 #define OVCMON 0xC000 /* b15-14: Over-current monitor */ 106 #define SOFEA 0x0020 /* b5: SOF monitor */ 107 #define IDMON 0x0004 /* b3: ID-pin monitor */ 108 #define LNST 0x0003 /* b1-0: D+, D- line status */ 109 #define SE1 0x0003 /* SE1 */ 110 #define FS_KSTS 0x0002 /* Full-Speed K State */ 111 #define FS_JSTS 0x0001 /* Full-Speed J State */ 112 #define LS_JSTS 0x0002 /* Low-Speed J State */ 113 #define LS_KSTS 0x0001 /* Low-Speed K State */ 114 #define SE0 0x0000 /* SE0 */ 115 116 /* Device State Control Register */ 117 #define EXTLP0 0x0400 /* b10: External port */ 118 #define VBOUT 0x0200 /* b9: VBUS output */ 119 #define WKUP 0x0100 /* b8: Remote wakeup */ 120 #define RWUPE 0x0080 /* b7: Remote wakeup sense */ 121 #define USBRST 0x0040 /* b6: USB reset enable */ 122 #define RESUME 0x0020 /* b5: Resume enable */ 123 #define UACT 0x0010 /* b4: USB bus enable */ 124 #define RHST 0x0007 /* b1-0: Reset handshake status */ 125 #define HSPROC 0x0004 /* HS handshake is processing */ 126 #define HSMODE 0x0003 /* Hi-Speed mode */ 127 #define FSMODE 0x0002 /* Full-Speed mode */ 128 #define LSMODE 0x0001 /* Low-Speed mode */ 129 #define UNDECID 0x0000 /* Undecided */ 130 131 /* Test Mode Register */ 132 #define UTST 0x000F /* b3-0: Test select */ 133 #define H_TST_PACKET 0x000C /* HOST TEST Packet */ 134 #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ 135 #define H_TST_K 0x000A /* HOST TEST K */ 136 #define H_TST_J 0x0009 /* HOST TEST J */ 137 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */ 138 #define P_TST_PACKET 0x0004 /* PERI TEST Packet */ 139 #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ 140 #define P_TST_K 0x0002 /* PERI TEST K */ 141 #define P_TST_J 0x0001 /* PERI TEST J */ 142 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 143 144 /* Data Pin Configuration Register */ 145 #define LDRV 0x8000 /* b15: Drive Current Adjust */ 146 #define VIF1 0x0000 /* VIF = 1.8V */ 147 #define VIF3 0x8000 /* VIF = 3.3V */ 148 #define INTA 0x0001 /* b1: USB INT-pin active */ 149 150 /* DMAx Pin Configuration Register */ 151 #define DREQA 0x4000 /* b14: Dreq active select */ 152 #define BURST 0x2000 /* b13: Burst mode */ 153 #define DACKA 0x0400 /* b10: Dack active select */ 154 #define DFORM 0x0380 /* b9-7: DMA mode select */ 155 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ 156 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ 157 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ 158 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ 159 #define DENDA 0x0040 /* b6: Dend active select */ 160 #define PKTM 0x0020 /* b5: Packet mode */ 161 #define DENDE 0x0010 /* b4: Dend enable */ 162 #define OBUS 0x0004 /* b2: OUTbus mode */ 163 164 /* CFIFO/DxFIFO Port Select Register */ 165 #define RCNT 0x8000 /* b15: Read count mode */ 166 #define REW 0x4000 /* b14: Buffer rewind */ 167 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */ 168 #define DREQE 0x1000 /* b12: DREQ output enable */ 169 #define MBW 0x0800 /* b10: Maximum bit width for FIFO access */ 170 #define MBW_8 0x0000 /* 8bit */ 171 #define MBW_16 0x0400 /* 16bit */ 172 #define MBW_32 0x0800 /* 32bit */ 173 #define BIGEND 0x0100 /* b8: Big endian mode */ 174 #define BYTE_LITTLE 0x0000 /* little dendian */ 175 #define BYTE_BIG 0x0100 /* big endifan */ 176 #define ISEL 0x0020 /* b5: DCP FIFO port direction select */ 177 #define CURPIPE 0x000F /* b2-0: PIPE select */ 178 179 /* CFIFO/DxFIFO Port Control Register */ 180 #define BVAL 0x8000 /* b15: Buffer valid flag */ 181 #define BCLR 0x4000 /* b14: Buffer clear */ 182 #define FRDY 0x2000 /* b13: FIFO ready */ 183 #define DTLN 0x0FFF /* b11-0: FIFO received data length */ 184 185 /* Interrupt Enable Register 0 */ 186 #define VBSE 0x8000 /* b15: VBUS interrupt */ 187 #define RSME 0x4000 /* b14: Resume interrupt */ 188 #define SOFE 0x2000 /* b13: Frame update interrupt */ 189 #define DVSE 0x1000 /* b12: Device state transition interrupt */ 190 #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ 191 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */ 192 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ 193 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */ 194 195 /* Interrupt Enable Register 1 */ 196 #define OVRCRE 0x8000 /* b15: Over-current interrupt */ 197 #define BCHGE 0x4000 /* b14: USB us chenge interrupt */ 198 #define DTCHE 0x1000 /* b12: Detach sense interrupt */ 199 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */ 200 #define EOFERRE 0x0040 /* b6: EOF error interrupt */ 201 #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ 202 #define SACKE 0x0010 /* b4: SETUP ACK interrupt */ 203 204 /* BRDY Interrupt Enable/Status Register */ 205 #define BRDY9 0x0200 /* b9: PIPE9 */ 206 #define BRDY8 0x0100 /* b8: PIPE8 */ 207 #define BRDY7 0x0080 /* b7: PIPE7 */ 208 #define BRDY6 0x0040 /* b6: PIPE6 */ 209 #define BRDY5 0x0020 /* b5: PIPE5 */ 210 #define BRDY4 0x0010 /* b4: PIPE4 */ 211 #define BRDY3 0x0008 /* b3: PIPE3 */ 212 #define BRDY2 0x0004 /* b2: PIPE2 */ 213 #define BRDY1 0x0002 /* b1: PIPE1 */ 214 #define BRDY0 0x0001 /* b1: PIPE0 */ 215 216 /* NRDY Interrupt Enable/Status Register */ 217 #define NRDY9 0x0200 /* b9: PIPE9 */ 218 #define NRDY8 0x0100 /* b8: PIPE8 */ 219 #define NRDY7 0x0080 /* b7: PIPE7 */ 220 #define NRDY6 0x0040 /* b6: PIPE6 */ 221 #define NRDY5 0x0020 /* b5: PIPE5 */ 222 #define NRDY4 0x0010 /* b4: PIPE4 */ 223 #define NRDY3 0x0008 /* b3: PIPE3 */ 224 #define NRDY2 0x0004 /* b2: PIPE2 */ 225 #define NRDY1 0x0002 /* b1: PIPE1 */ 226 #define NRDY0 0x0001 /* b1: PIPE0 */ 227 228 /* BEMP Interrupt Enable/Status Register */ 229 #define BEMP9 0x0200 /* b9: PIPE9 */ 230 #define BEMP8 0x0100 /* b8: PIPE8 */ 231 #define BEMP7 0x0080 /* b7: PIPE7 */ 232 #define BEMP6 0x0040 /* b6: PIPE6 */ 233 #define BEMP5 0x0020 /* b5: PIPE5 */ 234 #define BEMP4 0x0010 /* b4: PIPE4 */ 235 #define BEMP3 0x0008 /* b3: PIPE3 */ 236 #define BEMP2 0x0004 /* b2: PIPE2 */ 237 #define BEMP1 0x0002 /* b1: PIPE1 */ 238 #define BEMP0 0x0001 /* b0: PIPE0 */ 239 240 /* SOF Pin Configuration Register */ 241 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */ 242 #define BRDYM 0x0040 /* b6: BRDY clear timing */ 243 #define INTL 0x0020 /* b5: Interrupt sense select */ 244 #define EDGESTS 0x0010 /* b4: */ 245 #define SOFMODE 0x000C /* b3-2: SOF pin select */ 246 #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */ 247 #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ 248 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */ 249 250 /* Interrupt Status Register 0 */ 251 #define VBINT 0x8000 /* b15: VBUS interrupt */ 252 #define RESM 0x4000 /* b14: Resume interrupt */ 253 #define SOFR 0x2000 /* b13: SOF frame update interrupt */ 254 #define DVST 0x1000 /* b12: Device state transition interrupt */ 255 #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ 256 #define BEMP 0x0400 /* b10: Buffer empty interrupt */ 257 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */ 258 #define BRDY 0x0100 /* b8: Buffer ready interrupt */ 259 #define VBSTS 0x0080 /* b7: VBUS input port */ 260 #define DVSQ 0x0070 /* b6-4: Device state */ 261 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */ 262 #define DS_SPD_ADDR 0x0060 /* Suspend Address */ 263 #define DS_SPD_DFLT 0x0050 /* Suspend Default */ 264 #define DS_SPD_POWR 0x0040 /* Suspend Powered */ 265 #define DS_SUSP 0x0040 /* Suspend */ 266 #define DS_CNFG 0x0030 /* Configured */ 267 #define DS_ADDS 0x0020 /* Address */ 268 #define DS_DFLT 0x0010 /* Default */ 269 #define DS_POWR 0x0000 /* Powered */ 270 #define DVSQS 0x0030 /* b5-4: Device state */ 271 #define VALID 0x0008 /* b3: Setup packet detected flag */ 272 #define CTSQ 0x0007 /* b2-0: Control transfer stage */ 273 #define CS_SQER 0x0006 /* Sequence error */ 274 #define CS_WRND 0x0005 /* Control write nodata status stage */ 275 #define CS_WRSS 0x0004 /* Control write status stage */ 276 #define CS_WRDS 0x0003 /* Control write data stage */ 277 #define CS_RDSS 0x0002 /* Control read status stage */ 278 #define CS_RDDS 0x0001 /* Control read data stage */ 279 #define CS_IDST 0x0000 /* Idle or setup stage */ 280 281 /* Interrupt Status Register 1 */ 282 #define OVRCR 0x8000 /* b15: Over-current interrupt */ 283 #define BCHG 0x4000 /* b14: USB bus chenge interrupt */ 284 #define DTCH 0x1000 /* b12: Detach sense interrupt */ 285 #define ATTCH 0x0800 /* b11: Attach sense interrupt */ 286 #define EOFERR 0x0040 /* b6: EOF-error interrupt */ 287 #define SIGN 0x0020 /* b5: Setup ignore interrupt */ 288 #define SACK 0x0010 /* b4: Setup acknowledge interrupt */ 289 290 /* Frame Number Register */ 291 #define OVRN 0x8000 /* b15: Overrun error */ 292 #define CRCE 0x4000 /* b14: Received data error */ 293 #define FRNM 0x07FF /* b10-0: Frame number */ 294 295 /* Micro Frame Number Register */ 296 #define UFRNM 0x0007 /* b2-0: Micro frame number */ 297 298 /* Default Control Pipe Maxpacket Size Register */ 299 /* Pipe Maxpacket Size Register */ 300 #define DEVSEL 0xF000 /* b15-14: Device address select */ 301 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ 302 303 /* Default Control Pipe Control Register */ 304 #define BSTS 0x8000 /* b15: Buffer status */ 305 #define SUREQ 0x4000 /* b14: Send USB request */ 306 #define CSCLR 0x2000 /* b13: complete-split status clear */ 307 #define CSSTS 0x1000 /* b12: complete-split status */ 308 #define SUREQCLR 0x0800 /* b11: stop setup request */ 309 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 310 #define SQSET 0x0080 /* b7: Sequence toggle bit set */ 311 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 312 #define PBUSY 0x0020 /* b5: pipe busy */ 313 #define PINGE 0x0010 /* b4: ping enable */ 314 #define CCPL 0x0004 /* b2: Enable control transfer complete */ 315 #define PID 0x0003 /* b1-0: Response PID */ 316 #define PID_STALL11 0x0003 /* STALL */ 317 #define PID_STALL 0x0002 /* STALL */ 318 #define PID_BUF 0x0001 /* BUF */ 319 #define PID_NAK 0x0000 /* NAK */ 320 321 /* Pipe Window Select Register */ 322 #define PIPENM 0x0007 /* b2-0: Pipe select */ 323 324 /* Pipe Configuration Register */ 325 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */ 326 #define R8A66597_ISO 0xC000 /* Isochronous */ 327 #define R8A66597_INT 0x8000 /* Interrupt */ 328 #define R8A66597_BULK 0x4000 /* Bulk */ 329 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */ 330 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */ 331 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */ 332 #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */ 333 #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */ 334 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */ 335 336 /* Pipe Buffer Configuration Register */ 337 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ 338 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */ 339 #define PIPE0BUF 256 340 #define PIPExBUF 64 341 342 /* Pipe Maxpacket Size Register */ 343 #define MXPS 0x07FF /* b10-0: Maxpacket size */ 344 345 /* Pipe Cycle Configuration Register */ 346 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ 347 #define IITV 0x0007 /* b2-0: Isochronous interval */ 348 349 /* Pipex Control Register */ 350 #define BSTS 0x8000 /* b15: Buffer status */ 351 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ 352 #define CSCLR 0x2000 /* b13: complete-split status clear */ 353 #define CSSTS 0x1000 /* b12: complete-split status */ 354 #define ATREPM 0x0400 /* b10: Auto repeat mode */ 355 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ 356 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 357 #define SQSET 0x0080 /* b7: Sequence toggle bit set */ 358 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 359 #define PBUSY 0x0020 /* b5: pipe busy */ 360 #define PID 0x0003 /* b1-0: Response PID */ 361 362 /* PIPExTRE */ 363 #define TRENB 0x0200 /* b9: Transaction counter enable */ 364 #define TRCLR 0x0100 /* b8: Transaction counter clear */ 365 366 /* PIPExTRN */ 367 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */ 368 369 /* DEVADDx */ 370 #define UPPHUB 0x7800 371 #define HUBPORT 0x0700 372 #define USBSPD 0x00C0 373 #define RTPORT 0x0001 374 375 /* Suspend Mode Register */ 376 #define SUSPM 0x4000 /* b14: Suspend */ 377 378 #define R8A66597_MAX_NUM_PIPE 10 379 #define R8A66597_BUF_BSIZE 8 380 #define R8A66597_MAX_DEVICE 10 381 #define R8A66597_MAX_ROOT_HUB 2 382 #define R8A66597_MAX_SAMPLING 5 383 #define R8A66597_RH_POLL_TIME 10 384 385 #define BULK_IN_PIPENUM 3 386 #define BULK_IN_BUFNUM 8 387 388 #define BULK_OUT_PIPENUM 4 389 #define BULK_OUT_BUFNUM 40 390 391 #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5)) 392 #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9)) 393 #define make_devsel(addr) (addr << 12) 394 395 struct r8a66597 { 396 unsigned long reg; 397 unsigned short pipe_config; /* bit field */ 398 unsigned short port_status; 399 unsigned short port_change; 400 u16 speed; /* HSMODE or FSMODE or LSMODE */ 401 unsigned char rh_devnum; 402 }; 403 404 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) 405 { 406 return readw(r8a66597->reg + offset); 407 } 408 409 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, 410 unsigned long offset, void *buf, 411 int len) 412 { 413 int i; 414 unsigned long fifoaddr = r8a66597->reg + offset; 415 unsigned long count; 416 unsigned long *p = buf; 417 418 count = len / 4; 419 for (i = 0; i < count; i++) 420 p[i] = readl(r8a66597->reg + offset); 421 422 if (len & 0x00000003) { 423 unsigned long tmp = readl(fifoaddr); 424 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03); 425 } 426 } 427 428 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 429 unsigned long offset) 430 { 431 writew(val, r8a66597->reg + offset); 432 } 433 434 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, 435 unsigned long offset, void *buf, 436 int len) 437 { 438 int i; 439 unsigned long fifoaddr = r8a66597->reg + offset; 440 unsigned long count; 441 unsigned char *pb; 442 unsigned long *p = buf; 443 444 count = len / 4; 445 for (i = 0; i < count; i++) 446 writel(p[i], fifoaddr); 447 448 if (len & 0x00000003) { 449 pb = (unsigned char *)buf + count * 4; 450 for (i = 0; i < (len & 0x00000003); i++) { 451 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND) 452 writeb(pb[i], fifoaddr + i); 453 else 454 writeb(pb[i], fifoaddr + 3 - i); 455 } 456 } 457 } 458 459 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, 460 u16 val, u16 pat, unsigned long offset) 461 { 462 u16 tmp; 463 tmp = r8a66597_read(r8a66597, offset); 464 tmp = tmp & (~pat); 465 tmp = tmp | val; 466 r8a66597_write(r8a66597, tmp, offset); 467 } 468 469 #define r8a66597_bclr(r8a66597, val, offset) \ 470 r8a66597_mdfy(r8a66597, 0, val, offset) 471 #define r8a66597_bset(r8a66597, val, offset) \ 472 r8a66597_mdfy(r8a66597, val, 0, offset) 473 474 static inline unsigned long get_syscfg_reg(int port) 475 { 476 return port == 0 ? SYSCFG0 : SYSCFG1; 477 } 478 479 static inline unsigned long get_syssts_reg(int port) 480 { 481 return port == 0 ? SYSSTS0 : SYSSTS1; 482 } 483 484 static inline unsigned long get_dvstctr_reg(int port) 485 { 486 return port == 0 ? DVSTCTR0 : DVSTCTR1; 487 } 488 489 static inline unsigned long get_dmacfg_reg(int port) 490 { 491 return port == 0 ? DMA0CFG : DMA1CFG; 492 } 493 494 static inline unsigned long get_intenb_reg(int port) 495 { 496 return port == 0 ? INTENB1 : INTENB2; 497 } 498 499 static inline unsigned long get_intsts_reg(int port) 500 { 501 return port == 0 ? INTSTS1 : INTSTS2; 502 } 503 504 static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port) 505 { 506 unsigned long dvstctr_reg = get_dvstctr_reg(port); 507 508 return r8a66597_read(r8a66597, dvstctr_reg) & RHST; 509 } 510 511 static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port, 512 int power) 513 { 514 unsigned long dvstctr_reg = get_dvstctr_reg(port); 515 516 if (power) 517 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg); 518 else 519 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg); 520 } 521 522 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2) 523 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4) 524 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4) 525 #define get_devadd_addr(address) (DEVADD0 + address * 2) 526 527 528 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */ 529 530 /* destination of request */ 531 #define RH_INTERFACE 0x01 532 #define RH_ENDPOINT 0x02 533 #define RH_OTHER 0x03 534 535 #define RH_CLASS 0x20 536 #define RH_VENDOR 0x40 537 538 /* Requests: bRequest << 8 | bmRequestType */ 539 #define RH_GET_STATUS 0x0080 540 #define RH_CLEAR_FEATURE 0x0100 541 #define RH_SET_FEATURE 0x0300 542 #define RH_SET_ADDRESS 0x0500 543 #define RH_GET_DESCRIPTOR 0x0680 544 #define RH_SET_DESCRIPTOR 0x0700 545 #define RH_GET_CONFIGURATION 0x0880 546 #define RH_SET_CONFIGURATION 0x0900 547 #define RH_GET_STATE 0x0280 548 #define RH_GET_INTERFACE 0x0A80 549 #define RH_SET_INTERFACE 0x0B00 550 #define RH_SYNC_FRAME 0x0C80 551 /* Our Vendor Specific Request */ 552 #define RH_SET_EP 0x2000 553 554 /* Hub port features */ 555 #define RH_PORT_CONNECTION 0x00 556 #define RH_PORT_ENABLE 0x01 557 #define RH_PORT_SUSPEND 0x02 558 #define RH_PORT_OVER_CURRENT 0x03 559 #define RH_PORT_RESET 0x04 560 #define RH_PORT_POWER 0x08 561 #define RH_PORT_LOW_SPEED 0x09 562 563 #define RH_C_PORT_CONNECTION 0x10 564 #define RH_C_PORT_ENABLE 0x11 565 #define RH_C_PORT_SUSPEND 0x12 566 #define RH_C_PORT_OVER_CURRENT 0x13 567 #define RH_C_PORT_RESET 0x14 568 569 /* Hub features */ 570 #define RH_C_HUB_LOCAL_POWER 0x00 571 #define RH_C_HUB_OVER_CURRENT 0x01 572 573 #define RH_DEVICE_REMOTE_WAKEUP 0x00 574 #define RH_ENDPOINT_STALL 0x01 575 576 #define RH_ACK 0x01 577 #define RH_REQ_ERR -1 578 #define RH_NACK 0x00 579 580 /* OHCI ROOT HUB REGISTER MASKS */ 581 582 /* roothub.portstatus [i] bits */ 583 #define RH_PS_CCS 0x00000001 /* current connect status */ 584 #define RH_PS_PES 0x00000002 /* port enable status*/ 585 #define RH_PS_PSS 0x00000004 /* port suspend status */ 586 #define RH_PS_POCI 0x00000008 /* port over current indicator */ 587 #define RH_PS_PRS 0x00000010 /* port reset status */ 588 #define RH_PS_PPS 0x00000100 /* port power status */ 589 #define RH_PS_LSDA 0x00000200 /* low speed device attached */ 590 #define RH_PS_CSC 0x00010000 /* connect status change */ 591 #define RH_PS_PESC 0x00020000 /* port enable status change */ 592 #define RH_PS_PSSC 0x00040000 /* port suspend status change */ 593 #define RH_PS_OCIC 0x00080000 /* over current indicator change */ 594 #define RH_PS_PRSC 0x00100000 /* port reset status change */ 595 596 /* roothub.status bits */ 597 #define RH_HS_LPS 0x00000001 /* local power status */ 598 #define RH_HS_OCI 0x00000002 /* over current indicator */ 599 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ 600 #define RH_HS_LPSC 0x00010000 /* local power status change */ 601 #define RH_HS_OCIC 0x00020000 /* over current indicator change */ 602 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ 603 604 /* roothub.b masks */ 605 #define RH_B_DR 0x0000ffff /* device removable flags */ 606 #define RH_B_PPCM 0xffff0000 /* port power control mask */ 607 608 /* roothub.a masks */ 609 #define RH_A_NDP (0xff << 0) /* number of downstream ports */ 610 #define RH_A_PSM (1 << 8) /* power switching mode */ 611 #define RH_A_NPS (1 << 9) /* no power switching */ 612 #define RH_A_DT (1 << 10) /* device type (mbz) */ 613 #define RH_A_OCPM (1 << 11) /* over current protection mode */ 614 #define RH_A_NOCP (1 << 12) /* no over current protection */ 615 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ 616 617 #endif /* __R8A66597_H__ */ 618