1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2013 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/errno.h> 11 #include <asm/io.h> 12 #include <asm-generic/gpio.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch-tegra/usb.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <usb.h> 17 #include <usb/ulpi.h> 18 #include <libfdt.h> 19 #include <fdtdec.h> 20 21 #include "ehci.h" 22 23 #define USB1_ADDR_MASK 0xFFFF0000 24 25 #define HOSTPC1_DEVLC 0x84 26 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 27 28 #ifdef CONFIG_USB_ULPI 29 #ifndef CONFIG_USB_ULPI_VIEWPORT 30 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 31 define CONFIG_USB_ULPI_VIEWPORT" 32 #endif 33 #endif 34 35 enum { 36 USB_PORTS_MAX = 3, /* Maximum ports we allow */ 37 }; 38 39 /* Parameters we need for USB */ 40 enum { 41 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 42 PARAM_DIVM, /* PLL INPUT DIVIDER */ 43 PARAM_DIVP, /* POST DIVIDER (2^N) */ 44 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 45 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 46 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 47 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 48 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 49 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 50 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 51 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 52 53 PARAM_COUNT 54 }; 55 56 /* Possible port types (dual role mode) */ 57 enum dr_mode { 58 DR_MODE_NONE = 0, 59 DR_MODE_HOST, /* supports host operation */ 60 DR_MODE_DEVICE, /* supports device operation */ 61 DR_MODE_OTG, /* supports both */ 62 }; 63 64 /* Information about a USB port */ 65 struct fdt_usb { 66 struct usb_ctlr *reg; /* address of registers in physical memory */ 67 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 68 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 69 unsigned enabled:1; /* 1 to enable, 0 to disable */ 70 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 71 unsigned initialized:1; /* has this port already been initialized? */ 72 enum dr_mode dr_mode; /* dual role mode */ 73 enum periph_id periph_id;/* peripheral id */ 74 struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ 75 struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */ 76 }; 77 78 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ 79 static unsigned port_count; /* Number of available ports */ 80 /* Port that needs to clear CSC after Port Reset */ 81 static u32 port_addr_clear_csc; 82 83 /* 84 * This table has USB timing parameters for each Oscillator frequency we 85 * support. There are four sets of values: 86 * 87 * 1. PLLU configuration information (reference clock is osc/clk_m and 88 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 89 * 90 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 91 * ---------------------------------------------------------------------- 92 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 93 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 94 * Filter frequency (MHz) 1 4.8 6 2 95 * CPCON 1100b 0011b 1100b 1100b 96 * LFCON0 0 0 0 0 97 * 98 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 99 * 100 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 101 * --------------------------------------------------------------------------- 102 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 103 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 104 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 105 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 106 * 107 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 108 * SessEnd. Each of these signals have their own debouncer and for each of 109 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 110 * BIAS_DEBOUNCE_B). 111 * 112 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 113 * 0xffff -> No debouncing at all 114 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 115 * 116 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 117 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 118 * 119 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 120 * values, so we can keep those to default. 121 * 122 * 4. The 20 microsecond delay after bias cell operation. 123 */ 124 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 125 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 126 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 127 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 128 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 129 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 130 }; 131 132 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 133 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 134 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 135 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 136 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 137 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 138 }; 139 140 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 141 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 142 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 143 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 144 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 145 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 146 }; 147 148 /* UTMIP Idle Wait Delay */ 149 static const u8 utmip_idle_wait_delay = 17; 150 151 /* UTMIP Elastic limit */ 152 static const u8 utmip_elastic_limit = 16; 153 154 /* UTMIP High Speed Sync Start Delay */ 155 static const u8 utmip_hs_sync_start_delay = 9; 156 157 struct fdt_usb_controller { 158 int compat; 159 /* flag to determine whether controller supports hostpc register */ 160 u32 has_hostpc:1; 161 const unsigned *pll_parameter; 162 }; 163 164 static struct fdt_usb_controller fdt_usb_controllers[] = { 165 { 166 .compat = COMPAT_NVIDIA_TEGRA20_USB, 167 .has_hostpc = 0, 168 .pll_parameter = (const unsigned *)T20_usb_pll, 169 }, 170 { 171 .compat = COMPAT_NVIDIA_TEGRA30_USB, 172 .has_hostpc = 1, 173 .pll_parameter = (const unsigned *)T30_usb_pll, 174 }, 175 { 176 .compat = COMPAT_NVIDIA_TEGRA114_USB, 177 .has_hostpc = 1, 178 .pll_parameter = (const unsigned *)T114_usb_pll, 179 }, 180 }; 181 182 static struct fdt_usb_controller *controller; 183 184 /* 185 * A known hardware issue where Connect Status Change bit of PORTSC register 186 * of USB1 controller will be set after Port Reset. 187 * We have to clear it in order for later device enumeration to proceed. 188 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup 189 * in "ehci-hcd.c". 190 */ 191 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 192 { 193 mdelay(50); 194 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 195 if (controller->has_hostpc) 196 *reg |= EHCI_PS_PE; 197 198 if (((u32)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc) 199 return; 200 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 201 if (ehci_readl(status_reg) & EHCI_PS_CSC) 202 *reg |= EHCI_PS_CSC; 203 } 204 205 /* 206 * This ehci_set_usbmode overrides the weak function ehci_set_usbmode 207 * in "ehci-hcd.c". 208 */ 209 void ehci_set_usbmode(int index) 210 { 211 struct fdt_usb *config; 212 struct usb_ctlr *usbctlr; 213 uint32_t tmp; 214 215 config = &port[index]; 216 usbctlr = config->reg; 217 218 tmp = ehci_readl(&usbctlr->usb_mode); 219 tmp |= USBMODE_CM_HC; 220 ehci_writel(&usbctlr->usb_mode, tmp); 221 } 222 223 /* 224 * This ehci_get_port_speed overrides the weak function ehci_get_port_speed 225 * in "ehci-hcd.c". 226 */ 227 int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) 228 { 229 uint32_t tmp; 230 uint32_t *reg_ptr; 231 232 if (controller->has_hostpc) { 233 reg_ptr = (uint32_t *)((u8 *)&hcor->or_usbcmd + HOSTPC1_DEVLC); 234 tmp = ehci_readl(reg_ptr); 235 return HOSTPC1_PSPD(tmp); 236 } else 237 return PORTSC_PSPD(reg); 238 } 239 240 /* Put the port into host mode */ 241 static void set_host_mode(struct fdt_usb *config) 242 { 243 /* 244 * If we are an OTG port, check if remote host is driving VBus and 245 * bail out in this case. 246 */ 247 if (config->dr_mode == DR_MODE_OTG && 248 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) 249 return; 250 251 /* 252 * If not driving, we set the GPIO to enable VBUS. We assume 253 * that the pinmux is set up correctly for this. 254 */ 255 if (fdt_gpio_isvalid(&config->vbus_gpio)) { 256 fdtdec_setup_gpio(&config->vbus_gpio); 257 gpio_direction_output(config->vbus_gpio.gpio, 258 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? 259 0 : 1); 260 debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, 261 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? 262 "low" : "high"); 263 } 264 } 265 266 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) 267 { 268 /* Reset the USB controller with 2us delay */ 269 reset_periph(config->periph_id, 2); 270 271 /* 272 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 273 * base address 274 */ 275 if (config->has_legacy_mode) 276 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 277 278 /* Put UTMIP1/3 in reset */ 279 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 280 281 /* Enable the UTMIP PHY */ 282 if (config->utmi) 283 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 284 } 285 286 static const unsigned *get_pll_timing(void) 287 { 288 const unsigned *timing; 289 290 timing = controller->pll_parameter + 291 clock_get_osc_freq() * PARAM_COUNT; 292 293 return timing; 294 } 295 296 /* set up the UTMI USB controller with the parameters provided */ 297 static int init_utmi_usb_controller(struct fdt_usb *config) 298 { 299 u32 val; 300 int loop_count; 301 const unsigned *timing; 302 struct usb_ctlr *usbctlr = config->reg; 303 struct clk_rst_ctlr *clkrst; 304 struct usb_ctlr *usb1ctlr; 305 306 clock_enable(config->periph_id); 307 308 /* Reset the usb controller */ 309 usbf_reset_controller(config, usbctlr); 310 311 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 312 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 313 314 /* Follow the crystal clock disable by >100ns delay */ 315 udelay(1); 316 317 /* 318 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 319 * mux must be switched to actually use a_sess_vld threshold. 320 */ 321 if (config->dr_mode == DR_MODE_OTG && 322 fdt_gpio_isvalid(&config->vbus_gpio)) 323 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 324 VBUS_SENSE_CTL_MASK, 325 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 326 327 /* 328 * PLL Delay CONFIGURATION settings. The following parameters control 329 * the bring up of the plls. 330 */ 331 timing = get_pll_timing(); 332 333 if (!controller->has_hostpc) { 334 val = readl(&usbctlr->utmip_misc_cfg1); 335 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 336 timing[PARAM_STABLE_COUNT] << 337 UTMIP_PLLU_STABLE_COUNT_SHIFT); 338 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 339 timing[PARAM_ACTIVE_DELAY_COUNT] << 340 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 341 writel(val, &usbctlr->utmip_misc_cfg1); 342 343 /* Set PLL enable delay count and crystal frequency count */ 344 val = readl(&usbctlr->utmip_pll_cfg1); 345 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 346 timing[PARAM_ENABLE_DELAY_COUNT] << 347 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 348 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 349 timing[PARAM_XTAL_FREQ_COUNT] << 350 UTMIP_XTAL_FREQ_COUNT_SHIFT); 351 writel(val, &usbctlr->utmip_pll_cfg1); 352 } else { 353 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 354 355 val = readl(&clkrst->crc_utmip_pll_cfg2); 356 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 357 timing[PARAM_STABLE_COUNT] << 358 UTMIP_PLLU_STABLE_COUNT_SHIFT); 359 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 360 timing[PARAM_ACTIVE_DELAY_COUNT] << 361 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 362 writel(val, &clkrst->crc_utmip_pll_cfg2); 363 364 /* Set PLL enable delay count and crystal frequency count */ 365 val = readl(&clkrst->crc_utmip_pll_cfg1); 366 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 367 timing[PARAM_ENABLE_DELAY_COUNT] << 368 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 369 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 370 timing[PARAM_XTAL_FREQ_COUNT] << 371 UTMIP_XTAL_FREQ_COUNT_SHIFT); 372 writel(val, &clkrst->crc_utmip_pll_cfg1); 373 374 /* Disable Power Down state for PLL */ 375 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 376 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 377 PLL_ACTIVE_POWERDOWN); 378 379 /* Recommended PHY settings for EYE diagram */ 380 val = readl(&usbctlr->utmip_xcvr_cfg0); 381 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 382 0x4 << UTMIP_XCVR_SETUP_SHIFT); 383 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 384 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 385 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 386 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 387 writel(val, &usbctlr->utmip_xcvr_cfg0); 388 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 389 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 390 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 391 392 /* Some registers can be controlled from USB1 only. */ 393 if (config->periph_id != PERIPH_ID_USBD) { 394 clock_enable(PERIPH_ID_USBD); 395 /* Disable Reset if in Reset state */ 396 reset_set_enable(PERIPH_ID_USBD, 0); 397 } 398 usb1ctlr = (struct usb_ctlr *) 399 ((u32)config->reg & USB1_ADDR_MASK); 400 val = readl(&usb1ctlr->utmip_bias_cfg0); 401 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 402 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 403 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 404 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 405 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 406 writel(val, &usb1ctlr->utmip_bias_cfg0); 407 408 /* Miscellaneous setting mentioned in Programming Guide */ 409 clrbits_le32(&usbctlr->utmip_misc_cfg0, 410 UTMIP_SUSPEND_EXIT_ON_EDGE); 411 } 412 413 /* Setting the tracking length time */ 414 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 415 UTMIP_BIAS_PDTRK_COUNT_MASK, 416 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 417 418 /* Program debounce time for VBUS to become valid */ 419 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 420 UTMIP_DEBOUNCE_CFG0_MASK, 421 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 422 423 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 424 425 /* Disable battery charge enabling bit */ 426 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 427 428 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 429 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 430 431 /* 432 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 433 * Setting these fields, together with default values of the 434 * other fields, results in programming the registers below as 435 * follows: 436 * UTMIP_HSRX_CFG0 = 0x9168c000 437 * UTMIP_HSRX_CFG1 = 0x13 438 */ 439 440 /* Set PLL enable delay count and Crystal frequency count */ 441 val = readl(&usbctlr->utmip_hsrx_cfg0); 442 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 443 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 444 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 445 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 446 writel(val, &usbctlr->utmip_hsrx_cfg0); 447 448 /* Configure the UTMIP_HS_SYNC_START_DLY */ 449 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 450 UTMIP_HS_SYNC_START_DLY_MASK, 451 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 452 453 /* Preceed the crystal clock disable by >100ns delay. */ 454 udelay(1); 455 456 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 457 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 458 459 if (controller->has_hostpc) { 460 if (config->periph_id == PERIPH_ID_USBD) 461 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 462 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 463 if (config->periph_id == PERIPH_ID_USB2) 464 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 465 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 466 if (config->periph_id == PERIPH_ID_USB3) 467 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 468 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 469 } 470 /* Finished the per-controller init. */ 471 472 /* De-assert UTMIP_RESET to bring out of reset. */ 473 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 474 475 /* Wait for the phy clock to become valid in 100 ms */ 476 for (loop_count = 100000; loop_count != 0; loop_count--) { 477 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 478 break; 479 udelay(1); 480 } 481 if (!loop_count) 482 return -1; 483 484 /* Disable ICUSB FS/LS transceiver */ 485 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 486 487 /* Select UTMI parallel interface */ 488 #if defined(CONFIG_TEGRA20) 489 if (config->periph_id == PERIPH_ID_USBD) { 490 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 491 PTS_UTMI << PTS1_SHIFT); 492 clrbits_le32(&usbctlr->port_sc1, STS1); 493 } else { 494 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 495 PTS_UTMI << PTS_SHIFT); 496 clrbits_le32(&usbctlr->port_sc1, STS); 497 } 498 #else 499 /* Set to Host mode after Controller Reset was done */ 500 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 501 USBMODE_CM_HC); 502 /* Select PHY interface after setting host mode */ 503 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 504 PTS_UTMI << PTS_SHIFT); 505 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 506 #endif 507 508 /* Deassert power down state */ 509 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 510 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 511 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 512 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 513 514 if (controller->has_hostpc) { 515 /* 516 * BIAS Pad Power Down is common among all 3 USB 517 * controllers and can be controlled from USB1 only. 518 */ 519 usb1ctlr = (struct usb_ctlr *) 520 ((u32)config->reg & USB1_ADDR_MASK); 521 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 522 udelay(25); 523 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 524 UTMIP_FORCE_PDTRK_POWERDOWN); 525 } 526 return 0; 527 } 528 529 #ifdef CONFIG_USB_ULPI 530 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 531 #ifndef CONFIG_ULPI_REF_CLK 532 #define CONFIG_ULPI_REF_CLK 24000000 533 #endif 534 535 /* set up the ULPI USB controller with the parameters provided */ 536 static int init_ulpi_usb_controller(struct fdt_usb *config) 537 { 538 u32 val; 539 int loop_count; 540 struct ulpi_viewport ulpi_vp; 541 struct usb_ctlr *usbctlr = config->reg; 542 543 /* set up ULPI reference clock on pllp_out4 */ 544 clock_enable(PERIPH_ID_DEV2_OUT); 545 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 546 547 /* reset ULPI phy */ 548 if (fdt_gpio_isvalid(&config->phy_reset_gpio)) { 549 fdtdec_setup_gpio(&config->phy_reset_gpio); 550 gpio_direction_output(config->phy_reset_gpio.gpio, 0); 551 mdelay(5); 552 gpio_set_value(config->phy_reset_gpio.gpio, 1); 553 } 554 555 /* Reset the usb controller */ 556 clock_enable(config->periph_id); 557 usbf_reset_controller(config, usbctlr); 558 559 /* enable pinmux bypass */ 560 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 561 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 562 563 /* Select ULPI parallel interface */ 564 #if defined(CONFIG_TEGRA20) 565 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 566 PTS_ULPI << PTS_SHIFT); 567 #else 568 /* Set to Host mode after Controller Reset was done */ 569 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 570 USBMODE_CM_HC); 571 /* Select PHY interface after setting host mode */ 572 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 573 PTS_ULPI << PTS_SHIFT); 574 #endif 575 576 /* enable ULPI transceiver */ 577 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 578 579 /* configure ULPI transceiver timings */ 580 val = 0; 581 writel(val, &usbctlr->ulpi_timing_ctrl_1); 582 583 val |= ULPI_DATA_TRIMMER_SEL(4); 584 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 585 val |= ULPI_DIR_TRIMMER_SEL(4); 586 writel(val, &usbctlr->ulpi_timing_ctrl_1); 587 udelay(10); 588 589 val |= ULPI_DATA_TRIMMER_LOAD; 590 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 591 val |= ULPI_DIR_TRIMMER_LOAD; 592 writel(val, &usbctlr->ulpi_timing_ctrl_1); 593 594 /* set up phy for host operation with external vbus supply */ 595 ulpi_vp.port_num = 0; 596 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 597 598 if (ulpi_init(&ulpi_vp)) { 599 printf("Tegra ULPI viewport init failed\n"); 600 return -1; 601 } 602 603 ulpi_set_vbus(&ulpi_vp, 1, 1); 604 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 605 606 /* enable wakeup events */ 607 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 608 609 /* Enable and wait for the phy clock to become valid in 100 ms */ 610 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 611 for (loop_count = 100000; loop_count != 0; loop_count--) { 612 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 613 break; 614 udelay(1); 615 } 616 if (!loop_count) 617 return -1; 618 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 619 620 return 0; 621 } 622 #else 623 static int init_ulpi_usb_controller(struct fdt_usb *config) 624 { 625 printf("No code to set up ULPI controller, please enable" 626 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 627 return -1; 628 } 629 #endif 630 631 static void config_clock(const u32 timing[]) 632 { 633 clock_start_pll(CLOCK_ID_USB, 634 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 635 timing[PARAM_CPCON], timing[PARAM_LFCON]); 636 } 637 638 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 639 { 640 const char *phy, *mode; 641 642 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 643 mode = fdt_getprop(blob, node, "dr_mode", NULL); 644 if (mode) { 645 if (0 == strcmp(mode, "host")) 646 config->dr_mode = DR_MODE_HOST; 647 else if (0 == strcmp(mode, "peripheral")) 648 config->dr_mode = DR_MODE_DEVICE; 649 else if (0 == strcmp(mode, "otg")) 650 config->dr_mode = DR_MODE_OTG; 651 else { 652 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 653 mode); 654 return -FDT_ERR_NOTFOUND; 655 } 656 } else { 657 config->dr_mode = DR_MODE_HOST; 658 } 659 660 phy = fdt_getprop(blob, node, "phy_type", NULL); 661 config->utmi = phy && 0 == strcmp("utmi", phy); 662 config->ulpi = phy && 0 == strcmp("ulpi", phy); 663 config->enabled = fdtdec_get_is_enabled(blob, node); 664 config->has_legacy_mode = fdtdec_get_bool(blob, node, 665 "nvidia,has-legacy-mode"); 666 if (config->has_legacy_mode) 667 port_addr_clear_csc = (u32) config->reg; 668 config->periph_id = clock_decode_periph_id(blob, node); 669 if (config->periph_id == PERIPH_ID_NONE) { 670 debug("%s: Missing/invalid peripheral ID\n", __func__); 671 return -FDT_ERR_NOTFOUND; 672 } 673 fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); 674 fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio", 675 &config->phy_reset_gpio); 676 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 677 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 678 config->enabled, config->has_legacy_mode, config->utmi, 679 config->ulpi, config->periph_id, config->vbus_gpio.gpio, 680 config->phy_reset_gpio.gpio, config->dr_mode); 681 682 return 0; 683 } 684 685 /* 686 * process_usb_nodes() - Process a list of USB nodes, adding them to our list 687 * of USB ports. 688 * @blob: fdt blob 689 * @node_list: list of nodes to process (any <=0 are ignored) 690 * @count: number of nodes to process 691 * 692 * Return: 0 - ok, -1 - error 693 */ 694 static int process_usb_nodes(const void *blob, int node_list[], int count) 695 { 696 struct fdt_usb config; 697 int node, i; 698 int clk_done = 0; 699 700 port_count = 0; 701 for (i = 0; i < count; i++) { 702 if (port_count == USB_PORTS_MAX) { 703 printf("tegrausb: Cannot register more than %d ports\n", 704 USB_PORTS_MAX); 705 return -1; 706 } 707 708 debug("USB %d: ", i); 709 node = node_list[i]; 710 if (!node) 711 continue; 712 if (fdt_decode_usb(blob, node, &config)) { 713 debug("Cannot decode USB node %s\n", 714 fdt_get_name(blob, node, NULL)); 715 return -1; 716 } 717 if (!clk_done) { 718 config_clock(get_pll_timing()); 719 clk_done = 1; 720 } 721 config.initialized = 0; 722 723 /* add new USB port to the list of available ports */ 724 port[port_count++] = config; 725 } 726 727 return 0; 728 } 729 730 int usb_process_devicetree(const void *blob) 731 { 732 int node_list[USB_PORTS_MAX]; 733 int count, err = 0; 734 int i; 735 736 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { 737 controller = &fdt_usb_controllers[i]; 738 739 count = fdtdec_find_aliases_for_id(blob, "usb", 740 controller->compat, node_list, USB_PORTS_MAX); 741 if (count) { 742 err = process_usb_nodes(blob, node_list, count); 743 if (err) 744 printf("%s: Error processing USB node!\n", 745 __func__); 746 return err; 747 } 748 } 749 if (i == ARRAY_SIZE(fdt_usb_controllers)) 750 controller = NULL; 751 752 return err; 753 } 754 755 /** 756 * Start up the given port number (ports are numbered from 0 on each board). 757 * This returns values for the appropriate hccr and hcor addresses to use for 758 * USB EHCI operations. 759 * 760 * @param index port number to start 761 * @param hccr returns start address of EHCI HCCR registers 762 * @param hcor returns start address of EHCI HCOR registers 763 * @return 0 if ok, -1 on error (generally invalid port number) 764 */ 765 int ehci_hcd_init(int index, enum usb_init_type init, 766 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 767 { 768 struct fdt_usb *config; 769 struct usb_ctlr *usbctlr; 770 771 if (index >= port_count) 772 return -1; 773 774 config = &port[index]; 775 776 /* skip init, if the port is already initialized */ 777 if (config->initialized) 778 goto success; 779 780 if (config->utmi && init_utmi_usb_controller(config)) { 781 printf("tegrausb: Cannot init port %d\n", index); 782 return -1; 783 } 784 785 if (config->ulpi && init_ulpi_usb_controller(config)) { 786 printf("tegrausb: Cannot init port %d\n", index); 787 return -1; 788 } 789 790 set_host_mode(config); 791 792 config->initialized = 1; 793 794 success: 795 usbctlr = config->reg; 796 *hccr = (struct ehci_hccr *)&usbctlr->cap_length; 797 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; 798 799 return 0; 800 } 801 802 /* 803 * Bring down the specified USB controller 804 */ 805 int ehci_hcd_stop(int index) 806 { 807 struct usb_ctlr *usbctlr; 808 809 usbctlr = port[index].reg; 810 811 /* Stop controller */ 812 writel(0, &usbctlr->usb_cmd); 813 udelay(1000); 814 815 /* Initiate controller reset */ 816 writel(2, &usbctlr->usb_cmd); 817 udelay(1000); 818 819 port[index].initialized = 0; 820 821 return 0; 822 } 823