1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2013 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/errno.h> 11 #include <asm/io.h> 12 #include <asm-generic/gpio.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch-tegra/usb.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <usb.h> 17 #include <usb/ulpi.h> 18 #include <libfdt.h> 19 #include <fdtdec.h> 20 21 #include "ehci.h" 22 23 #define USB1_ADDR_MASK 0xFFFF0000 24 25 #define HOSTPC1_DEVLC 0x84 26 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 27 28 #ifdef CONFIG_USB_ULPI 29 #ifndef CONFIG_USB_ULPI_VIEWPORT 30 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 31 define CONFIG_USB_ULPI_VIEWPORT" 32 #endif 33 #endif 34 35 enum { 36 USB_PORTS_MAX = 3, /* Maximum ports we allow */ 37 }; 38 39 /* Parameters we need for USB */ 40 enum { 41 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 42 PARAM_DIVM, /* PLL INPUT DIVIDER */ 43 PARAM_DIVP, /* POST DIVIDER (2^N) */ 44 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 45 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 46 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 47 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 48 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 49 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 50 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 51 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 52 53 PARAM_COUNT 54 }; 55 56 /* Possible port types (dual role mode) */ 57 enum dr_mode { 58 DR_MODE_NONE = 0, 59 DR_MODE_HOST, /* supports host operation */ 60 DR_MODE_DEVICE, /* supports device operation */ 61 DR_MODE_OTG, /* supports both */ 62 }; 63 64 enum usb_ctlr_type { 65 USB_CTLR_T20, 66 USB_CTLR_T30, 67 USB_CTLR_T114, 68 69 USB_CTRL_COUNT, 70 }; 71 72 /* Information about a USB port */ 73 struct fdt_usb { 74 struct usb_ctlr *reg; /* address of registers in physical memory */ 75 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 76 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 77 unsigned enabled:1; /* 1 to enable, 0 to disable */ 78 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 79 unsigned initialized:1; /* has this port already been initialized? */ 80 enum usb_ctlr_type type; 81 enum usb_init_type init_type; 82 enum dr_mode dr_mode; /* dual role mode */ 83 enum periph_id periph_id;/* peripheral id */ 84 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 85 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 86 }; 87 88 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ 89 static unsigned port_count; /* Number of available ports */ 90 91 /* 92 * This table has USB timing parameters for each Oscillator frequency we 93 * support. There are four sets of values: 94 * 95 * 1. PLLU configuration information (reference clock is osc/clk_m and 96 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 97 * 98 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 99 * ---------------------------------------------------------------------- 100 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 101 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 102 * Filter frequency (MHz) 1 4.8 6 2 103 * CPCON 1100b 0011b 1100b 1100b 104 * LFCON0 0 0 0 0 105 * 106 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 107 * 108 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 109 * --------------------------------------------------------------------------- 110 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 111 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 112 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 113 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 114 * 115 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 116 * SessEnd. Each of these signals have their own debouncer and for each of 117 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 118 * BIAS_DEBOUNCE_B). 119 * 120 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 121 * 0xffff -> No debouncing at all 122 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 123 * 124 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 125 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 126 * 127 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 128 * values, so we can keep those to default. 129 * 130 * 4. The 20 microsecond delay after bias cell operation. 131 */ 132 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 133 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 134 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 135 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 136 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 137 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 138 }; 139 140 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 141 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 142 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 143 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 144 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 145 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 146 }; 147 148 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 149 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 150 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 151 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 152 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 153 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 154 }; 155 156 /* UTMIP Idle Wait Delay */ 157 static const u8 utmip_idle_wait_delay = 17; 158 159 /* UTMIP Elastic limit */ 160 static const u8 utmip_elastic_limit = 16; 161 162 /* UTMIP High Speed Sync Start Delay */ 163 static const u8 utmip_hs_sync_start_delay = 9; 164 165 struct fdt_usb_controller { 166 int compat; 167 /* flag to determine whether controller supports hostpc register */ 168 u32 has_hostpc:1; 169 const unsigned *pll_parameter; 170 }; 171 172 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { 173 { 174 .compat = COMPAT_NVIDIA_TEGRA20_USB, 175 .has_hostpc = 0, 176 .pll_parameter = (const unsigned *)T20_usb_pll, 177 }, 178 { 179 .compat = COMPAT_NVIDIA_TEGRA30_USB, 180 .has_hostpc = 1, 181 .pll_parameter = (const unsigned *)T30_usb_pll, 182 }, 183 { 184 .compat = COMPAT_NVIDIA_TEGRA114_USB, 185 .has_hostpc = 1, 186 .pll_parameter = (const unsigned *)T114_usb_pll, 187 }, 188 }; 189 190 /* 191 * A known hardware issue where Connect Status Change bit of PORTSC register 192 * of USB1 controller will be set after Port Reset. 193 * We have to clear it in order for later device enumeration to proceed. 194 */ 195 static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl, 196 uint32_t *status_reg, uint32_t *reg) 197 { 198 struct fdt_usb *config = ctrl->priv; 199 struct fdt_usb_controller *controller; 200 201 controller = &fdt_usb_controllers[config->type]; 202 mdelay(50); 203 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 204 if (controller->has_hostpc) 205 *reg |= EHCI_PS_PE; 206 207 if (!config->has_legacy_mode) 208 return; 209 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 210 if (ehci_readl(status_reg) & EHCI_PS_CSC) 211 *reg |= EHCI_PS_CSC; 212 } 213 214 static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl) 215 { 216 struct fdt_usb *config = ctrl->priv; 217 struct usb_ctlr *usbctlr; 218 uint32_t tmp; 219 220 usbctlr = config->reg; 221 222 tmp = ehci_readl(&usbctlr->usb_mode); 223 tmp |= USBMODE_CM_HC; 224 ehci_writel(&usbctlr->usb_mode, tmp); 225 } 226 227 static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 228 { 229 struct fdt_usb *config = ctrl->priv; 230 struct fdt_usb_controller *controller; 231 uint32_t tmp; 232 uint32_t *reg_ptr; 233 234 controller = &fdt_usb_controllers[config->type]; 235 if (controller->has_hostpc) { 236 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 237 HOSTPC1_DEVLC); 238 tmp = ehci_readl(reg_ptr); 239 return HOSTPC1_PSPD(tmp); 240 } else 241 return PORTSC_PSPD(reg); 242 } 243 244 /* Set up VBUS for host/device mode */ 245 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 246 { 247 /* 248 * If we are an OTG port initializing in host mode, 249 * check if remote host is driving VBus and bail out in this case. 250 */ 251 if (init == USB_INIT_HOST && 252 config->dr_mode == DR_MODE_OTG && 253 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 254 printf("tegrausb: VBUS input active; not enabling as host\n"); 255 return; 256 } 257 258 if (dm_gpio_is_valid(&config->vbus_gpio)) { 259 int vbus_value; 260 261 vbus_value = (init == USB_INIT_HOST); 262 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 263 264 debug("set_up_vbus: GPIO %d %d\n", 265 gpio_get_number(&config->vbus_gpio), vbus_value); 266 } 267 } 268 269 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) 270 { 271 /* Reset the USB controller with 2us delay */ 272 reset_periph(config->periph_id, 2); 273 274 /* 275 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 276 * base address 277 */ 278 if (config->has_legacy_mode) 279 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 280 281 /* Put UTMIP1/3 in reset */ 282 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 283 284 /* Enable the UTMIP PHY */ 285 if (config->utmi) 286 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 287 } 288 289 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) 290 { 291 const unsigned *timing; 292 293 timing = controller->pll_parameter + 294 clock_get_osc_freq() * PARAM_COUNT; 295 296 return timing; 297 } 298 299 /* select the PHY to use with a USB controller */ 300 static void init_phy_mux(struct fdt_usb *config, uint pts, 301 enum usb_init_type init) 302 { 303 struct usb_ctlr *usbctlr = config->reg; 304 305 #if defined(CONFIG_TEGRA20) 306 if (config->periph_id == PERIPH_ID_USBD) { 307 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 308 pts << PTS1_SHIFT); 309 clrbits_le32(&usbctlr->port_sc1, STS1); 310 } else { 311 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 312 pts << PTS_SHIFT); 313 clrbits_le32(&usbctlr->port_sc1, STS); 314 } 315 #else 316 /* Set to Host mode (if applicable) after Controller Reset was done */ 317 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 318 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 319 /* 320 * Select PHY interface after setting host mode. 321 * For device mode, the ordering requirement is not an issue, since 322 * only the first USB controller supports device mode, and that USB 323 * controller can only talk to a UTMI PHY, so the PHY selection is 324 * already made at reset time, so this write is a no-op. 325 */ 326 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 327 pts << PTS_SHIFT); 328 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 329 #endif 330 } 331 332 /* set up the UTMI USB controller with the parameters provided */ 333 static int init_utmi_usb_controller(struct fdt_usb *config, 334 enum usb_init_type init) 335 { 336 struct fdt_usb_controller *controller; 337 u32 b_sess_valid_mask, val; 338 int loop_count; 339 const unsigned *timing; 340 struct usb_ctlr *usbctlr = config->reg; 341 struct clk_rst_ctlr *clkrst; 342 struct usb_ctlr *usb1ctlr; 343 344 clock_enable(config->periph_id); 345 346 /* Reset the usb controller */ 347 usbf_reset_controller(config, usbctlr); 348 349 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 350 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 351 352 /* Follow the crystal clock disable by >100ns delay */ 353 udelay(1); 354 355 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 356 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 357 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 358 359 /* 360 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 361 * mux must be switched to actually use a_sess_vld threshold. 362 */ 363 if (config->dr_mode == DR_MODE_OTG && 364 dm_gpio_is_valid(&config->vbus_gpio)) 365 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 366 VBUS_SENSE_CTL_MASK, 367 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 368 369 controller = &fdt_usb_controllers[config->type]; 370 debug("controller=%p, type=%d\n", controller, config->type); 371 372 /* 373 * PLL Delay CONFIGURATION settings. The following parameters control 374 * the bring up of the plls. 375 */ 376 timing = get_pll_timing(controller); 377 378 if (!controller->has_hostpc) { 379 val = readl(&usbctlr->utmip_misc_cfg1); 380 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 381 timing[PARAM_STABLE_COUNT] << 382 UTMIP_PLLU_STABLE_COUNT_SHIFT); 383 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 384 timing[PARAM_ACTIVE_DELAY_COUNT] << 385 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 386 writel(val, &usbctlr->utmip_misc_cfg1); 387 388 /* Set PLL enable delay count and crystal frequency count */ 389 val = readl(&usbctlr->utmip_pll_cfg1); 390 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 391 timing[PARAM_ENABLE_DELAY_COUNT] << 392 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 393 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 394 timing[PARAM_XTAL_FREQ_COUNT] << 395 UTMIP_XTAL_FREQ_COUNT_SHIFT); 396 writel(val, &usbctlr->utmip_pll_cfg1); 397 } else { 398 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 399 400 val = readl(&clkrst->crc_utmip_pll_cfg2); 401 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 402 timing[PARAM_STABLE_COUNT] << 403 UTMIP_PLLU_STABLE_COUNT_SHIFT); 404 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 405 timing[PARAM_ACTIVE_DELAY_COUNT] << 406 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 407 writel(val, &clkrst->crc_utmip_pll_cfg2); 408 409 /* Set PLL enable delay count and crystal frequency count */ 410 val = readl(&clkrst->crc_utmip_pll_cfg1); 411 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 412 timing[PARAM_ENABLE_DELAY_COUNT] << 413 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 414 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 415 timing[PARAM_XTAL_FREQ_COUNT] << 416 UTMIP_XTAL_FREQ_COUNT_SHIFT); 417 writel(val, &clkrst->crc_utmip_pll_cfg1); 418 419 /* Disable Power Down state for PLL */ 420 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 421 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 422 PLL_ACTIVE_POWERDOWN); 423 424 /* Recommended PHY settings for EYE diagram */ 425 val = readl(&usbctlr->utmip_xcvr_cfg0); 426 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 427 0x4 << UTMIP_XCVR_SETUP_SHIFT); 428 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 429 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 430 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 431 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 432 writel(val, &usbctlr->utmip_xcvr_cfg0); 433 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 434 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 435 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 436 437 /* Some registers can be controlled from USB1 only. */ 438 if (config->periph_id != PERIPH_ID_USBD) { 439 clock_enable(PERIPH_ID_USBD); 440 /* Disable Reset if in Reset state */ 441 reset_set_enable(PERIPH_ID_USBD, 0); 442 } 443 usb1ctlr = (struct usb_ctlr *) 444 ((unsigned long)config->reg & USB1_ADDR_MASK); 445 val = readl(&usb1ctlr->utmip_bias_cfg0); 446 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 447 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 448 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 449 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 450 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 451 writel(val, &usb1ctlr->utmip_bias_cfg0); 452 453 /* Miscellaneous setting mentioned in Programming Guide */ 454 clrbits_le32(&usbctlr->utmip_misc_cfg0, 455 UTMIP_SUSPEND_EXIT_ON_EDGE); 456 } 457 458 /* Setting the tracking length time */ 459 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 460 UTMIP_BIAS_PDTRK_COUNT_MASK, 461 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 462 463 /* Program debounce time for VBUS to become valid */ 464 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 465 UTMIP_DEBOUNCE_CFG0_MASK, 466 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 467 468 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 469 470 /* Disable battery charge enabling bit */ 471 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 472 473 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 474 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 475 476 /* 477 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 478 * Setting these fields, together with default values of the 479 * other fields, results in programming the registers below as 480 * follows: 481 * UTMIP_HSRX_CFG0 = 0x9168c000 482 * UTMIP_HSRX_CFG1 = 0x13 483 */ 484 485 /* Set PLL enable delay count and Crystal frequency count */ 486 val = readl(&usbctlr->utmip_hsrx_cfg0); 487 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 488 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 489 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 490 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 491 writel(val, &usbctlr->utmip_hsrx_cfg0); 492 493 /* Configure the UTMIP_HS_SYNC_START_DLY */ 494 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 495 UTMIP_HS_SYNC_START_DLY_MASK, 496 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 497 498 /* Preceed the crystal clock disable by >100ns delay. */ 499 udelay(1); 500 501 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 502 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 503 504 if (controller->has_hostpc) { 505 if (config->periph_id == PERIPH_ID_USBD) 506 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 507 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 508 if (config->periph_id == PERIPH_ID_USB2) 509 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 510 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 511 if (config->periph_id == PERIPH_ID_USB3) 512 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 513 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 514 } 515 /* Finished the per-controller init. */ 516 517 /* De-assert UTMIP_RESET to bring out of reset. */ 518 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 519 520 /* Wait for the phy clock to become valid in 100 ms */ 521 for (loop_count = 100000; loop_count != 0; loop_count--) { 522 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 523 break; 524 udelay(1); 525 } 526 if (!loop_count) 527 return -1; 528 529 /* Disable ICUSB FS/LS transceiver */ 530 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 531 532 /* Select UTMI parallel interface */ 533 init_phy_mux(config, PTS_UTMI, init); 534 535 /* Deassert power down state */ 536 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 537 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 538 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 539 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 540 541 if (controller->has_hostpc) { 542 /* 543 * BIAS Pad Power Down is common among all 3 USB 544 * controllers and can be controlled from USB1 only. 545 */ 546 usb1ctlr = (struct usb_ctlr *) 547 ((unsigned long)config->reg & USB1_ADDR_MASK); 548 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 549 udelay(25); 550 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 551 UTMIP_FORCE_PDTRK_POWERDOWN); 552 } 553 return 0; 554 } 555 556 #ifdef CONFIG_USB_ULPI 557 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 558 #ifndef CONFIG_ULPI_REF_CLK 559 #define CONFIG_ULPI_REF_CLK 24000000 560 #endif 561 562 /* set up the ULPI USB controller with the parameters provided */ 563 static int init_ulpi_usb_controller(struct fdt_usb *config, 564 enum usb_init_type init) 565 { 566 u32 val; 567 int loop_count; 568 struct ulpi_viewport ulpi_vp; 569 struct usb_ctlr *usbctlr = config->reg; 570 571 /* set up ULPI reference clock on pllp_out4 */ 572 clock_enable(PERIPH_ID_DEV2_OUT); 573 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 574 575 /* reset ULPI phy */ 576 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 577 dm_gpio_set_value(&config->phy_reset_gpio, 0); 578 mdelay(5); 579 dm_gpio_set_value(&config->phy_reset_gpio, 1); 580 } 581 582 /* Reset the usb controller */ 583 clock_enable(config->periph_id); 584 usbf_reset_controller(config, usbctlr); 585 586 /* enable pinmux bypass */ 587 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 588 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 589 590 /* Select ULPI parallel interface */ 591 init_phy_mux(config, PTS_ULPI, init); 592 593 /* enable ULPI transceiver */ 594 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 595 596 /* configure ULPI transceiver timings */ 597 val = 0; 598 writel(val, &usbctlr->ulpi_timing_ctrl_1); 599 600 val |= ULPI_DATA_TRIMMER_SEL(4); 601 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 602 val |= ULPI_DIR_TRIMMER_SEL(4); 603 writel(val, &usbctlr->ulpi_timing_ctrl_1); 604 udelay(10); 605 606 val |= ULPI_DATA_TRIMMER_LOAD; 607 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 608 val |= ULPI_DIR_TRIMMER_LOAD; 609 writel(val, &usbctlr->ulpi_timing_ctrl_1); 610 611 /* set up phy for host operation with external vbus supply */ 612 ulpi_vp.port_num = 0; 613 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 614 615 if (ulpi_init(&ulpi_vp)) { 616 printf("Tegra ULPI viewport init failed\n"); 617 return -1; 618 } 619 620 ulpi_set_vbus(&ulpi_vp, 1, 1); 621 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 622 623 /* enable wakeup events */ 624 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 625 626 /* Enable and wait for the phy clock to become valid in 100 ms */ 627 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 628 for (loop_count = 100000; loop_count != 0; loop_count--) { 629 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 630 break; 631 udelay(1); 632 } 633 if (!loop_count) 634 return -1; 635 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 636 637 return 0; 638 } 639 #else 640 static int init_ulpi_usb_controller(struct fdt_usb *config, 641 enum usb_init_type init) 642 { 643 printf("No code to set up ULPI controller, please enable" 644 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 645 return -1; 646 } 647 #endif 648 649 static void config_clock(const u32 timing[]) 650 { 651 clock_start_pll(CLOCK_ID_USB, 652 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 653 timing[PARAM_CPCON], timing[PARAM_LFCON]); 654 } 655 656 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 657 { 658 const char *phy, *mode; 659 660 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 661 mode = fdt_getprop(blob, node, "dr_mode", NULL); 662 if (mode) { 663 if (0 == strcmp(mode, "host")) 664 config->dr_mode = DR_MODE_HOST; 665 else if (0 == strcmp(mode, "peripheral")) 666 config->dr_mode = DR_MODE_DEVICE; 667 else if (0 == strcmp(mode, "otg")) 668 config->dr_mode = DR_MODE_OTG; 669 else { 670 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 671 mode); 672 return -FDT_ERR_NOTFOUND; 673 } 674 } else { 675 config->dr_mode = DR_MODE_HOST; 676 } 677 678 phy = fdt_getprop(blob, node, "phy_type", NULL); 679 config->utmi = phy && 0 == strcmp("utmi", phy); 680 config->ulpi = phy && 0 == strcmp("ulpi", phy); 681 config->enabled = fdtdec_get_is_enabled(blob, node); 682 config->has_legacy_mode = fdtdec_get_bool(blob, node, 683 "nvidia,has-legacy-mode"); 684 config->periph_id = clock_decode_periph_id(blob, node); 685 if (config->periph_id == PERIPH_ID_NONE) { 686 debug("%s: Missing/invalid peripheral ID\n", __func__); 687 return -FDT_ERR_NOTFOUND; 688 } 689 gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, 690 &config->vbus_gpio, GPIOD_IS_OUT); 691 gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, 692 &config->phy_reset_gpio, GPIOD_IS_OUT); 693 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 694 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 695 config->enabled, config->has_legacy_mode, config->utmi, 696 config->ulpi, config->periph_id, 697 gpio_get_number(&config->vbus_gpio), 698 gpio_get_number(&config->phy_reset_gpio), config->dr_mode); 699 700 return 0; 701 } 702 703 static const struct ehci_ops tegra_ehci_ops = { 704 .set_usb_mode = tegra_ehci_set_usbmode, 705 .get_port_speed = tegra_ehci_get_port_speed, 706 .powerup_fixup = tegra_ehci_powerup_fixup, 707 }; 708 709 /* 710 * process_usb_nodes() - Process a list of USB nodes, adding them to our list 711 * of USB ports. 712 * @blob: fdt blob 713 * @node_list: list of nodes to process (any <=0 are ignored) 714 * @count: number of nodes to process 715 * @id: controller type (enum usb_ctlr_type) 716 * 717 * Return: 0 - ok, -1 - error 718 */ 719 static int process_usb_nodes(const void *blob, int node_list[], int count, 720 enum usb_ctlr_type id) 721 { 722 struct fdt_usb config; 723 int node, i; 724 int clk_done = 0; 725 726 port_count = 0; 727 for (i = 0; i < count; i++) { 728 if (port_count == USB_PORTS_MAX) { 729 printf("tegrausb: Cannot register more than %d ports\n", 730 USB_PORTS_MAX); 731 return -1; 732 } 733 734 debug("USB %d: ", i); 735 node = node_list[i]; 736 if (!node) 737 continue; 738 if (fdt_decode_usb(blob, node, &config)) { 739 debug("Cannot decode USB node %s\n", 740 fdt_get_name(blob, node, NULL)); 741 return -1; 742 } 743 if (!clk_done) { 744 config_clock(get_pll_timing( 745 &fdt_usb_controllers[id])); 746 clk_done = 1; 747 } 748 config.type = id; 749 config.initialized = 0; 750 751 /* add new USB port to the list of available ports */ 752 port[port_count++] = config; 753 } 754 755 return 0; 756 } 757 758 int usb_process_devicetree(const void *blob) 759 { 760 int node_list[USB_PORTS_MAX]; 761 int count, err = 0; 762 int i; 763 764 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { 765 count = fdtdec_find_aliases_for_id(blob, "usb", 766 fdt_usb_controllers[i].compat, node_list, 767 USB_PORTS_MAX); 768 if (count) { 769 err = process_usb_nodes(blob, node_list, count, i); 770 if (err) 771 printf("%s: Error processing USB node!\n", 772 __func__); 773 return err; 774 } 775 } 776 777 return err; 778 } 779 780 /** 781 * Start up the given port number (ports are numbered from 0 on each board). 782 * This returns values for the appropriate hccr and hcor addresses to use for 783 * USB EHCI operations. 784 * 785 * @param index port number to start 786 * @param hccr returns start address of EHCI HCCR registers 787 * @param hcor returns start address of EHCI HCOR registers 788 * @return 0 if ok, -1 on error (generally invalid port number) 789 */ 790 int ehci_hcd_init(int index, enum usb_init_type init, 791 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 792 { 793 struct fdt_usb *config; 794 struct usb_ctlr *usbctlr; 795 796 if (index >= port_count) 797 return -1; 798 799 config = &port[index]; 800 ehci_set_controller_priv(index, config, &tegra_ehci_ops); 801 802 switch (init) { 803 case USB_INIT_HOST: 804 switch (config->dr_mode) { 805 case DR_MODE_HOST: 806 case DR_MODE_OTG: 807 break; 808 default: 809 printf("tegrausb: Invalid dr_mode %d for host mode\n", 810 config->dr_mode); 811 return -1; 812 } 813 break; 814 case USB_INIT_DEVICE: 815 if (config->periph_id != PERIPH_ID_USBD) { 816 printf("tegrausb: Device mode only supported on first USB controller\n"); 817 return -1; 818 } 819 if (!config->utmi) { 820 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 821 return -1; 822 } 823 switch (config->dr_mode) { 824 case DR_MODE_DEVICE: 825 case DR_MODE_OTG: 826 break; 827 default: 828 printf("tegrausb: Invalid dr_mode %d for device mode\n", 829 config->dr_mode); 830 return -1; 831 } 832 break; 833 default: 834 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 835 return -1; 836 } 837 838 /* skip init, if the port is already initialized */ 839 if (config->initialized && config->init_type == init) 840 goto success; 841 842 if (config->utmi && init_utmi_usb_controller(config, init)) { 843 printf("tegrausb: Cannot init port %d\n", index); 844 return -1; 845 } 846 847 if (config->ulpi && init_ulpi_usb_controller(config, init)) { 848 printf("tegrausb: Cannot init port %d\n", index); 849 return -1; 850 } 851 852 set_up_vbus(config, init); 853 854 config->initialized = 1; 855 config->init_type = init; 856 857 success: 858 usbctlr = config->reg; 859 *hccr = (struct ehci_hccr *)&usbctlr->cap_length; 860 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; 861 862 return 0; 863 } 864 865 /* 866 * Bring down the specified USB controller 867 */ 868 int ehci_hcd_stop(int index) 869 { 870 struct usb_ctlr *usbctlr; 871 872 usbctlr = port[index].reg; 873 874 /* Stop controller */ 875 writel(0, &usbctlr->usb_cmd); 876 udelay(1000); 877 878 /* Initiate controller reset */ 879 writel(2, &usbctlr->usb_cmd); 880 udelay(1000); 881 882 port[index].initialized = 0; 883 884 return 0; 885 } 886