1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2012 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/errno.h> 27 #include <asm/io.h> 28 #include <asm-generic/gpio.h> 29 #include <asm/arch/clock.h> 30 #include <asm/arch-tegra/usb.h> 31 #include <usb.h> 32 #include <usb/ulpi.h> 33 #include <libfdt.h> 34 #include <fdtdec.h> 35 36 #include "ehci.h" 37 38 #ifdef CONFIG_USB_ULPI 39 #ifndef CONFIG_USB_ULPI_VIEWPORT 40 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 41 define CONFIG_USB_ULPI_VIEWPORT" 42 #endif 43 #endif 44 45 enum { 46 USB_PORTS_MAX = 3, /* Maximum ports we allow */ 47 }; 48 49 /* Parameters we need for USB */ 50 enum { 51 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 52 PARAM_DIVM, /* PLL INPUT DIVIDER */ 53 PARAM_DIVP, /* POST DIVIDER (2^N) */ 54 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 55 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 56 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 57 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 58 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 59 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 60 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 61 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 62 63 PARAM_COUNT 64 }; 65 66 /* Possible port types (dual role mode) */ 67 enum dr_mode { 68 DR_MODE_NONE = 0, 69 DR_MODE_HOST, /* supports host operation */ 70 DR_MODE_DEVICE, /* supports device operation */ 71 DR_MODE_OTG, /* supports both */ 72 }; 73 74 /* Information about a USB port */ 75 struct fdt_usb { 76 struct usb_ctlr *reg; /* address of registers in physical memory */ 77 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 78 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 79 unsigned enabled:1; /* 1 to enable, 0 to disable */ 80 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 81 unsigned initialized:1; /* has this port already been initialized? */ 82 enum dr_mode dr_mode; /* dual role mode */ 83 enum periph_id periph_id;/* peripheral id */ 84 struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ 85 struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */ 86 }; 87 88 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ 89 static unsigned port_count; /* Number of available ports */ 90 91 /* 92 * This table has USB timing parameters for each Oscillator frequency we 93 * support. There are four sets of values: 94 * 95 * 1. PLLU configuration information (reference clock is osc/clk_m and 96 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 97 * 98 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 99 * ---------------------------------------------------------------------- 100 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 101 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 102 * Filter frequency (MHz) 1 4.8 6 2 103 * CPCON 1100b 0011b 1100b 1100b 104 * LFCON0 0 0 0 0 105 * 106 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 107 * 108 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 109 * --------------------------------------------------------------------------- 110 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 111 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 112 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 113 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 114 * 115 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 116 * SessEnd. Each of these signals have their own debouncer and for each of 117 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 118 * BIAS_DEBOUNCE_B). 119 * 120 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 121 * 0xffff -> No debouncing at all 122 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 123 * 124 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 125 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 126 * 127 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 128 * values, so we can keep those to default. 129 * 130 * 4. The 20 microsecond delay after bias cell operation. 131 */ 132 static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 133 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 134 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 135 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 136 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 137 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 138 }; 139 140 /* UTMIP Idle Wait Delay */ 141 static const u8 utmip_idle_wait_delay = 17; 142 143 /* UTMIP Elastic limit */ 144 static const u8 utmip_elastic_limit = 16; 145 146 /* UTMIP High Speed Sync Start Delay */ 147 static const u8 utmip_hs_sync_start_delay = 9; 148 149 /* 150 * A known hardware issue where Connect Status Change bit of PORTSC register 151 * of USB1 controller will be set after Port Reset. 152 * We have to clear it in order for later device enumeration to proceed. 153 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup 154 * in "ehci-hcd.c". 155 */ 156 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 157 { 158 mdelay(50); 159 if (((u32) status_reg & TEGRA_USB_ADDR_MASK) != TEGRA_USB1_BASE) 160 return; 161 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 162 if (ehci_readl(status_reg) & EHCI_PS_CSC) 163 *reg |= EHCI_PS_CSC; 164 } 165 166 /* Put the port into host mode */ 167 static void set_host_mode(struct fdt_usb *config) 168 { 169 /* 170 * If we are an OTG port, check if remote host is driving VBus and 171 * bail out in this case. 172 */ 173 if (config->dr_mode == DR_MODE_OTG && 174 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) 175 return; 176 177 /* 178 * If not driving, we set the GPIO to enable VBUS. We assume 179 * that the pinmux is set up correctly for this. 180 */ 181 if (fdt_gpio_isvalid(&config->vbus_gpio)) { 182 fdtdec_setup_gpio(&config->vbus_gpio); 183 gpio_direction_output(config->vbus_gpio.gpio, 184 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? 185 0 : 1); 186 debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, 187 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? 188 "low" : "high"); 189 } 190 } 191 192 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) 193 { 194 /* Reset the USB controller with 2us delay */ 195 reset_periph(config->periph_id, 2); 196 197 /* 198 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 199 * base address 200 */ 201 if (config->has_legacy_mode) 202 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 203 204 /* Put UTMIP1/3 in reset */ 205 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 206 207 /* Enable the UTMIP PHY */ 208 if (config->utmi) 209 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 210 } 211 212 /* set up the UTMI USB controller with the parameters provided */ 213 static int init_utmi_usb_controller(struct fdt_usb *config) 214 { 215 u32 val; 216 int loop_count; 217 const unsigned *timing; 218 struct usb_ctlr *usbctlr = config->reg; 219 220 clock_enable(config->periph_id); 221 222 /* Reset the usb controller */ 223 usbf_reset_controller(config, usbctlr); 224 225 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 226 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 227 228 /* Follow the crystal clock disable by >100ns delay */ 229 udelay(1); 230 231 /* 232 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 233 * mux must be switched to actually use a_sess_vld threshold. 234 */ 235 if (fdt_gpio_isvalid(&config->vbus_gpio)) { 236 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 237 VBUS_SENSE_CTL_MASK, 238 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 239 } 240 241 /* 242 * PLL Delay CONFIGURATION settings. The following parameters control 243 * the bring up of the plls. 244 */ 245 timing = usb_pll[clock_get_osc_freq()]; 246 247 val = readl(&usbctlr->utmip_misc_cfg1); 248 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 249 timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); 250 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 251 timing[PARAM_ACTIVE_DELAY_COUNT] << 252 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 253 writel(val, &usbctlr->utmip_misc_cfg1); 254 255 /* Set PLL enable delay count and crystal frequency count */ 256 val = readl(&usbctlr->utmip_pll_cfg1); 257 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 258 timing[PARAM_ENABLE_DELAY_COUNT] << 259 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 260 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 261 timing[PARAM_XTAL_FREQ_COUNT] << 262 UTMIP_XTAL_FREQ_COUNT_SHIFT); 263 writel(val, &usbctlr->utmip_pll_cfg1); 264 265 /* Setting the tracking length time */ 266 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 267 UTMIP_BIAS_PDTRK_COUNT_MASK, 268 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 269 270 /* Program debounce time for VBUS to become valid */ 271 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 272 UTMIP_DEBOUNCE_CFG0_MASK, 273 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 274 275 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 276 277 /* Disable battery charge enabling bit */ 278 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 279 280 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 281 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 282 283 /* 284 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 285 * Setting these fields, together with default values of the 286 * other fields, results in programming the registers below as 287 * follows: 288 * UTMIP_HSRX_CFG0 = 0x9168c000 289 * UTMIP_HSRX_CFG1 = 0x13 290 */ 291 292 /* Set PLL enable delay count and Crystal frequency count */ 293 val = readl(&usbctlr->utmip_hsrx_cfg0); 294 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 295 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 296 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 297 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 298 writel(val, &usbctlr->utmip_hsrx_cfg0); 299 300 /* Configure the UTMIP_HS_SYNC_START_DLY */ 301 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 302 UTMIP_HS_SYNC_START_DLY_MASK, 303 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 304 305 /* Preceed the crystal clock disable by >100ns delay. */ 306 udelay(1); 307 308 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 309 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 310 311 /* Finished the per-controller init. */ 312 313 /* De-assert UTMIP_RESET to bring out of reset. */ 314 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 315 316 /* Wait for the phy clock to become valid in 100 ms */ 317 for (loop_count = 100000; loop_count != 0; loop_count--) { 318 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 319 break; 320 udelay(1); 321 } 322 if (!loop_count) 323 return -1; 324 325 /* Disable ICUSB FS/LS transceiver */ 326 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 327 328 /* Select UTMI parallel interface */ 329 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 330 PTS_UTMI << PTS_SHIFT); 331 clrbits_le32(&usbctlr->port_sc1, STS); 332 333 /* Deassert power down state */ 334 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 335 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 336 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 337 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 338 339 return 0; 340 } 341 342 #ifdef CONFIG_USB_ULPI 343 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 344 #ifndef CONFIG_ULPI_REF_CLK 345 #define CONFIG_ULPI_REF_CLK 24000000 346 #endif 347 348 /* set up the ULPI USB controller with the parameters provided */ 349 static int init_ulpi_usb_controller(struct fdt_usb *config) 350 { 351 u32 val; 352 int loop_count; 353 struct ulpi_viewport ulpi_vp; 354 struct usb_ctlr *usbctlr = config->reg; 355 356 /* set up ULPI reference clock on pllp_out4 */ 357 clock_enable(PERIPH_ID_DEV2_OUT); 358 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 359 360 /* reset ULPI phy */ 361 if (fdt_gpio_isvalid(&config->phy_reset_gpio)) { 362 fdtdec_setup_gpio(&config->phy_reset_gpio); 363 gpio_direction_output(config->phy_reset_gpio.gpio, 0); 364 mdelay(5); 365 gpio_set_value(config->phy_reset_gpio.gpio, 1); 366 } 367 368 /* Reset the usb controller */ 369 clock_enable(config->periph_id); 370 usbf_reset_controller(config, usbctlr); 371 372 /* enable pinmux bypass */ 373 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 374 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 375 376 /* Select ULPI parallel interface */ 377 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT); 378 379 /* enable ULPI transceiver */ 380 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 381 382 /* configure ULPI transceiver timings */ 383 val = 0; 384 writel(val, &usbctlr->ulpi_timing_ctrl_1); 385 386 val |= ULPI_DATA_TRIMMER_SEL(4); 387 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 388 val |= ULPI_DIR_TRIMMER_SEL(4); 389 writel(val, &usbctlr->ulpi_timing_ctrl_1); 390 udelay(10); 391 392 val |= ULPI_DATA_TRIMMER_LOAD; 393 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 394 val |= ULPI_DIR_TRIMMER_LOAD; 395 writel(val, &usbctlr->ulpi_timing_ctrl_1); 396 397 /* set up phy for host operation with external vbus supply */ 398 ulpi_vp.port_num = 0; 399 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 400 401 if (ulpi_init(&ulpi_vp)) { 402 printf("Tegra ULPI viewport init failed\n"); 403 return -1; 404 } 405 406 ulpi_set_vbus(&ulpi_vp, 1, 1); 407 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 408 409 /* enable wakeup events */ 410 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 411 412 /* Enable and wait for the phy clock to become valid in 100 ms */ 413 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 414 for (loop_count = 100000; loop_count != 0; loop_count--) { 415 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 416 break; 417 udelay(1); 418 } 419 if (!loop_count) 420 return -1; 421 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 422 423 return 0; 424 } 425 #else 426 static int init_ulpi_usb_controller(struct fdt_usb *config) 427 { 428 printf("No code to set up ULPI controller, please enable" 429 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 430 return -1; 431 } 432 #endif 433 434 static void config_clock(const u32 timing[]) 435 { 436 clock_start_pll(CLOCK_ID_USB, 437 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 438 timing[PARAM_CPCON], timing[PARAM_LFCON]); 439 } 440 441 int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor) 442 { 443 struct fdt_usb *config; 444 struct usb_ctlr *usbctlr; 445 446 if (portnum >= port_count) 447 return -1; 448 449 config = &port[portnum]; 450 451 /* skip init, if the port is already initialized */ 452 if (config->initialized) 453 goto success; 454 455 if (config->utmi && init_utmi_usb_controller(config)) { 456 printf("tegrausb: Cannot init port %d\n", portnum); 457 return -1; 458 } 459 460 if (config->ulpi && init_ulpi_usb_controller(config)) { 461 printf("tegrausb: Cannot init port %d\n", portnum); 462 return -1; 463 } 464 465 set_host_mode(config); 466 467 config->initialized = 1; 468 469 success: 470 usbctlr = config->reg; 471 *hccr = (u32)&usbctlr->cap_length; 472 *hcor = (u32)&usbctlr->usb_cmd; 473 return 0; 474 } 475 476 int tegrausb_stop_port(int portnum) 477 { 478 struct usb_ctlr *usbctlr; 479 480 usbctlr = port[portnum].reg; 481 482 /* Stop controller */ 483 writel(0, &usbctlr->usb_cmd); 484 udelay(1000); 485 486 /* Initiate controller reset */ 487 writel(2, &usbctlr->usb_cmd); 488 udelay(1000); 489 490 port[portnum].initialized = 0; 491 492 return 0; 493 } 494 495 int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 496 { 497 const char *phy, *mode; 498 499 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 500 mode = fdt_getprop(blob, node, "dr_mode", NULL); 501 if (mode) { 502 if (0 == strcmp(mode, "host")) 503 config->dr_mode = DR_MODE_HOST; 504 else if (0 == strcmp(mode, "peripheral")) 505 config->dr_mode = DR_MODE_DEVICE; 506 else if (0 == strcmp(mode, "otg")) 507 config->dr_mode = DR_MODE_OTG; 508 else { 509 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 510 mode); 511 return -FDT_ERR_NOTFOUND; 512 } 513 } else { 514 config->dr_mode = DR_MODE_HOST; 515 } 516 517 phy = fdt_getprop(blob, node, "phy_type", NULL); 518 config->utmi = phy && 0 == strcmp("utmi", phy); 519 config->ulpi = phy && 0 == strcmp("ulpi", phy); 520 config->enabled = fdtdec_get_is_enabled(blob, node); 521 config->has_legacy_mode = fdtdec_get_bool(blob, node, 522 "nvidia,has-legacy-mode"); 523 config->periph_id = clock_decode_periph_id(blob, node); 524 if (config->periph_id == PERIPH_ID_NONE) { 525 debug("%s: Missing/invalid peripheral ID\n", __func__); 526 return -FDT_ERR_NOTFOUND; 527 } 528 fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); 529 fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio", 530 &config->phy_reset_gpio); 531 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 532 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 533 config->enabled, config->has_legacy_mode, config->utmi, 534 config->ulpi, config->periph_id, config->vbus_gpio.gpio, 535 config->phy_reset_gpio.gpio, config->dr_mode); 536 537 return 0; 538 } 539 540 int board_usb_init(const void *blob) 541 { 542 struct fdt_usb config; 543 enum clock_osc_freq freq; 544 int node_list[USB_PORTS_MAX]; 545 int node, count, i; 546 547 /* Set up the USB clocks correctly based on our oscillator frequency */ 548 freq = clock_get_osc_freq(); 549 config_clock(usb_pll[freq]); 550 551 /* count may return <0 on error */ 552 count = fdtdec_find_aliases_for_id(blob, "usb", 553 COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); 554 for (i = 0; i < count; i++) { 555 if (port_count == USB_PORTS_MAX) { 556 printf("tegrausb: Cannot register more than %d ports\n", 557 USB_PORTS_MAX); 558 return -1; 559 } 560 561 debug("USB %d: ", i); 562 node = node_list[i]; 563 if (!node) 564 continue; 565 if (fdt_decode_usb(blob, node, &config)) { 566 debug("Cannot decode USB node %s\n", 567 fdt_get_name(blob, node, NULL)); 568 return -1; 569 } 570 config.initialized = 0; 571 572 /* add new USB port to the list of available ports */ 573 port[port_count++] = config; 574 } 575 576 return 0; 577 } 578 579 /* 580 * Create the appropriate control structures to manage 581 * a new EHCI host controller. 582 */ 583 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 584 { 585 u32 our_hccr, our_hcor; 586 587 /* 588 * Select the first port, as we don't have a way of selecting others 589 * yet 590 */ 591 if (tegrausb_start_port(index, &our_hccr, &our_hcor)) 592 return -1; 593 594 *hccr = (struct ehci_hccr *)our_hccr; 595 *hcor = (struct ehci_hcor *)our_hcor; 596 597 return 0; 598 } 599 600 /* 601 * Destroy the appropriate control structures corresponding 602 * the the EHCI host controller. 603 */ 604 int ehci_hcd_stop(int index) 605 { 606 return tegrausb_stop_port(index); 607 } 608