1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2013 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/errno.h> 11 #include <asm/io.h> 12 #include <asm-generic/gpio.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch-tegra/usb.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <usb.h> 17 #include <usb/ulpi.h> 18 #include <libfdt.h> 19 #include <fdtdec.h> 20 21 #include "ehci.h" 22 23 #define USB1_ADDR_MASK 0xFFFF0000 24 25 #define HOSTPC1_DEVLC 0x84 26 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 27 28 #ifdef CONFIG_USB_ULPI 29 #ifndef CONFIG_USB_ULPI_VIEWPORT 30 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 31 define CONFIG_USB_ULPI_VIEWPORT" 32 #endif 33 #endif 34 35 enum { 36 USB_PORTS_MAX = 3, /* Maximum ports we allow */ 37 }; 38 39 /* Parameters we need for USB */ 40 enum { 41 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 42 PARAM_DIVM, /* PLL INPUT DIVIDER */ 43 PARAM_DIVP, /* POST DIVIDER (2^N) */ 44 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 45 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 46 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 47 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 48 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 49 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 50 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 51 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 52 53 PARAM_COUNT 54 }; 55 56 /* Possible port types (dual role mode) */ 57 enum dr_mode { 58 DR_MODE_NONE = 0, 59 DR_MODE_HOST, /* supports host operation */ 60 DR_MODE_DEVICE, /* supports device operation */ 61 DR_MODE_OTG, /* supports both */ 62 }; 63 64 /* Information about a USB port */ 65 struct fdt_usb { 66 struct usb_ctlr *reg; /* address of registers in physical memory */ 67 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 68 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 69 unsigned enabled:1; /* 1 to enable, 0 to disable */ 70 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 71 unsigned initialized:1; /* has this port already been initialized? */ 72 enum usb_init_type init_type; 73 enum dr_mode dr_mode; /* dual role mode */ 74 enum periph_id periph_id;/* peripheral id */ 75 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 76 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 77 }; 78 79 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ 80 static unsigned port_count; /* Number of available ports */ 81 /* Port that needs to clear CSC after Port Reset */ 82 static u32 port_addr_clear_csc; 83 84 /* 85 * This table has USB timing parameters for each Oscillator frequency we 86 * support. There are four sets of values: 87 * 88 * 1. PLLU configuration information (reference clock is osc/clk_m and 89 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 90 * 91 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 92 * ---------------------------------------------------------------------- 93 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 94 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 95 * Filter frequency (MHz) 1 4.8 6 2 96 * CPCON 1100b 0011b 1100b 1100b 97 * LFCON0 0 0 0 0 98 * 99 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 100 * 101 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 102 * --------------------------------------------------------------------------- 103 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 104 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 105 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 106 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 107 * 108 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 109 * SessEnd. Each of these signals have their own debouncer and for each of 110 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 111 * BIAS_DEBOUNCE_B). 112 * 113 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 114 * 0xffff -> No debouncing at all 115 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 116 * 117 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 118 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 119 * 120 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 121 * values, so we can keep those to default. 122 * 123 * 4. The 20 microsecond delay after bias cell operation. 124 */ 125 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 126 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 127 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 128 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 129 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 130 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 131 }; 132 133 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 134 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 135 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 136 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 137 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 138 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 139 }; 140 141 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 142 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 143 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 144 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 145 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 146 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 147 }; 148 149 /* UTMIP Idle Wait Delay */ 150 static const u8 utmip_idle_wait_delay = 17; 151 152 /* UTMIP Elastic limit */ 153 static const u8 utmip_elastic_limit = 16; 154 155 /* UTMIP High Speed Sync Start Delay */ 156 static const u8 utmip_hs_sync_start_delay = 9; 157 158 struct fdt_usb_controller { 159 int compat; 160 /* flag to determine whether controller supports hostpc register */ 161 u32 has_hostpc:1; 162 const unsigned *pll_parameter; 163 }; 164 165 static struct fdt_usb_controller fdt_usb_controllers[] = { 166 { 167 .compat = COMPAT_NVIDIA_TEGRA20_USB, 168 .has_hostpc = 0, 169 .pll_parameter = (const unsigned *)T20_usb_pll, 170 }, 171 { 172 .compat = COMPAT_NVIDIA_TEGRA30_USB, 173 .has_hostpc = 1, 174 .pll_parameter = (const unsigned *)T30_usb_pll, 175 }, 176 { 177 .compat = COMPAT_NVIDIA_TEGRA114_USB, 178 .has_hostpc = 1, 179 .pll_parameter = (const unsigned *)T114_usb_pll, 180 }, 181 }; 182 183 static struct fdt_usb_controller *controller; 184 185 /* 186 * A known hardware issue where Connect Status Change bit of PORTSC register 187 * of USB1 controller will be set after Port Reset. 188 * We have to clear it in order for later device enumeration to proceed. 189 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup 190 * in "ehci-hcd.c". 191 */ 192 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 193 { 194 mdelay(50); 195 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 196 if (controller->has_hostpc) 197 *reg |= EHCI_PS_PE; 198 199 if (((unsigned long)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc) 200 return; 201 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 202 if (ehci_readl(status_reg) & EHCI_PS_CSC) 203 *reg |= EHCI_PS_CSC; 204 } 205 206 /* 207 * This ehci_set_usbmode overrides the weak function ehci_set_usbmode 208 * in "ehci-hcd.c". 209 */ 210 void ehci_set_usbmode(int index) 211 { 212 struct fdt_usb *config; 213 struct usb_ctlr *usbctlr; 214 uint32_t tmp; 215 216 config = &port[index]; 217 usbctlr = config->reg; 218 219 tmp = ehci_readl(&usbctlr->usb_mode); 220 tmp |= USBMODE_CM_HC; 221 ehci_writel(&usbctlr->usb_mode, tmp); 222 } 223 224 /* 225 * This ehci_get_port_speed overrides the weak function ehci_get_port_speed 226 * in "ehci-hcd.c". 227 */ 228 int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 229 { 230 uint32_t tmp; 231 uint32_t *reg_ptr; 232 233 if (controller->has_hostpc) { 234 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 235 HOSTPC1_DEVLC); 236 tmp = ehci_readl(reg_ptr); 237 return HOSTPC1_PSPD(tmp); 238 } else 239 return PORTSC_PSPD(reg); 240 } 241 242 /* Set up VBUS for host/device mode */ 243 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 244 { 245 /* 246 * If we are an OTG port initializing in host mode, 247 * check if remote host is driving VBus and bail out in this case. 248 */ 249 if (init == USB_INIT_HOST && 250 config->dr_mode == DR_MODE_OTG && 251 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 252 printf("tegrausb: VBUS input active; not enabling as host\n"); 253 return; 254 } 255 256 if (dm_gpio_is_valid(&config->vbus_gpio)) { 257 int vbus_value; 258 259 vbus_value = (init == USB_INIT_HOST); 260 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 261 262 debug("set_up_vbus: GPIO %d %d\n", 263 gpio_get_number(&config->vbus_gpio), vbus_value); 264 } 265 } 266 267 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) 268 { 269 /* Reset the USB controller with 2us delay */ 270 reset_periph(config->periph_id, 2); 271 272 /* 273 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 274 * base address 275 */ 276 if (config->has_legacy_mode) 277 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 278 279 /* Put UTMIP1/3 in reset */ 280 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 281 282 /* Enable the UTMIP PHY */ 283 if (config->utmi) 284 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 285 } 286 287 static const unsigned *get_pll_timing(void) 288 { 289 const unsigned *timing; 290 291 timing = controller->pll_parameter + 292 clock_get_osc_freq() * PARAM_COUNT; 293 294 return timing; 295 } 296 297 /* select the PHY to use with a USB controller */ 298 static void init_phy_mux(struct fdt_usb *config, uint pts, 299 enum usb_init_type init) 300 { 301 struct usb_ctlr *usbctlr = config->reg; 302 303 #if defined(CONFIG_TEGRA20) 304 if (config->periph_id == PERIPH_ID_USBD) { 305 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 306 pts << PTS1_SHIFT); 307 clrbits_le32(&usbctlr->port_sc1, STS1); 308 } else { 309 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 310 pts << PTS_SHIFT); 311 clrbits_le32(&usbctlr->port_sc1, STS); 312 } 313 #else 314 /* Set to Host mode (if applicable) after Controller Reset was done */ 315 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 316 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 317 /* 318 * Select PHY interface after setting host mode. 319 * For device mode, the ordering requirement is not an issue, since 320 * only the first USB controller supports device mode, and that USB 321 * controller can only talk to a UTMI PHY, so the PHY selection is 322 * already made at reset time, so this write is a no-op. 323 */ 324 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 325 pts << PTS_SHIFT); 326 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 327 #endif 328 } 329 330 /* set up the UTMI USB controller with the parameters provided */ 331 static int init_utmi_usb_controller(struct fdt_usb *config, 332 enum usb_init_type init) 333 { 334 u32 b_sess_valid_mask, val; 335 int loop_count; 336 const unsigned *timing; 337 struct usb_ctlr *usbctlr = config->reg; 338 struct clk_rst_ctlr *clkrst; 339 struct usb_ctlr *usb1ctlr; 340 341 clock_enable(config->periph_id); 342 343 /* Reset the usb controller */ 344 usbf_reset_controller(config, usbctlr); 345 346 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 347 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 348 349 /* Follow the crystal clock disable by >100ns delay */ 350 udelay(1); 351 352 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 353 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 354 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 355 356 /* 357 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 358 * mux must be switched to actually use a_sess_vld threshold. 359 */ 360 if (config->dr_mode == DR_MODE_OTG && 361 dm_gpio_is_valid(&config->vbus_gpio)) 362 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 363 VBUS_SENSE_CTL_MASK, 364 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 365 366 /* 367 * PLL Delay CONFIGURATION settings. The following parameters control 368 * the bring up of the plls. 369 */ 370 timing = get_pll_timing(); 371 372 if (!controller->has_hostpc) { 373 val = readl(&usbctlr->utmip_misc_cfg1); 374 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 375 timing[PARAM_STABLE_COUNT] << 376 UTMIP_PLLU_STABLE_COUNT_SHIFT); 377 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 378 timing[PARAM_ACTIVE_DELAY_COUNT] << 379 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 380 writel(val, &usbctlr->utmip_misc_cfg1); 381 382 /* Set PLL enable delay count and crystal frequency count */ 383 val = readl(&usbctlr->utmip_pll_cfg1); 384 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 385 timing[PARAM_ENABLE_DELAY_COUNT] << 386 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 387 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 388 timing[PARAM_XTAL_FREQ_COUNT] << 389 UTMIP_XTAL_FREQ_COUNT_SHIFT); 390 writel(val, &usbctlr->utmip_pll_cfg1); 391 } else { 392 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 393 394 val = readl(&clkrst->crc_utmip_pll_cfg2); 395 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 396 timing[PARAM_STABLE_COUNT] << 397 UTMIP_PLLU_STABLE_COUNT_SHIFT); 398 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 399 timing[PARAM_ACTIVE_DELAY_COUNT] << 400 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 401 writel(val, &clkrst->crc_utmip_pll_cfg2); 402 403 /* Set PLL enable delay count and crystal frequency count */ 404 val = readl(&clkrst->crc_utmip_pll_cfg1); 405 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 406 timing[PARAM_ENABLE_DELAY_COUNT] << 407 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 408 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 409 timing[PARAM_XTAL_FREQ_COUNT] << 410 UTMIP_XTAL_FREQ_COUNT_SHIFT); 411 writel(val, &clkrst->crc_utmip_pll_cfg1); 412 413 /* Disable Power Down state for PLL */ 414 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 415 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 416 PLL_ACTIVE_POWERDOWN); 417 418 /* Recommended PHY settings for EYE diagram */ 419 val = readl(&usbctlr->utmip_xcvr_cfg0); 420 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 421 0x4 << UTMIP_XCVR_SETUP_SHIFT); 422 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 423 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 424 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 425 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 426 writel(val, &usbctlr->utmip_xcvr_cfg0); 427 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 428 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 429 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 430 431 /* Some registers can be controlled from USB1 only. */ 432 if (config->periph_id != PERIPH_ID_USBD) { 433 clock_enable(PERIPH_ID_USBD); 434 /* Disable Reset if in Reset state */ 435 reset_set_enable(PERIPH_ID_USBD, 0); 436 } 437 usb1ctlr = (struct usb_ctlr *) 438 ((unsigned long)config->reg & USB1_ADDR_MASK); 439 val = readl(&usb1ctlr->utmip_bias_cfg0); 440 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 441 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 442 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 443 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 444 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 445 writel(val, &usb1ctlr->utmip_bias_cfg0); 446 447 /* Miscellaneous setting mentioned in Programming Guide */ 448 clrbits_le32(&usbctlr->utmip_misc_cfg0, 449 UTMIP_SUSPEND_EXIT_ON_EDGE); 450 } 451 452 /* Setting the tracking length time */ 453 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 454 UTMIP_BIAS_PDTRK_COUNT_MASK, 455 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 456 457 /* Program debounce time for VBUS to become valid */ 458 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 459 UTMIP_DEBOUNCE_CFG0_MASK, 460 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 461 462 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 463 464 /* Disable battery charge enabling bit */ 465 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 466 467 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 468 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 469 470 /* 471 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 472 * Setting these fields, together with default values of the 473 * other fields, results in programming the registers below as 474 * follows: 475 * UTMIP_HSRX_CFG0 = 0x9168c000 476 * UTMIP_HSRX_CFG1 = 0x13 477 */ 478 479 /* Set PLL enable delay count and Crystal frequency count */ 480 val = readl(&usbctlr->utmip_hsrx_cfg0); 481 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 482 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 483 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 484 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 485 writel(val, &usbctlr->utmip_hsrx_cfg0); 486 487 /* Configure the UTMIP_HS_SYNC_START_DLY */ 488 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 489 UTMIP_HS_SYNC_START_DLY_MASK, 490 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 491 492 /* Preceed the crystal clock disable by >100ns delay. */ 493 udelay(1); 494 495 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 496 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 497 498 if (controller->has_hostpc) { 499 if (config->periph_id == PERIPH_ID_USBD) 500 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 501 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 502 if (config->periph_id == PERIPH_ID_USB2) 503 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 504 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 505 if (config->periph_id == PERIPH_ID_USB3) 506 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 507 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 508 } 509 /* Finished the per-controller init. */ 510 511 /* De-assert UTMIP_RESET to bring out of reset. */ 512 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 513 514 /* Wait for the phy clock to become valid in 100 ms */ 515 for (loop_count = 100000; loop_count != 0; loop_count--) { 516 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 517 break; 518 udelay(1); 519 } 520 if (!loop_count) 521 return -1; 522 523 /* Disable ICUSB FS/LS transceiver */ 524 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 525 526 /* Select UTMI parallel interface */ 527 init_phy_mux(config, PTS_UTMI, init); 528 529 /* Deassert power down state */ 530 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 531 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 532 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 533 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 534 535 if (controller->has_hostpc) { 536 /* 537 * BIAS Pad Power Down is common among all 3 USB 538 * controllers and can be controlled from USB1 only. 539 */ 540 usb1ctlr = (struct usb_ctlr *) 541 ((unsigned long)config->reg & USB1_ADDR_MASK); 542 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 543 udelay(25); 544 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 545 UTMIP_FORCE_PDTRK_POWERDOWN); 546 } 547 return 0; 548 } 549 550 #ifdef CONFIG_USB_ULPI 551 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 552 #ifndef CONFIG_ULPI_REF_CLK 553 #define CONFIG_ULPI_REF_CLK 24000000 554 #endif 555 556 /* set up the ULPI USB controller with the parameters provided */ 557 static int init_ulpi_usb_controller(struct fdt_usb *config, 558 enum usb_init_type init) 559 { 560 u32 val; 561 int loop_count; 562 struct ulpi_viewport ulpi_vp; 563 struct usb_ctlr *usbctlr = config->reg; 564 565 /* set up ULPI reference clock on pllp_out4 */ 566 clock_enable(PERIPH_ID_DEV2_OUT); 567 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 568 569 /* reset ULPI phy */ 570 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 571 dm_gpio_set_value(&config->phy_reset_gpio, 0); 572 mdelay(5); 573 dm_gpio_set_value(&config->phy_reset_gpio, 1); 574 } 575 576 /* Reset the usb controller */ 577 clock_enable(config->periph_id); 578 usbf_reset_controller(config, usbctlr); 579 580 /* enable pinmux bypass */ 581 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 582 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 583 584 /* Select ULPI parallel interface */ 585 init_phy_mux(config, PTS_ULPI, init); 586 587 /* enable ULPI transceiver */ 588 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 589 590 /* configure ULPI transceiver timings */ 591 val = 0; 592 writel(val, &usbctlr->ulpi_timing_ctrl_1); 593 594 val |= ULPI_DATA_TRIMMER_SEL(4); 595 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 596 val |= ULPI_DIR_TRIMMER_SEL(4); 597 writel(val, &usbctlr->ulpi_timing_ctrl_1); 598 udelay(10); 599 600 val |= ULPI_DATA_TRIMMER_LOAD; 601 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 602 val |= ULPI_DIR_TRIMMER_LOAD; 603 writel(val, &usbctlr->ulpi_timing_ctrl_1); 604 605 /* set up phy for host operation with external vbus supply */ 606 ulpi_vp.port_num = 0; 607 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 608 609 if (ulpi_init(&ulpi_vp)) { 610 printf("Tegra ULPI viewport init failed\n"); 611 return -1; 612 } 613 614 ulpi_set_vbus(&ulpi_vp, 1, 1); 615 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 616 617 /* enable wakeup events */ 618 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 619 620 /* Enable and wait for the phy clock to become valid in 100 ms */ 621 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 622 for (loop_count = 100000; loop_count != 0; loop_count--) { 623 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 624 break; 625 udelay(1); 626 } 627 if (!loop_count) 628 return -1; 629 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 630 631 return 0; 632 } 633 #else 634 static int init_ulpi_usb_controller(struct fdt_usb *config, 635 enum usb_init_type init) 636 { 637 printf("No code to set up ULPI controller, please enable" 638 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 639 return -1; 640 } 641 #endif 642 643 static void config_clock(const u32 timing[]) 644 { 645 clock_start_pll(CLOCK_ID_USB, 646 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 647 timing[PARAM_CPCON], timing[PARAM_LFCON]); 648 } 649 650 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 651 { 652 const char *phy, *mode; 653 654 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 655 mode = fdt_getprop(blob, node, "dr_mode", NULL); 656 if (mode) { 657 if (0 == strcmp(mode, "host")) 658 config->dr_mode = DR_MODE_HOST; 659 else if (0 == strcmp(mode, "peripheral")) 660 config->dr_mode = DR_MODE_DEVICE; 661 else if (0 == strcmp(mode, "otg")) 662 config->dr_mode = DR_MODE_OTG; 663 else { 664 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 665 mode); 666 return -FDT_ERR_NOTFOUND; 667 } 668 } else { 669 config->dr_mode = DR_MODE_HOST; 670 } 671 672 phy = fdt_getprop(blob, node, "phy_type", NULL); 673 config->utmi = phy && 0 == strcmp("utmi", phy); 674 config->ulpi = phy && 0 == strcmp("ulpi", phy); 675 config->enabled = fdtdec_get_is_enabled(blob, node); 676 config->has_legacy_mode = fdtdec_get_bool(blob, node, 677 "nvidia,has-legacy-mode"); 678 if (config->has_legacy_mode) 679 port_addr_clear_csc = (unsigned long)config->reg; 680 config->periph_id = clock_decode_periph_id(blob, node); 681 if (config->periph_id == PERIPH_ID_NONE) { 682 debug("%s: Missing/invalid peripheral ID\n", __func__); 683 return -FDT_ERR_NOTFOUND; 684 } 685 gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, 686 &config->vbus_gpio, GPIOD_IS_OUT); 687 gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, 688 &config->phy_reset_gpio, GPIOD_IS_OUT); 689 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 690 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 691 config->enabled, config->has_legacy_mode, config->utmi, 692 config->ulpi, config->periph_id, 693 gpio_get_number(&config->vbus_gpio), 694 gpio_get_number(&config->phy_reset_gpio), config->dr_mode); 695 696 return 0; 697 } 698 699 /* 700 * process_usb_nodes() - Process a list of USB nodes, adding them to our list 701 * of USB ports. 702 * @blob: fdt blob 703 * @node_list: list of nodes to process (any <=0 are ignored) 704 * @count: number of nodes to process 705 * 706 * Return: 0 - ok, -1 - error 707 */ 708 static int process_usb_nodes(const void *blob, int node_list[], int count) 709 { 710 struct fdt_usb config; 711 int node, i; 712 int clk_done = 0; 713 714 port_count = 0; 715 for (i = 0; i < count; i++) { 716 if (port_count == USB_PORTS_MAX) { 717 printf("tegrausb: Cannot register more than %d ports\n", 718 USB_PORTS_MAX); 719 return -1; 720 } 721 722 debug("USB %d: ", i); 723 node = node_list[i]; 724 if (!node) 725 continue; 726 if (fdt_decode_usb(blob, node, &config)) { 727 debug("Cannot decode USB node %s\n", 728 fdt_get_name(blob, node, NULL)); 729 return -1; 730 } 731 if (!clk_done) { 732 config_clock(get_pll_timing()); 733 clk_done = 1; 734 } 735 config.initialized = 0; 736 737 /* add new USB port to the list of available ports */ 738 port[port_count++] = config; 739 } 740 741 return 0; 742 } 743 744 int usb_process_devicetree(const void *blob) 745 { 746 int node_list[USB_PORTS_MAX]; 747 int count, err = 0; 748 int i; 749 750 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { 751 controller = &fdt_usb_controllers[i]; 752 753 count = fdtdec_find_aliases_for_id(blob, "usb", 754 controller->compat, node_list, USB_PORTS_MAX); 755 if (count) { 756 err = process_usb_nodes(blob, node_list, count); 757 if (err) 758 printf("%s: Error processing USB node!\n", 759 __func__); 760 return err; 761 } 762 } 763 if (i == ARRAY_SIZE(fdt_usb_controllers)) 764 controller = NULL; 765 766 return err; 767 } 768 769 /** 770 * Start up the given port number (ports are numbered from 0 on each board). 771 * This returns values for the appropriate hccr and hcor addresses to use for 772 * USB EHCI operations. 773 * 774 * @param index port number to start 775 * @param hccr returns start address of EHCI HCCR registers 776 * @param hcor returns start address of EHCI HCOR registers 777 * @return 0 if ok, -1 on error (generally invalid port number) 778 */ 779 int ehci_hcd_init(int index, enum usb_init_type init, 780 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 781 { 782 struct fdt_usb *config; 783 struct usb_ctlr *usbctlr; 784 785 if (index >= port_count) 786 return -1; 787 788 config = &port[index]; 789 790 switch (init) { 791 case USB_INIT_HOST: 792 switch (config->dr_mode) { 793 case DR_MODE_HOST: 794 case DR_MODE_OTG: 795 break; 796 default: 797 printf("tegrausb: Invalid dr_mode %d for host mode\n", 798 config->dr_mode); 799 return -1; 800 } 801 break; 802 case USB_INIT_DEVICE: 803 if (config->periph_id != PERIPH_ID_USBD) { 804 printf("tegrausb: Device mode only supported on first USB controller\n"); 805 return -1; 806 } 807 if (!config->utmi) { 808 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 809 return -1; 810 } 811 switch (config->dr_mode) { 812 case DR_MODE_DEVICE: 813 case DR_MODE_OTG: 814 break; 815 default: 816 printf("tegrausb: Invalid dr_mode %d for device mode\n", 817 config->dr_mode); 818 return -1; 819 } 820 break; 821 default: 822 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 823 return -1; 824 } 825 826 /* skip init, if the port is already initialized */ 827 if (config->initialized && config->init_type == init) 828 goto success; 829 830 if (config->utmi && init_utmi_usb_controller(config, init)) { 831 printf("tegrausb: Cannot init port %d\n", index); 832 return -1; 833 } 834 835 if (config->ulpi && init_ulpi_usb_controller(config, init)) { 836 printf("tegrausb: Cannot init port %d\n", index); 837 return -1; 838 } 839 840 set_up_vbus(config, init); 841 842 config->initialized = 1; 843 config->init_type = init; 844 845 success: 846 usbctlr = config->reg; 847 *hccr = (struct ehci_hccr *)&usbctlr->cap_length; 848 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; 849 850 return 0; 851 } 852 853 /* 854 * Bring down the specified USB controller 855 */ 856 int ehci_hcd_stop(int index) 857 { 858 struct usb_ctlr *usbctlr; 859 860 usbctlr = port[index].reg; 861 862 /* Stop controller */ 863 writel(0, &usbctlr->usb_cmd); 864 udelay(1000); 865 866 /* Initiate controller reset */ 867 writel(2, &usbctlr->usb_cmd); 868 udelay(1000); 869 870 port[index].initialized = 0; 871 872 return 0; 873 } 874