1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2013 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/errno.h> 11 #include <asm/io.h> 12 #include <asm-generic/gpio.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch-tegra/usb.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <usb.h> 17 #include <usb/ulpi.h> 18 #include <libfdt.h> 19 #include <fdtdec.h> 20 21 #include "ehci.h" 22 23 #define USB1_ADDR_MASK 0xFFFF0000 24 25 #define HOSTPC1_DEVLC 0x84 26 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 27 28 #ifdef CONFIG_USB_ULPI 29 #ifndef CONFIG_USB_ULPI_VIEWPORT 30 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 31 define CONFIG_USB_ULPI_VIEWPORT" 32 #endif 33 #endif 34 35 enum { 36 USB_PORTS_MAX = 3, /* Maximum ports we allow */ 37 }; 38 39 /* Parameters we need for USB */ 40 enum { 41 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 42 PARAM_DIVM, /* PLL INPUT DIVIDER */ 43 PARAM_DIVP, /* POST DIVIDER (2^N) */ 44 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 45 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 46 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 47 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 48 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 49 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 50 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 51 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 52 53 PARAM_COUNT 54 }; 55 56 /* Possible port types (dual role mode) */ 57 enum dr_mode { 58 DR_MODE_NONE = 0, 59 DR_MODE_HOST, /* supports host operation */ 60 DR_MODE_DEVICE, /* supports device operation */ 61 DR_MODE_OTG, /* supports both */ 62 }; 63 64 enum usb_ctlr_type { 65 USB_CTLR_T20, 66 USB_CTLR_T30, 67 USB_CTLR_T114, 68 69 USB_CTRL_COUNT, 70 }; 71 72 /* Information about a USB port */ 73 struct fdt_usb { 74 struct usb_ctlr *reg; /* address of registers in physical memory */ 75 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 76 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 77 unsigned enabled:1; /* 1 to enable, 0 to disable */ 78 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 79 unsigned initialized:1; /* has this port already been initialized? */ 80 enum usb_ctlr_type type; 81 enum usb_init_type init_type; 82 enum dr_mode dr_mode; /* dual role mode */ 83 enum periph_id periph_id;/* peripheral id */ 84 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 85 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 86 }; 87 88 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ 89 static unsigned port_count; /* Number of available ports */ 90 /* Port that needs to clear CSC after Port Reset */ 91 static u32 port_addr_clear_csc; 92 93 /* 94 * This table has USB timing parameters for each Oscillator frequency we 95 * support. There are four sets of values: 96 * 97 * 1. PLLU configuration information (reference clock is osc/clk_m and 98 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 99 * 100 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 101 * ---------------------------------------------------------------------- 102 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 103 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 104 * Filter frequency (MHz) 1 4.8 6 2 105 * CPCON 1100b 0011b 1100b 1100b 106 * LFCON0 0 0 0 0 107 * 108 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 109 * 110 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 111 * --------------------------------------------------------------------------- 112 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 113 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 114 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 115 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 116 * 117 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 118 * SessEnd. Each of these signals have their own debouncer and for each of 119 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 120 * BIAS_DEBOUNCE_B). 121 * 122 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 123 * 0xffff -> No debouncing at all 124 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 125 * 126 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 127 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 128 * 129 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 130 * values, so we can keep those to default. 131 * 132 * 4. The 20 microsecond delay after bias cell operation. 133 */ 134 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 135 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 136 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 137 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 138 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 139 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 140 }; 141 142 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 143 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 144 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 145 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 146 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 147 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 148 }; 149 150 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 151 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 152 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 153 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 154 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 155 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 156 }; 157 158 /* UTMIP Idle Wait Delay */ 159 static const u8 utmip_idle_wait_delay = 17; 160 161 /* UTMIP Elastic limit */ 162 static const u8 utmip_elastic_limit = 16; 163 164 /* UTMIP High Speed Sync Start Delay */ 165 static const u8 utmip_hs_sync_start_delay = 9; 166 167 struct fdt_usb_controller { 168 int compat; 169 /* flag to determine whether controller supports hostpc register */ 170 u32 has_hostpc:1; 171 const unsigned *pll_parameter; 172 }; 173 174 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { 175 { 176 .compat = COMPAT_NVIDIA_TEGRA20_USB, 177 .has_hostpc = 0, 178 .pll_parameter = (const unsigned *)T20_usb_pll, 179 }, 180 { 181 .compat = COMPAT_NVIDIA_TEGRA30_USB, 182 .has_hostpc = 1, 183 .pll_parameter = (const unsigned *)T30_usb_pll, 184 }, 185 { 186 .compat = COMPAT_NVIDIA_TEGRA114_USB, 187 .has_hostpc = 1, 188 .pll_parameter = (const unsigned *)T114_usb_pll, 189 }, 190 }; 191 192 /* 193 * A known hardware issue where Connect Status Change bit of PORTSC register 194 * of USB1 controller will be set after Port Reset. 195 * We have to clear it in order for later device enumeration to proceed. 196 */ 197 static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl, 198 uint32_t *status_reg, uint32_t *reg) 199 { 200 struct fdt_usb *config = ctrl->priv; 201 struct fdt_usb_controller *controller; 202 203 controller = &fdt_usb_controllers[config->type]; 204 mdelay(50); 205 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 206 if (controller->has_hostpc) 207 *reg |= EHCI_PS_PE; 208 209 if (((unsigned long)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc) 210 return; 211 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 212 if (ehci_readl(status_reg) & EHCI_PS_CSC) 213 *reg |= EHCI_PS_CSC; 214 } 215 216 static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl) 217 { 218 struct fdt_usb *config = ctrl->priv; 219 struct usb_ctlr *usbctlr; 220 uint32_t tmp; 221 222 usbctlr = config->reg; 223 224 tmp = ehci_readl(&usbctlr->usb_mode); 225 tmp |= USBMODE_CM_HC; 226 ehci_writel(&usbctlr->usb_mode, tmp); 227 } 228 229 static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 230 { 231 struct fdt_usb *config = ctrl->priv; 232 struct fdt_usb_controller *controller; 233 uint32_t tmp; 234 uint32_t *reg_ptr; 235 236 controller = &fdt_usb_controllers[config->type]; 237 if (controller->has_hostpc) { 238 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 239 HOSTPC1_DEVLC); 240 tmp = ehci_readl(reg_ptr); 241 return HOSTPC1_PSPD(tmp); 242 } else 243 return PORTSC_PSPD(reg); 244 } 245 246 /* Set up VBUS for host/device mode */ 247 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 248 { 249 /* 250 * If we are an OTG port initializing in host mode, 251 * check if remote host is driving VBus and bail out in this case. 252 */ 253 if (init == USB_INIT_HOST && 254 config->dr_mode == DR_MODE_OTG && 255 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 256 printf("tegrausb: VBUS input active; not enabling as host\n"); 257 return; 258 } 259 260 if (dm_gpio_is_valid(&config->vbus_gpio)) { 261 int vbus_value; 262 263 vbus_value = (init == USB_INIT_HOST); 264 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 265 266 debug("set_up_vbus: GPIO %d %d\n", 267 gpio_get_number(&config->vbus_gpio), vbus_value); 268 } 269 } 270 271 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) 272 { 273 /* Reset the USB controller with 2us delay */ 274 reset_periph(config->periph_id, 2); 275 276 /* 277 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 278 * base address 279 */ 280 if (config->has_legacy_mode) 281 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 282 283 /* Put UTMIP1/3 in reset */ 284 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 285 286 /* Enable the UTMIP PHY */ 287 if (config->utmi) 288 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 289 } 290 291 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) 292 { 293 const unsigned *timing; 294 295 timing = controller->pll_parameter + 296 clock_get_osc_freq() * PARAM_COUNT; 297 298 return timing; 299 } 300 301 /* select the PHY to use with a USB controller */ 302 static void init_phy_mux(struct fdt_usb *config, uint pts, 303 enum usb_init_type init) 304 { 305 struct usb_ctlr *usbctlr = config->reg; 306 307 #if defined(CONFIG_TEGRA20) 308 if (config->periph_id == PERIPH_ID_USBD) { 309 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 310 pts << PTS1_SHIFT); 311 clrbits_le32(&usbctlr->port_sc1, STS1); 312 } else { 313 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 314 pts << PTS_SHIFT); 315 clrbits_le32(&usbctlr->port_sc1, STS); 316 } 317 #else 318 /* Set to Host mode (if applicable) after Controller Reset was done */ 319 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 320 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 321 /* 322 * Select PHY interface after setting host mode. 323 * For device mode, the ordering requirement is not an issue, since 324 * only the first USB controller supports device mode, and that USB 325 * controller can only talk to a UTMI PHY, so the PHY selection is 326 * already made at reset time, so this write is a no-op. 327 */ 328 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 329 pts << PTS_SHIFT); 330 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 331 #endif 332 } 333 334 /* set up the UTMI USB controller with the parameters provided */ 335 static int init_utmi_usb_controller(struct fdt_usb *config, 336 enum usb_init_type init) 337 { 338 struct fdt_usb_controller *controller; 339 u32 b_sess_valid_mask, val; 340 int loop_count; 341 const unsigned *timing; 342 struct usb_ctlr *usbctlr = config->reg; 343 struct clk_rst_ctlr *clkrst; 344 struct usb_ctlr *usb1ctlr; 345 346 clock_enable(config->periph_id); 347 348 /* Reset the usb controller */ 349 usbf_reset_controller(config, usbctlr); 350 351 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 352 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 353 354 /* Follow the crystal clock disable by >100ns delay */ 355 udelay(1); 356 357 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 358 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 359 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 360 361 /* 362 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 363 * mux must be switched to actually use a_sess_vld threshold. 364 */ 365 if (config->dr_mode == DR_MODE_OTG && 366 dm_gpio_is_valid(&config->vbus_gpio)) 367 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 368 VBUS_SENSE_CTL_MASK, 369 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 370 371 controller = &fdt_usb_controllers[config->type]; 372 debug("controller=%p, type=%d\n", controller, config->type); 373 374 /* 375 * PLL Delay CONFIGURATION settings. The following parameters control 376 * the bring up of the plls. 377 */ 378 timing = get_pll_timing(controller); 379 380 if (!controller->has_hostpc) { 381 val = readl(&usbctlr->utmip_misc_cfg1); 382 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 383 timing[PARAM_STABLE_COUNT] << 384 UTMIP_PLLU_STABLE_COUNT_SHIFT); 385 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 386 timing[PARAM_ACTIVE_DELAY_COUNT] << 387 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 388 writel(val, &usbctlr->utmip_misc_cfg1); 389 390 /* Set PLL enable delay count and crystal frequency count */ 391 val = readl(&usbctlr->utmip_pll_cfg1); 392 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 393 timing[PARAM_ENABLE_DELAY_COUNT] << 394 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 395 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 396 timing[PARAM_XTAL_FREQ_COUNT] << 397 UTMIP_XTAL_FREQ_COUNT_SHIFT); 398 writel(val, &usbctlr->utmip_pll_cfg1); 399 } else { 400 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 401 402 val = readl(&clkrst->crc_utmip_pll_cfg2); 403 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 404 timing[PARAM_STABLE_COUNT] << 405 UTMIP_PLLU_STABLE_COUNT_SHIFT); 406 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 407 timing[PARAM_ACTIVE_DELAY_COUNT] << 408 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 409 writel(val, &clkrst->crc_utmip_pll_cfg2); 410 411 /* Set PLL enable delay count and crystal frequency count */ 412 val = readl(&clkrst->crc_utmip_pll_cfg1); 413 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 414 timing[PARAM_ENABLE_DELAY_COUNT] << 415 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 416 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 417 timing[PARAM_XTAL_FREQ_COUNT] << 418 UTMIP_XTAL_FREQ_COUNT_SHIFT); 419 writel(val, &clkrst->crc_utmip_pll_cfg1); 420 421 /* Disable Power Down state for PLL */ 422 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 423 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 424 PLL_ACTIVE_POWERDOWN); 425 426 /* Recommended PHY settings for EYE diagram */ 427 val = readl(&usbctlr->utmip_xcvr_cfg0); 428 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 429 0x4 << UTMIP_XCVR_SETUP_SHIFT); 430 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 431 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 432 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 433 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 434 writel(val, &usbctlr->utmip_xcvr_cfg0); 435 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 436 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 437 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 438 439 /* Some registers can be controlled from USB1 only. */ 440 if (config->periph_id != PERIPH_ID_USBD) { 441 clock_enable(PERIPH_ID_USBD); 442 /* Disable Reset if in Reset state */ 443 reset_set_enable(PERIPH_ID_USBD, 0); 444 } 445 usb1ctlr = (struct usb_ctlr *) 446 ((unsigned long)config->reg & USB1_ADDR_MASK); 447 val = readl(&usb1ctlr->utmip_bias_cfg0); 448 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 449 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 450 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 451 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 452 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 453 writel(val, &usb1ctlr->utmip_bias_cfg0); 454 455 /* Miscellaneous setting mentioned in Programming Guide */ 456 clrbits_le32(&usbctlr->utmip_misc_cfg0, 457 UTMIP_SUSPEND_EXIT_ON_EDGE); 458 } 459 460 /* Setting the tracking length time */ 461 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 462 UTMIP_BIAS_PDTRK_COUNT_MASK, 463 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 464 465 /* Program debounce time for VBUS to become valid */ 466 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 467 UTMIP_DEBOUNCE_CFG0_MASK, 468 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 469 470 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 471 472 /* Disable battery charge enabling bit */ 473 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 474 475 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 476 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 477 478 /* 479 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 480 * Setting these fields, together with default values of the 481 * other fields, results in programming the registers below as 482 * follows: 483 * UTMIP_HSRX_CFG0 = 0x9168c000 484 * UTMIP_HSRX_CFG1 = 0x13 485 */ 486 487 /* Set PLL enable delay count and Crystal frequency count */ 488 val = readl(&usbctlr->utmip_hsrx_cfg0); 489 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 490 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 491 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 492 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 493 writel(val, &usbctlr->utmip_hsrx_cfg0); 494 495 /* Configure the UTMIP_HS_SYNC_START_DLY */ 496 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 497 UTMIP_HS_SYNC_START_DLY_MASK, 498 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 499 500 /* Preceed the crystal clock disable by >100ns delay. */ 501 udelay(1); 502 503 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 504 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 505 506 if (controller->has_hostpc) { 507 if (config->periph_id == PERIPH_ID_USBD) 508 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 509 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 510 if (config->periph_id == PERIPH_ID_USB2) 511 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 512 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 513 if (config->periph_id == PERIPH_ID_USB3) 514 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 515 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 516 } 517 /* Finished the per-controller init. */ 518 519 /* De-assert UTMIP_RESET to bring out of reset. */ 520 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 521 522 /* Wait for the phy clock to become valid in 100 ms */ 523 for (loop_count = 100000; loop_count != 0; loop_count--) { 524 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 525 break; 526 udelay(1); 527 } 528 if (!loop_count) 529 return -1; 530 531 /* Disable ICUSB FS/LS transceiver */ 532 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 533 534 /* Select UTMI parallel interface */ 535 init_phy_mux(config, PTS_UTMI, init); 536 537 /* Deassert power down state */ 538 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 539 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 540 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 541 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 542 543 if (controller->has_hostpc) { 544 /* 545 * BIAS Pad Power Down is common among all 3 USB 546 * controllers and can be controlled from USB1 only. 547 */ 548 usb1ctlr = (struct usb_ctlr *) 549 ((unsigned long)config->reg & USB1_ADDR_MASK); 550 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 551 udelay(25); 552 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 553 UTMIP_FORCE_PDTRK_POWERDOWN); 554 } 555 return 0; 556 } 557 558 #ifdef CONFIG_USB_ULPI 559 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 560 #ifndef CONFIG_ULPI_REF_CLK 561 #define CONFIG_ULPI_REF_CLK 24000000 562 #endif 563 564 /* set up the ULPI USB controller with the parameters provided */ 565 static int init_ulpi_usb_controller(struct fdt_usb *config, 566 enum usb_init_type init) 567 { 568 u32 val; 569 int loop_count; 570 struct ulpi_viewport ulpi_vp; 571 struct usb_ctlr *usbctlr = config->reg; 572 573 /* set up ULPI reference clock on pllp_out4 */ 574 clock_enable(PERIPH_ID_DEV2_OUT); 575 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 576 577 /* reset ULPI phy */ 578 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 579 dm_gpio_set_value(&config->phy_reset_gpio, 0); 580 mdelay(5); 581 dm_gpio_set_value(&config->phy_reset_gpio, 1); 582 } 583 584 /* Reset the usb controller */ 585 clock_enable(config->periph_id); 586 usbf_reset_controller(config, usbctlr); 587 588 /* enable pinmux bypass */ 589 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 590 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 591 592 /* Select ULPI parallel interface */ 593 init_phy_mux(config, PTS_ULPI, init); 594 595 /* enable ULPI transceiver */ 596 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 597 598 /* configure ULPI transceiver timings */ 599 val = 0; 600 writel(val, &usbctlr->ulpi_timing_ctrl_1); 601 602 val |= ULPI_DATA_TRIMMER_SEL(4); 603 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 604 val |= ULPI_DIR_TRIMMER_SEL(4); 605 writel(val, &usbctlr->ulpi_timing_ctrl_1); 606 udelay(10); 607 608 val |= ULPI_DATA_TRIMMER_LOAD; 609 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 610 val |= ULPI_DIR_TRIMMER_LOAD; 611 writel(val, &usbctlr->ulpi_timing_ctrl_1); 612 613 /* set up phy for host operation with external vbus supply */ 614 ulpi_vp.port_num = 0; 615 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 616 617 if (ulpi_init(&ulpi_vp)) { 618 printf("Tegra ULPI viewport init failed\n"); 619 return -1; 620 } 621 622 ulpi_set_vbus(&ulpi_vp, 1, 1); 623 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 624 625 /* enable wakeup events */ 626 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 627 628 /* Enable and wait for the phy clock to become valid in 100 ms */ 629 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 630 for (loop_count = 100000; loop_count != 0; loop_count--) { 631 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 632 break; 633 udelay(1); 634 } 635 if (!loop_count) 636 return -1; 637 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 638 639 return 0; 640 } 641 #else 642 static int init_ulpi_usb_controller(struct fdt_usb *config, 643 enum usb_init_type init) 644 { 645 printf("No code to set up ULPI controller, please enable" 646 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 647 return -1; 648 } 649 #endif 650 651 static void config_clock(const u32 timing[]) 652 { 653 clock_start_pll(CLOCK_ID_USB, 654 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 655 timing[PARAM_CPCON], timing[PARAM_LFCON]); 656 } 657 658 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 659 { 660 const char *phy, *mode; 661 662 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 663 mode = fdt_getprop(blob, node, "dr_mode", NULL); 664 if (mode) { 665 if (0 == strcmp(mode, "host")) 666 config->dr_mode = DR_MODE_HOST; 667 else if (0 == strcmp(mode, "peripheral")) 668 config->dr_mode = DR_MODE_DEVICE; 669 else if (0 == strcmp(mode, "otg")) 670 config->dr_mode = DR_MODE_OTG; 671 else { 672 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 673 mode); 674 return -FDT_ERR_NOTFOUND; 675 } 676 } else { 677 config->dr_mode = DR_MODE_HOST; 678 } 679 680 phy = fdt_getprop(blob, node, "phy_type", NULL); 681 config->utmi = phy && 0 == strcmp("utmi", phy); 682 config->ulpi = phy && 0 == strcmp("ulpi", phy); 683 config->enabled = fdtdec_get_is_enabled(blob, node); 684 config->has_legacy_mode = fdtdec_get_bool(blob, node, 685 "nvidia,has-legacy-mode"); 686 if (config->has_legacy_mode) 687 port_addr_clear_csc = (unsigned long)config->reg; 688 config->periph_id = clock_decode_periph_id(blob, node); 689 if (config->periph_id == PERIPH_ID_NONE) { 690 debug("%s: Missing/invalid peripheral ID\n", __func__); 691 return -FDT_ERR_NOTFOUND; 692 } 693 gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, 694 &config->vbus_gpio, GPIOD_IS_OUT); 695 gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, 696 &config->phy_reset_gpio, GPIOD_IS_OUT); 697 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 698 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 699 config->enabled, config->has_legacy_mode, config->utmi, 700 config->ulpi, config->periph_id, 701 gpio_get_number(&config->vbus_gpio), 702 gpio_get_number(&config->phy_reset_gpio), config->dr_mode); 703 704 return 0; 705 } 706 707 static const struct ehci_ops tegra_ehci_ops = { 708 .set_usb_mode = tegra_ehci_set_usbmode, 709 .get_port_speed = tegra_ehci_get_port_speed, 710 .powerup_fixup = tegra_ehci_powerup_fixup, 711 }; 712 713 /* 714 * process_usb_nodes() - Process a list of USB nodes, adding them to our list 715 * of USB ports. 716 * @blob: fdt blob 717 * @node_list: list of nodes to process (any <=0 are ignored) 718 * @count: number of nodes to process 719 * @id: controller type (enum usb_ctlr_type) 720 * 721 * Return: 0 - ok, -1 - error 722 */ 723 static int process_usb_nodes(const void *blob, int node_list[], int count, 724 enum usb_ctlr_type id) 725 { 726 struct fdt_usb config; 727 int node, i; 728 int clk_done = 0; 729 730 port_count = 0; 731 for (i = 0; i < count; i++) { 732 if (port_count == USB_PORTS_MAX) { 733 printf("tegrausb: Cannot register more than %d ports\n", 734 USB_PORTS_MAX); 735 return -1; 736 } 737 738 debug("USB %d: ", i); 739 node = node_list[i]; 740 if (!node) 741 continue; 742 if (fdt_decode_usb(blob, node, &config)) { 743 debug("Cannot decode USB node %s\n", 744 fdt_get_name(blob, node, NULL)); 745 return -1; 746 } 747 if (!clk_done) { 748 config_clock(get_pll_timing( 749 &fdt_usb_controllers[id])); 750 clk_done = 1; 751 } 752 config.type = id; 753 config.initialized = 0; 754 755 /* add new USB port to the list of available ports */ 756 port[port_count++] = config; 757 } 758 759 return 0; 760 } 761 762 int usb_process_devicetree(const void *blob) 763 { 764 int node_list[USB_PORTS_MAX]; 765 int count, err = 0; 766 int i; 767 768 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { 769 count = fdtdec_find_aliases_for_id(blob, "usb", 770 fdt_usb_controllers[i].compat, node_list, 771 USB_PORTS_MAX); 772 if (count) { 773 err = process_usb_nodes(blob, node_list, count, i); 774 if (err) 775 printf("%s: Error processing USB node!\n", 776 __func__); 777 return err; 778 } 779 } 780 781 return err; 782 } 783 784 /** 785 * Start up the given port number (ports are numbered from 0 on each board). 786 * This returns values for the appropriate hccr and hcor addresses to use for 787 * USB EHCI operations. 788 * 789 * @param index port number to start 790 * @param hccr returns start address of EHCI HCCR registers 791 * @param hcor returns start address of EHCI HCOR registers 792 * @return 0 if ok, -1 on error (generally invalid port number) 793 */ 794 int ehci_hcd_init(int index, enum usb_init_type init, 795 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 796 { 797 struct fdt_usb *config; 798 struct usb_ctlr *usbctlr; 799 800 if (index >= port_count) 801 return -1; 802 803 config = &port[index]; 804 ehci_set_controller_priv(index, config, &tegra_ehci_ops); 805 806 switch (init) { 807 case USB_INIT_HOST: 808 switch (config->dr_mode) { 809 case DR_MODE_HOST: 810 case DR_MODE_OTG: 811 break; 812 default: 813 printf("tegrausb: Invalid dr_mode %d for host mode\n", 814 config->dr_mode); 815 return -1; 816 } 817 break; 818 case USB_INIT_DEVICE: 819 if (config->periph_id != PERIPH_ID_USBD) { 820 printf("tegrausb: Device mode only supported on first USB controller\n"); 821 return -1; 822 } 823 if (!config->utmi) { 824 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 825 return -1; 826 } 827 switch (config->dr_mode) { 828 case DR_MODE_DEVICE: 829 case DR_MODE_OTG: 830 break; 831 default: 832 printf("tegrausb: Invalid dr_mode %d for device mode\n", 833 config->dr_mode); 834 return -1; 835 } 836 break; 837 default: 838 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 839 return -1; 840 } 841 842 /* skip init, if the port is already initialized */ 843 if (config->initialized && config->init_type == init) 844 goto success; 845 846 if (config->utmi && init_utmi_usb_controller(config, init)) { 847 printf("tegrausb: Cannot init port %d\n", index); 848 return -1; 849 } 850 851 if (config->ulpi && init_ulpi_usb_controller(config, init)) { 852 printf("tegrausb: Cannot init port %d\n", index); 853 return -1; 854 } 855 856 set_up_vbus(config, init); 857 858 config->initialized = 1; 859 config->init_type = init; 860 861 success: 862 usbctlr = config->reg; 863 *hccr = (struct ehci_hccr *)&usbctlr->cap_length; 864 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; 865 866 return 0; 867 } 868 869 /* 870 * Bring down the specified USB controller 871 */ 872 int ehci_hcd_stop(int index) 873 { 874 struct usb_ctlr *usbctlr; 875 876 usbctlr = port[index].reg; 877 878 /* Stop controller */ 879 writel(0, &usbctlr->usb_cmd); 880 udelay(1000); 881 882 /* Initiate controller reset */ 883 writel(2, &usbctlr->usb_cmd); 884 udelay(1000); 885 886 port[index].initialized = 0; 887 888 return 0; 889 } 890