1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2013 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/errno.h> 11 #include <asm/io.h> 12 #include <asm-generic/gpio.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch-tegra/usb.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <usb.h> 17 #include <usb/ulpi.h> 18 #include <libfdt.h> 19 #include <fdtdec.h> 20 21 #include "ehci.h" 22 23 #define USB1_ADDR_MASK 0xFFFF0000 24 25 #define HOSTPC1_DEVLC 0x84 26 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 27 28 #ifdef CONFIG_USB_ULPI 29 #ifndef CONFIG_USB_ULPI_VIEWPORT 30 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 31 define CONFIG_USB_ULPI_VIEWPORT" 32 #endif 33 #endif 34 35 enum { 36 USB_PORTS_MAX = 3, /* Maximum ports we allow */ 37 }; 38 39 /* Parameters we need for USB */ 40 enum { 41 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 42 PARAM_DIVM, /* PLL INPUT DIVIDER */ 43 PARAM_DIVP, /* POST DIVIDER (2^N) */ 44 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 45 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 46 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 47 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 48 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 49 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 50 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 51 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 52 53 PARAM_COUNT 54 }; 55 56 /* Possible port types (dual role mode) */ 57 enum dr_mode { 58 DR_MODE_NONE = 0, 59 DR_MODE_HOST, /* supports host operation */ 60 DR_MODE_DEVICE, /* supports device operation */ 61 DR_MODE_OTG, /* supports both */ 62 }; 63 64 enum usb_ctlr_type { 65 USB_CTLR_T20, 66 USB_CTLR_T30, 67 USB_CTLR_T114, 68 69 USB_CTRL_COUNT, 70 }; 71 72 /* Information about a USB port */ 73 struct fdt_usb { 74 struct usb_ctlr *reg; /* address of registers in physical memory */ 75 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 76 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 77 unsigned enabled:1; /* 1 to enable, 0 to disable */ 78 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 79 unsigned initialized:1; /* has this port already been initialized? */ 80 enum usb_ctlr_type type; 81 enum usb_init_type init_type; 82 enum dr_mode dr_mode; /* dual role mode */ 83 enum periph_id periph_id;/* peripheral id */ 84 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 85 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 86 }; 87 88 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ 89 static unsigned port_count; /* Number of available ports */ 90 /* Port that needs to clear CSC after Port Reset */ 91 static u32 port_addr_clear_csc; 92 93 /* 94 * This table has USB timing parameters for each Oscillator frequency we 95 * support. There are four sets of values: 96 * 97 * 1. PLLU configuration information (reference clock is osc/clk_m and 98 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 99 * 100 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 101 * ---------------------------------------------------------------------- 102 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 103 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 104 * Filter frequency (MHz) 1 4.8 6 2 105 * CPCON 1100b 0011b 1100b 1100b 106 * LFCON0 0 0 0 0 107 * 108 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 109 * 110 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 111 * --------------------------------------------------------------------------- 112 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 113 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 114 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 115 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 116 * 117 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 118 * SessEnd. Each of these signals have their own debouncer and for each of 119 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 120 * BIAS_DEBOUNCE_B). 121 * 122 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 123 * 0xffff -> No debouncing at all 124 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 125 * 126 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 127 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 128 * 129 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 130 * values, so we can keep those to default. 131 * 132 * 4. The 20 microsecond delay after bias cell operation. 133 */ 134 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 135 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 136 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 137 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 138 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 139 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 140 }; 141 142 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 143 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 144 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 145 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 146 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 147 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 148 }; 149 150 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 151 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 152 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 153 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 154 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 155 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 156 }; 157 158 /* UTMIP Idle Wait Delay */ 159 static const u8 utmip_idle_wait_delay = 17; 160 161 /* UTMIP Elastic limit */ 162 static const u8 utmip_elastic_limit = 16; 163 164 /* UTMIP High Speed Sync Start Delay */ 165 static const u8 utmip_hs_sync_start_delay = 9; 166 167 struct fdt_usb_controller { 168 int compat; 169 /* flag to determine whether controller supports hostpc register */ 170 u32 has_hostpc:1; 171 const unsigned *pll_parameter; 172 }; 173 174 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { 175 { 176 .compat = COMPAT_NVIDIA_TEGRA20_USB, 177 .has_hostpc = 0, 178 .pll_parameter = (const unsigned *)T20_usb_pll, 179 }, 180 { 181 .compat = COMPAT_NVIDIA_TEGRA30_USB, 182 .has_hostpc = 1, 183 .pll_parameter = (const unsigned *)T30_usb_pll, 184 }, 185 { 186 .compat = COMPAT_NVIDIA_TEGRA114_USB, 187 .has_hostpc = 1, 188 .pll_parameter = (const unsigned *)T114_usb_pll, 189 }, 190 }; 191 192 /* 193 * A known hardware issue where Connect Status Change bit of PORTSC register 194 * of USB1 controller will be set after Port Reset. 195 * We have to clear it in order for later device enumeration to proceed. 196 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup 197 * in "ehci-hcd.c". 198 */ 199 void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, 200 uint32_t *reg) 201 { 202 struct fdt_usb *config = ctrl->priv; 203 struct fdt_usb_controller *controller; 204 205 controller = &fdt_usb_controllers[config->type]; 206 mdelay(50); 207 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 208 if (controller->has_hostpc) 209 *reg |= EHCI_PS_PE; 210 211 if (((unsigned long)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc) 212 return; 213 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 214 if (ehci_readl(status_reg) & EHCI_PS_CSC) 215 *reg |= EHCI_PS_CSC; 216 } 217 218 /* 219 * This ehci_set_usbmode overrides the weak function ehci_set_usbmode 220 * in "ehci-hcd.c". 221 */ 222 void ehci_set_usbmode(int index) 223 { 224 struct fdt_usb *config; 225 struct usb_ctlr *usbctlr; 226 uint32_t tmp; 227 228 config = &port[index]; 229 usbctlr = config->reg; 230 231 tmp = ehci_readl(&usbctlr->usb_mode); 232 tmp |= USBMODE_CM_HC; 233 ehci_writel(&usbctlr->usb_mode, tmp); 234 } 235 236 /* 237 * This ehci_get_port_speed overrides the weak function ehci_get_port_speed 238 * in "ehci-hcd.c". 239 */ 240 int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 241 { 242 struct fdt_usb *config = ctrl->priv; 243 struct fdt_usb_controller *controller; 244 uint32_t tmp; 245 uint32_t *reg_ptr; 246 247 controller = &fdt_usb_controllers[config->type]; 248 if (controller->has_hostpc) { 249 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 250 HOSTPC1_DEVLC); 251 tmp = ehci_readl(reg_ptr); 252 return HOSTPC1_PSPD(tmp); 253 } else 254 return PORTSC_PSPD(reg); 255 } 256 257 /* Set up VBUS for host/device mode */ 258 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 259 { 260 /* 261 * If we are an OTG port initializing in host mode, 262 * check if remote host is driving VBus and bail out in this case. 263 */ 264 if (init == USB_INIT_HOST && 265 config->dr_mode == DR_MODE_OTG && 266 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 267 printf("tegrausb: VBUS input active; not enabling as host\n"); 268 return; 269 } 270 271 if (dm_gpio_is_valid(&config->vbus_gpio)) { 272 int vbus_value; 273 274 vbus_value = (init == USB_INIT_HOST); 275 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 276 277 debug("set_up_vbus: GPIO %d %d\n", 278 gpio_get_number(&config->vbus_gpio), vbus_value); 279 } 280 } 281 282 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) 283 { 284 /* Reset the USB controller with 2us delay */ 285 reset_periph(config->periph_id, 2); 286 287 /* 288 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 289 * base address 290 */ 291 if (config->has_legacy_mode) 292 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 293 294 /* Put UTMIP1/3 in reset */ 295 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 296 297 /* Enable the UTMIP PHY */ 298 if (config->utmi) 299 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 300 } 301 302 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) 303 { 304 const unsigned *timing; 305 306 timing = controller->pll_parameter + 307 clock_get_osc_freq() * PARAM_COUNT; 308 309 return timing; 310 } 311 312 /* select the PHY to use with a USB controller */ 313 static void init_phy_mux(struct fdt_usb *config, uint pts, 314 enum usb_init_type init) 315 { 316 struct usb_ctlr *usbctlr = config->reg; 317 318 #if defined(CONFIG_TEGRA20) 319 if (config->periph_id == PERIPH_ID_USBD) { 320 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 321 pts << PTS1_SHIFT); 322 clrbits_le32(&usbctlr->port_sc1, STS1); 323 } else { 324 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 325 pts << PTS_SHIFT); 326 clrbits_le32(&usbctlr->port_sc1, STS); 327 } 328 #else 329 /* Set to Host mode (if applicable) after Controller Reset was done */ 330 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 331 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 332 /* 333 * Select PHY interface after setting host mode. 334 * For device mode, the ordering requirement is not an issue, since 335 * only the first USB controller supports device mode, and that USB 336 * controller can only talk to a UTMI PHY, so the PHY selection is 337 * already made at reset time, so this write is a no-op. 338 */ 339 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 340 pts << PTS_SHIFT); 341 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 342 #endif 343 } 344 345 /* set up the UTMI USB controller with the parameters provided */ 346 static int init_utmi_usb_controller(struct fdt_usb *config, 347 enum usb_init_type init) 348 { 349 struct fdt_usb_controller *controller; 350 u32 b_sess_valid_mask, val; 351 int loop_count; 352 const unsigned *timing; 353 struct usb_ctlr *usbctlr = config->reg; 354 struct clk_rst_ctlr *clkrst; 355 struct usb_ctlr *usb1ctlr; 356 357 clock_enable(config->periph_id); 358 359 /* Reset the usb controller */ 360 usbf_reset_controller(config, usbctlr); 361 362 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 363 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 364 365 /* Follow the crystal clock disable by >100ns delay */ 366 udelay(1); 367 368 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 369 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 370 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 371 372 /* 373 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 374 * mux must be switched to actually use a_sess_vld threshold. 375 */ 376 if (config->dr_mode == DR_MODE_OTG && 377 dm_gpio_is_valid(&config->vbus_gpio)) 378 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 379 VBUS_SENSE_CTL_MASK, 380 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 381 382 controller = &fdt_usb_controllers[config->type]; 383 debug("controller=%p, type=%d\n", controller, config->type); 384 385 /* 386 * PLL Delay CONFIGURATION settings. The following parameters control 387 * the bring up of the plls. 388 */ 389 timing = get_pll_timing(controller); 390 391 if (!controller->has_hostpc) { 392 val = readl(&usbctlr->utmip_misc_cfg1); 393 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 394 timing[PARAM_STABLE_COUNT] << 395 UTMIP_PLLU_STABLE_COUNT_SHIFT); 396 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 397 timing[PARAM_ACTIVE_DELAY_COUNT] << 398 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 399 writel(val, &usbctlr->utmip_misc_cfg1); 400 401 /* Set PLL enable delay count and crystal frequency count */ 402 val = readl(&usbctlr->utmip_pll_cfg1); 403 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 404 timing[PARAM_ENABLE_DELAY_COUNT] << 405 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 406 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 407 timing[PARAM_XTAL_FREQ_COUNT] << 408 UTMIP_XTAL_FREQ_COUNT_SHIFT); 409 writel(val, &usbctlr->utmip_pll_cfg1); 410 } else { 411 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 412 413 val = readl(&clkrst->crc_utmip_pll_cfg2); 414 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 415 timing[PARAM_STABLE_COUNT] << 416 UTMIP_PLLU_STABLE_COUNT_SHIFT); 417 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 418 timing[PARAM_ACTIVE_DELAY_COUNT] << 419 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 420 writel(val, &clkrst->crc_utmip_pll_cfg2); 421 422 /* Set PLL enable delay count and crystal frequency count */ 423 val = readl(&clkrst->crc_utmip_pll_cfg1); 424 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 425 timing[PARAM_ENABLE_DELAY_COUNT] << 426 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 427 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 428 timing[PARAM_XTAL_FREQ_COUNT] << 429 UTMIP_XTAL_FREQ_COUNT_SHIFT); 430 writel(val, &clkrst->crc_utmip_pll_cfg1); 431 432 /* Disable Power Down state for PLL */ 433 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 434 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 435 PLL_ACTIVE_POWERDOWN); 436 437 /* Recommended PHY settings for EYE diagram */ 438 val = readl(&usbctlr->utmip_xcvr_cfg0); 439 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 440 0x4 << UTMIP_XCVR_SETUP_SHIFT); 441 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 442 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 443 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 444 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 445 writel(val, &usbctlr->utmip_xcvr_cfg0); 446 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 447 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 448 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 449 450 /* Some registers can be controlled from USB1 only. */ 451 if (config->periph_id != PERIPH_ID_USBD) { 452 clock_enable(PERIPH_ID_USBD); 453 /* Disable Reset if in Reset state */ 454 reset_set_enable(PERIPH_ID_USBD, 0); 455 } 456 usb1ctlr = (struct usb_ctlr *) 457 ((unsigned long)config->reg & USB1_ADDR_MASK); 458 val = readl(&usb1ctlr->utmip_bias_cfg0); 459 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 460 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 461 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 462 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 463 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 464 writel(val, &usb1ctlr->utmip_bias_cfg0); 465 466 /* Miscellaneous setting mentioned in Programming Guide */ 467 clrbits_le32(&usbctlr->utmip_misc_cfg0, 468 UTMIP_SUSPEND_EXIT_ON_EDGE); 469 } 470 471 /* Setting the tracking length time */ 472 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 473 UTMIP_BIAS_PDTRK_COUNT_MASK, 474 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 475 476 /* Program debounce time for VBUS to become valid */ 477 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 478 UTMIP_DEBOUNCE_CFG0_MASK, 479 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 480 481 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 482 483 /* Disable battery charge enabling bit */ 484 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 485 486 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 487 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 488 489 /* 490 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 491 * Setting these fields, together with default values of the 492 * other fields, results in programming the registers below as 493 * follows: 494 * UTMIP_HSRX_CFG0 = 0x9168c000 495 * UTMIP_HSRX_CFG1 = 0x13 496 */ 497 498 /* Set PLL enable delay count and Crystal frequency count */ 499 val = readl(&usbctlr->utmip_hsrx_cfg0); 500 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 501 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 502 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 503 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 504 writel(val, &usbctlr->utmip_hsrx_cfg0); 505 506 /* Configure the UTMIP_HS_SYNC_START_DLY */ 507 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 508 UTMIP_HS_SYNC_START_DLY_MASK, 509 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 510 511 /* Preceed the crystal clock disable by >100ns delay. */ 512 udelay(1); 513 514 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 515 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 516 517 if (controller->has_hostpc) { 518 if (config->periph_id == PERIPH_ID_USBD) 519 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 520 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 521 if (config->periph_id == PERIPH_ID_USB2) 522 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 523 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 524 if (config->periph_id == PERIPH_ID_USB3) 525 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 526 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 527 } 528 /* Finished the per-controller init. */ 529 530 /* De-assert UTMIP_RESET to bring out of reset. */ 531 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 532 533 /* Wait for the phy clock to become valid in 100 ms */ 534 for (loop_count = 100000; loop_count != 0; loop_count--) { 535 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 536 break; 537 udelay(1); 538 } 539 if (!loop_count) 540 return -1; 541 542 /* Disable ICUSB FS/LS transceiver */ 543 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 544 545 /* Select UTMI parallel interface */ 546 init_phy_mux(config, PTS_UTMI, init); 547 548 /* Deassert power down state */ 549 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 550 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 551 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 552 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 553 554 if (controller->has_hostpc) { 555 /* 556 * BIAS Pad Power Down is common among all 3 USB 557 * controllers and can be controlled from USB1 only. 558 */ 559 usb1ctlr = (struct usb_ctlr *) 560 ((unsigned long)config->reg & USB1_ADDR_MASK); 561 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 562 udelay(25); 563 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 564 UTMIP_FORCE_PDTRK_POWERDOWN); 565 } 566 return 0; 567 } 568 569 #ifdef CONFIG_USB_ULPI 570 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 571 #ifndef CONFIG_ULPI_REF_CLK 572 #define CONFIG_ULPI_REF_CLK 24000000 573 #endif 574 575 /* set up the ULPI USB controller with the parameters provided */ 576 static int init_ulpi_usb_controller(struct fdt_usb *config, 577 enum usb_init_type init) 578 { 579 u32 val; 580 int loop_count; 581 struct ulpi_viewport ulpi_vp; 582 struct usb_ctlr *usbctlr = config->reg; 583 584 /* set up ULPI reference clock on pllp_out4 */ 585 clock_enable(PERIPH_ID_DEV2_OUT); 586 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 587 588 /* reset ULPI phy */ 589 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 590 dm_gpio_set_value(&config->phy_reset_gpio, 0); 591 mdelay(5); 592 dm_gpio_set_value(&config->phy_reset_gpio, 1); 593 } 594 595 /* Reset the usb controller */ 596 clock_enable(config->periph_id); 597 usbf_reset_controller(config, usbctlr); 598 599 /* enable pinmux bypass */ 600 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 601 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 602 603 /* Select ULPI parallel interface */ 604 init_phy_mux(config, PTS_ULPI, init); 605 606 /* enable ULPI transceiver */ 607 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 608 609 /* configure ULPI transceiver timings */ 610 val = 0; 611 writel(val, &usbctlr->ulpi_timing_ctrl_1); 612 613 val |= ULPI_DATA_TRIMMER_SEL(4); 614 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 615 val |= ULPI_DIR_TRIMMER_SEL(4); 616 writel(val, &usbctlr->ulpi_timing_ctrl_1); 617 udelay(10); 618 619 val |= ULPI_DATA_TRIMMER_LOAD; 620 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 621 val |= ULPI_DIR_TRIMMER_LOAD; 622 writel(val, &usbctlr->ulpi_timing_ctrl_1); 623 624 /* set up phy for host operation with external vbus supply */ 625 ulpi_vp.port_num = 0; 626 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 627 628 if (ulpi_init(&ulpi_vp)) { 629 printf("Tegra ULPI viewport init failed\n"); 630 return -1; 631 } 632 633 ulpi_set_vbus(&ulpi_vp, 1, 1); 634 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 635 636 /* enable wakeup events */ 637 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 638 639 /* Enable and wait for the phy clock to become valid in 100 ms */ 640 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 641 for (loop_count = 100000; loop_count != 0; loop_count--) { 642 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 643 break; 644 udelay(1); 645 } 646 if (!loop_count) 647 return -1; 648 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 649 650 return 0; 651 } 652 #else 653 static int init_ulpi_usb_controller(struct fdt_usb *config, 654 enum usb_init_type init) 655 { 656 printf("No code to set up ULPI controller, please enable" 657 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 658 return -1; 659 } 660 #endif 661 662 static void config_clock(const u32 timing[]) 663 { 664 clock_start_pll(CLOCK_ID_USB, 665 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 666 timing[PARAM_CPCON], timing[PARAM_LFCON]); 667 } 668 669 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 670 { 671 const char *phy, *mode; 672 673 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 674 mode = fdt_getprop(blob, node, "dr_mode", NULL); 675 if (mode) { 676 if (0 == strcmp(mode, "host")) 677 config->dr_mode = DR_MODE_HOST; 678 else if (0 == strcmp(mode, "peripheral")) 679 config->dr_mode = DR_MODE_DEVICE; 680 else if (0 == strcmp(mode, "otg")) 681 config->dr_mode = DR_MODE_OTG; 682 else { 683 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 684 mode); 685 return -FDT_ERR_NOTFOUND; 686 } 687 } else { 688 config->dr_mode = DR_MODE_HOST; 689 } 690 691 phy = fdt_getprop(blob, node, "phy_type", NULL); 692 config->utmi = phy && 0 == strcmp("utmi", phy); 693 config->ulpi = phy && 0 == strcmp("ulpi", phy); 694 config->enabled = fdtdec_get_is_enabled(blob, node); 695 config->has_legacy_mode = fdtdec_get_bool(blob, node, 696 "nvidia,has-legacy-mode"); 697 if (config->has_legacy_mode) 698 port_addr_clear_csc = (unsigned long)config->reg; 699 config->periph_id = clock_decode_periph_id(blob, node); 700 if (config->periph_id == PERIPH_ID_NONE) { 701 debug("%s: Missing/invalid peripheral ID\n", __func__); 702 return -FDT_ERR_NOTFOUND; 703 } 704 gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, 705 &config->vbus_gpio, GPIOD_IS_OUT); 706 gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, 707 &config->phy_reset_gpio, GPIOD_IS_OUT); 708 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 709 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 710 config->enabled, config->has_legacy_mode, config->utmi, 711 config->ulpi, config->periph_id, 712 gpio_get_number(&config->vbus_gpio), 713 gpio_get_number(&config->phy_reset_gpio), config->dr_mode); 714 715 return 0; 716 } 717 718 /* 719 * process_usb_nodes() - Process a list of USB nodes, adding them to our list 720 * of USB ports. 721 * @blob: fdt blob 722 * @node_list: list of nodes to process (any <=0 are ignored) 723 * @count: number of nodes to process 724 * @id: controller type (enum usb_ctlr_type) 725 * 726 * Return: 0 - ok, -1 - error 727 */ 728 static int process_usb_nodes(const void *blob, int node_list[], int count, 729 enum usb_ctlr_type id) 730 { 731 struct fdt_usb config; 732 int node, i; 733 int clk_done = 0; 734 735 port_count = 0; 736 for (i = 0; i < count; i++) { 737 if (port_count == USB_PORTS_MAX) { 738 printf("tegrausb: Cannot register more than %d ports\n", 739 USB_PORTS_MAX); 740 return -1; 741 } 742 743 debug("USB %d: ", i); 744 node = node_list[i]; 745 if (!node) 746 continue; 747 if (fdt_decode_usb(blob, node, &config)) { 748 debug("Cannot decode USB node %s\n", 749 fdt_get_name(blob, node, NULL)); 750 return -1; 751 } 752 if (!clk_done) { 753 config_clock(get_pll_timing( 754 &fdt_usb_controllers[id])); 755 clk_done = 1; 756 } 757 config.type = id; 758 config.initialized = 0; 759 760 /* add new USB port to the list of available ports */ 761 port[port_count++] = config; 762 } 763 764 return 0; 765 } 766 767 int usb_process_devicetree(const void *blob) 768 { 769 int node_list[USB_PORTS_MAX]; 770 int count, err = 0; 771 int i; 772 773 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { 774 count = fdtdec_find_aliases_for_id(blob, "usb", 775 fdt_usb_controllers[i].compat, node_list, 776 USB_PORTS_MAX); 777 if (count) { 778 err = process_usb_nodes(blob, node_list, count, i); 779 if (err) 780 printf("%s: Error processing USB node!\n", 781 __func__); 782 return err; 783 } 784 } 785 786 return err; 787 } 788 789 /** 790 * Start up the given port number (ports are numbered from 0 on each board). 791 * This returns values for the appropriate hccr and hcor addresses to use for 792 * USB EHCI operations. 793 * 794 * @param index port number to start 795 * @param hccr returns start address of EHCI HCCR registers 796 * @param hcor returns start address of EHCI HCOR registers 797 * @return 0 if ok, -1 on error (generally invalid port number) 798 */ 799 int ehci_hcd_init(int index, enum usb_init_type init, 800 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 801 { 802 struct fdt_usb *config; 803 struct usb_ctlr *usbctlr; 804 805 if (index >= port_count) 806 return -1; 807 808 config = &port[index]; 809 ehci_set_controller_priv(index, config); 810 811 switch (init) { 812 case USB_INIT_HOST: 813 switch (config->dr_mode) { 814 case DR_MODE_HOST: 815 case DR_MODE_OTG: 816 break; 817 default: 818 printf("tegrausb: Invalid dr_mode %d for host mode\n", 819 config->dr_mode); 820 return -1; 821 } 822 break; 823 case USB_INIT_DEVICE: 824 if (config->periph_id != PERIPH_ID_USBD) { 825 printf("tegrausb: Device mode only supported on first USB controller\n"); 826 return -1; 827 } 828 if (!config->utmi) { 829 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 830 return -1; 831 } 832 switch (config->dr_mode) { 833 case DR_MODE_DEVICE: 834 case DR_MODE_OTG: 835 break; 836 default: 837 printf("tegrausb: Invalid dr_mode %d for device mode\n", 838 config->dr_mode); 839 return -1; 840 } 841 break; 842 default: 843 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 844 return -1; 845 } 846 847 /* skip init, if the port is already initialized */ 848 if (config->initialized && config->init_type == init) 849 goto success; 850 851 if (config->utmi && init_utmi_usb_controller(config, init)) { 852 printf("tegrausb: Cannot init port %d\n", index); 853 return -1; 854 } 855 856 if (config->ulpi && init_ulpi_usb_controller(config, init)) { 857 printf("tegrausb: Cannot init port %d\n", index); 858 return -1; 859 } 860 861 set_up_vbus(config, init); 862 863 config->initialized = 1; 864 config->init_type = init; 865 866 success: 867 usbctlr = config->reg; 868 *hccr = (struct ehci_hccr *)&usbctlr->cap_length; 869 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; 870 871 return 0; 872 } 873 874 /* 875 * Bring down the specified USB controller 876 */ 877 int ehci_hcd_stop(int index) 878 { 879 struct usb_ctlr *usbctlr; 880 881 usbctlr = port[index].reg; 882 883 /* Stop controller */ 884 writel(0, &usbctlr->usb_cmd); 885 udelay(1000); 886 887 /* Initiate controller reset */ 888 writel(2, &usbctlr->usb_cmd); 889 udelay(1000); 890 891 port[index].initialized = 0; 892 893 return 0; 894 } 895