1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2013 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/errno.h> 11 #include <asm/io.h> 12 #include <asm-generic/gpio.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch-tegra/usb.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <usb.h> 17 #include <usb/ulpi.h> 18 #include <libfdt.h> 19 #include <fdtdec.h> 20 21 #include "ehci.h" 22 23 #define USB1_ADDR_MASK 0xFFFF0000 24 25 #define HOSTPC1_DEVLC 0x84 26 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 27 28 #ifdef CONFIG_USB_ULPI 29 #ifndef CONFIG_USB_ULPI_VIEWPORT 30 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 31 define CONFIG_USB_ULPI_VIEWPORT" 32 #endif 33 #endif 34 35 enum { 36 USB_PORTS_MAX = 3, /* Maximum ports we allow */ 37 }; 38 39 /* Parameters we need for USB */ 40 enum { 41 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 42 PARAM_DIVM, /* PLL INPUT DIVIDER */ 43 PARAM_DIVP, /* POST DIVIDER (2^N) */ 44 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 45 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 46 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 47 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 48 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 49 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 50 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 51 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 52 53 PARAM_COUNT 54 }; 55 56 /* Possible port types (dual role mode) */ 57 enum dr_mode { 58 DR_MODE_NONE = 0, 59 DR_MODE_HOST, /* supports host operation */ 60 DR_MODE_DEVICE, /* supports device operation */ 61 DR_MODE_OTG, /* supports both */ 62 }; 63 64 enum usb_ctlr_type { 65 USB_CTLR_T20, 66 USB_CTLR_T30, 67 USB_CTLR_T114, 68 69 USB_CTRL_COUNT, 70 }; 71 72 /* Information about a USB port */ 73 struct fdt_usb { 74 struct usb_ctlr *reg; /* address of registers in physical memory */ 75 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 76 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 77 unsigned enabled:1; /* 1 to enable, 0 to disable */ 78 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 79 unsigned initialized:1; /* has this port already been initialized? */ 80 enum usb_ctlr_type type; 81 enum usb_init_type init_type; 82 enum dr_mode dr_mode; /* dual role mode */ 83 enum periph_id periph_id;/* peripheral id */ 84 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 85 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 86 }; 87 88 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ 89 static unsigned port_count; /* Number of available ports */ 90 /* Port that needs to clear CSC after Port Reset */ 91 static u32 port_addr_clear_csc; 92 93 /* 94 * This table has USB timing parameters for each Oscillator frequency we 95 * support. There are four sets of values: 96 * 97 * 1. PLLU configuration information (reference clock is osc/clk_m and 98 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 99 * 100 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 101 * ---------------------------------------------------------------------- 102 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 103 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 104 * Filter frequency (MHz) 1 4.8 6 2 105 * CPCON 1100b 0011b 1100b 1100b 106 * LFCON0 0 0 0 0 107 * 108 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 109 * 110 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 111 * --------------------------------------------------------------------------- 112 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 113 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 114 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 115 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 116 * 117 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 118 * SessEnd. Each of these signals have their own debouncer and for each of 119 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 120 * BIAS_DEBOUNCE_B). 121 * 122 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 123 * 0xffff -> No debouncing at all 124 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 125 * 126 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 127 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 128 * 129 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 130 * values, so we can keep those to default. 131 * 132 * 4. The 20 microsecond delay after bias cell operation. 133 */ 134 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 135 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 136 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 137 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 138 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 139 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 140 }; 141 142 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 143 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 144 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 145 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 146 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 147 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 148 }; 149 150 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 151 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 152 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 153 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 154 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 155 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 156 }; 157 158 /* UTMIP Idle Wait Delay */ 159 static const u8 utmip_idle_wait_delay = 17; 160 161 /* UTMIP Elastic limit */ 162 static const u8 utmip_elastic_limit = 16; 163 164 /* UTMIP High Speed Sync Start Delay */ 165 static const u8 utmip_hs_sync_start_delay = 9; 166 167 struct fdt_usb_controller { 168 int compat; 169 /* flag to determine whether controller supports hostpc register */ 170 u32 has_hostpc:1; 171 const unsigned *pll_parameter; 172 }; 173 174 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { 175 { 176 .compat = COMPAT_NVIDIA_TEGRA20_USB, 177 .has_hostpc = 0, 178 .pll_parameter = (const unsigned *)T20_usb_pll, 179 }, 180 { 181 .compat = COMPAT_NVIDIA_TEGRA30_USB, 182 .has_hostpc = 1, 183 .pll_parameter = (const unsigned *)T30_usb_pll, 184 }, 185 { 186 .compat = COMPAT_NVIDIA_TEGRA114_USB, 187 .has_hostpc = 1, 188 .pll_parameter = (const unsigned *)T114_usb_pll, 189 }, 190 }; 191 192 static struct fdt_usb_controller *controller; 193 194 /* 195 * A known hardware issue where Connect Status Change bit of PORTSC register 196 * of USB1 controller will be set after Port Reset. 197 * We have to clear it in order for later device enumeration to proceed. 198 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup 199 * in "ehci-hcd.c". 200 */ 201 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 202 { 203 mdelay(50); 204 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 205 if (controller->has_hostpc) 206 *reg |= EHCI_PS_PE; 207 208 if (((unsigned long)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc) 209 return; 210 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 211 if (ehci_readl(status_reg) & EHCI_PS_CSC) 212 *reg |= EHCI_PS_CSC; 213 } 214 215 /* 216 * This ehci_set_usbmode overrides the weak function ehci_set_usbmode 217 * in "ehci-hcd.c". 218 */ 219 void ehci_set_usbmode(int index) 220 { 221 struct fdt_usb *config; 222 struct usb_ctlr *usbctlr; 223 uint32_t tmp; 224 225 config = &port[index]; 226 usbctlr = config->reg; 227 228 tmp = ehci_readl(&usbctlr->usb_mode); 229 tmp |= USBMODE_CM_HC; 230 ehci_writel(&usbctlr->usb_mode, tmp); 231 } 232 233 /* 234 * This ehci_get_port_speed overrides the weak function ehci_get_port_speed 235 * in "ehci-hcd.c". 236 */ 237 int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 238 { 239 uint32_t tmp; 240 uint32_t *reg_ptr; 241 242 if (controller->has_hostpc) { 243 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 244 HOSTPC1_DEVLC); 245 tmp = ehci_readl(reg_ptr); 246 return HOSTPC1_PSPD(tmp); 247 } else 248 return PORTSC_PSPD(reg); 249 } 250 251 /* Set up VBUS for host/device mode */ 252 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 253 { 254 /* 255 * If we are an OTG port initializing in host mode, 256 * check if remote host is driving VBus and bail out in this case. 257 */ 258 if (init == USB_INIT_HOST && 259 config->dr_mode == DR_MODE_OTG && 260 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 261 printf("tegrausb: VBUS input active; not enabling as host\n"); 262 return; 263 } 264 265 if (dm_gpio_is_valid(&config->vbus_gpio)) { 266 int vbus_value; 267 268 vbus_value = (init == USB_INIT_HOST); 269 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 270 271 debug("set_up_vbus: GPIO %d %d\n", 272 gpio_get_number(&config->vbus_gpio), vbus_value); 273 } 274 } 275 276 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) 277 { 278 /* Reset the USB controller with 2us delay */ 279 reset_periph(config->periph_id, 2); 280 281 /* 282 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 283 * base address 284 */ 285 if (config->has_legacy_mode) 286 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 287 288 /* Put UTMIP1/3 in reset */ 289 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 290 291 /* Enable the UTMIP PHY */ 292 if (config->utmi) 293 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 294 } 295 296 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) 297 { 298 const unsigned *timing; 299 300 timing = controller->pll_parameter + 301 clock_get_osc_freq() * PARAM_COUNT; 302 303 return timing; 304 } 305 306 /* select the PHY to use with a USB controller */ 307 static void init_phy_mux(struct fdt_usb *config, uint pts, 308 enum usb_init_type init) 309 { 310 struct usb_ctlr *usbctlr = config->reg; 311 312 #if defined(CONFIG_TEGRA20) 313 if (config->periph_id == PERIPH_ID_USBD) { 314 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 315 pts << PTS1_SHIFT); 316 clrbits_le32(&usbctlr->port_sc1, STS1); 317 } else { 318 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 319 pts << PTS_SHIFT); 320 clrbits_le32(&usbctlr->port_sc1, STS); 321 } 322 #else 323 /* Set to Host mode (if applicable) after Controller Reset was done */ 324 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 325 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 326 /* 327 * Select PHY interface after setting host mode. 328 * For device mode, the ordering requirement is not an issue, since 329 * only the first USB controller supports device mode, and that USB 330 * controller can only talk to a UTMI PHY, so the PHY selection is 331 * already made at reset time, so this write is a no-op. 332 */ 333 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 334 pts << PTS_SHIFT); 335 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 336 #endif 337 } 338 339 /* set up the UTMI USB controller with the parameters provided */ 340 static int init_utmi_usb_controller(struct fdt_usb *config, 341 enum usb_init_type init) 342 { 343 struct fdt_usb_controller *controller; 344 u32 b_sess_valid_mask, val; 345 int loop_count; 346 const unsigned *timing; 347 struct usb_ctlr *usbctlr = config->reg; 348 struct clk_rst_ctlr *clkrst; 349 struct usb_ctlr *usb1ctlr; 350 351 clock_enable(config->periph_id); 352 353 /* Reset the usb controller */ 354 usbf_reset_controller(config, usbctlr); 355 356 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 357 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 358 359 /* Follow the crystal clock disable by >100ns delay */ 360 udelay(1); 361 362 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 363 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 364 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 365 366 /* 367 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 368 * mux must be switched to actually use a_sess_vld threshold. 369 */ 370 if (config->dr_mode == DR_MODE_OTG && 371 dm_gpio_is_valid(&config->vbus_gpio)) 372 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 373 VBUS_SENSE_CTL_MASK, 374 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 375 376 controller = &fdt_usb_controllers[config->type]; 377 debug("controller=%p, type=%d\n", controller, config->type); 378 379 /* 380 * PLL Delay CONFIGURATION settings. The following parameters control 381 * the bring up of the plls. 382 */ 383 timing = get_pll_timing(controller); 384 385 if (!controller->has_hostpc) { 386 val = readl(&usbctlr->utmip_misc_cfg1); 387 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 388 timing[PARAM_STABLE_COUNT] << 389 UTMIP_PLLU_STABLE_COUNT_SHIFT); 390 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 391 timing[PARAM_ACTIVE_DELAY_COUNT] << 392 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 393 writel(val, &usbctlr->utmip_misc_cfg1); 394 395 /* Set PLL enable delay count and crystal frequency count */ 396 val = readl(&usbctlr->utmip_pll_cfg1); 397 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 398 timing[PARAM_ENABLE_DELAY_COUNT] << 399 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 400 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 401 timing[PARAM_XTAL_FREQ_COUNT] << 402 UTMIP_XTAL_FREQ_COUNT_SHIFT); 403 writel(val, &usbctlr->utmip_pll_cfg1); 404 } else { 405 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 406 407 val = readl(&clkrst->crc_utmip_pll_cfg2); 408 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 409 timing[PARAM_STABLE_COUNT] << 410 UTMIP_PLLU_STABLE_COUNT_SHIFT); 411 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 412 timing[PARAM_ACTIVE_DELAY_COUNT] << 413 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 414 writel(val, &clkrst->crc_utmip_pll_cfg2); 415 416 /* Set PLL enable delay count and crystal frequency count */ 417 val = readl(&clkrst->crc_utmip_pll_cfg1); 418 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 419 timing[PARAM_ENABLE_DELAY_COUNT] << 420 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 421 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 422 timing[PARAM_XTAL_FREQ_COUNT] << 423 UTMIP_XTAL_FREQ_COUNT_SHIFT); 424 writel(val, &clkrst->crc_utmip_pll_cfg1); 425 426 /* Disable Power Down state for PLL */ 427 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 428 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 429 PLL_ACTIVE_POWERDOWN); 430 431 /* Recommended PHY settings for EYE diagram */ 432 val = readl(&usbctlr->utmip_xcvr_cfg0); 433 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 434 0x4 << UTMIP_XCVR_SETUP_SHIFT); 435 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 436 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 437 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 438 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 439 writel(val, &usbctlr->utmip_xcvr_cfg0); 440 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 441 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 442 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 443 444 /* Some registers can be controlled from USB1 only. */ 445 if (config->periph_id != PERIPH_ID_USBD) { 446 clock_enable(PERIPH_ID_USBD); 447 /* Disable Reset if in Reset state */ 448 reset_set_enable(PERIPH_ID_USBD, 0); 449 } 450 usb1ctlr = (struct usb_ctlr *) 451 ((unsigned long)config->reg & USB1_ADDR_MASK); 452 val = readl(&usb1ctlr->utmip_bias_cfg0); 453 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 454 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 455 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 456 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 457 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 458 writel(val, &usb1ctlr->utmip_bias_cfg0); 459 460 /* Miscellaneous setting mentioned in Programming Guide */ 461 clrbits_le32(&usbctlr->utmip_misc_cfg0, 462 UTMIP_SUSPEND_EXIT_ON_EDGE); 463 } 464 465 /* Setting the tracking length time */ 466 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 467 UTMIP_BIAS_PDTRK_COUNT_MASK, 468 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 469 470 /* Program debounce time for VBUS to become valid */ 471 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 472 UTMIP_DEBOUNCE_CFG0_MASK, 473 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 474 475 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 476 477 /* Disable battery charge enabling bit */ 478 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 479 480 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 481 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 482 483 /* 484 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 485 * Setting these fields, together with default values of the 486 * other fields, results in programming the registers below as 487 * follows: 488 * UTMIP_HSRX_CFG0 = 0x9168c000 489 * UTMIP_HSRX_CFG1 = 0x13 490 */ 491 492 /* Set PLL enable delay count and Crystal frequency count */ 493 val = readl(&usbctlr->utmip_hsrx_cfg0); 494 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 495 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 496 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 497 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 498 writel(val, &usbctlr->utmip_hsrx_cfg0); 499 500 /* Configure the UTMIP_HS_SYNC_START_DLY */ 501 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 502 UTMIP_HS_SYNC_START_DLY_MASK, 503 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 504 505 /* Preceed the crystal clock disable by >100ns delay. */ 506 udelay(1); 507 508 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 509 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 510 511 if (controller->has_hostpc) { 512 if (config->periph_id == PERIPH_ID_USBD) 513 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 514 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 515 if (config->periph_id == PERIPH_ID_USB2) 516 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 517 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 518 if (config->periph_id == PERIPH_ID_USB3) 519 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 520 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 521 } 522 /* Finished the per-controller init. */ 523 524 /* De-assert UTMIP_RESET to bring out of reset. */ 525 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 526 527 /* Wait for the phy clock to become valid in 100 ms */ 528 for (loop_count = 100000; loop_count != 0; loop_count--) { 529 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 530 break; 531 udelay(1); 532 } 533 if (!loop_count) 534 return -1; 535 536 /* Disable ICUSB FS/LS transceiver */ 537 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 538 539 /* Select UTMI parallel interface */ 540 init_phy_mux(config, PTS_UTMI, init); 541 542 /* Deassert power down state */ 543 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 544 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 545 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 546 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 547 548 if (controller->has_hostpc) { 549 /* 550 * BIAS Pad Power Down is common among all 3 USB 551 * controllers and can be controlled from USB1 only. 552 */ 553 usb1ctlr = (struct usb_ctlr *) 554 ((unsigned long)config->reg & USB1_ADDR_MASK); 555 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 556 udelay(25); 557 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 558 UTMIP_FORCE_PDTRK_POWERDOWN); 559 } 560 return 0; 561 } 562 563 #ifdef CONFIG_USB_ULPI 564 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 565 #ifndef CONFIG_ULPI_REF_CLK 566 #define CONFIG_ULPI_REF_CLK 24000000 567 #endif 568 569 /* set up the ULPI USB controller with the parameters provided */ 570 static int init_ulpi_usb_controller(struct fdt_usb *config, 571 enum usb_init_type init) 572 { 573 u32 val; 574 int loop_count; 575 struct ulpi_viewport ulpi_vp; 576 struct usb_ctlr *usbctlr = config->reg; 577 578 /* set up ULPI reference clock on pllp_out4 */ 579 clock_enable(PERIPH_ID_DEV2_OUT); 580 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 581 582 /* reset ULPI phy */ 583 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 584 dm_gpio_set_value(&config->phy_reset_gpio, 0); 585 mdelay(5); 586 dm_gpio_set_value(&config->phy_reset_gpio, 1); 587 } 588 589 /* Reset the usb controller */ 590 clock_enable(config->periph_id); 591 usbf_reset_controller(config, usbctlr); 592 593 /* enable pinmux bypass */ 594 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 595 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 596 597 /* Select ULPI parallel interface */ 598 init_phy_mux(config, PTS_ULPI, init); 599 600 /* enable ULPI transceiver */ 601 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 602 603 /* configure ULPI transceiver timings */ 604 val = 0; 605 writel(val, &usbctlr->ulpi_timing_ctrl_1); 606 607 val |= ULPI_DATA_TRIMMER_SEL(4); 608 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 609 val |= ULPI_DIR_TRIMMER_SEL(4); 610 writel(val, &usbctlr->ulpi_timing_ctrl_1); 611 udelay(10); 612 613 val |= ULPI_DATA_TRIMMER_LOAD; 614 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 615 val |= ULPI_DIR_TRIMMER_LOAD; 616 writel(val, &usbctlr->ulpi_timing_ctrl_1); 617 618 /* set up phy for host operation with external vbus supply */ 619 ulpi_vp.port_num = 0; 620 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 621 622 if (ulpi_init(&ulpi_vp)) { 623 printf("Tegra ULPI viewport init failed\n"); 624 return -1; 625 } 626 627 ulpi_set_vbus(&ulpi_vp, 1, 1); 628 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 629 630 /* enable wakeup events */ 631 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 632 633 /* Enable and wait for the phy clock to become valid in 100 ms */ 634 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 635 for (loop_count = 100000; loop_count != 0; loop_count--) { 636 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 637 break; 638 udelay(1); 639 } 640 if (!loop_count) 641 return -1; 642 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 643 644 return 0; 645 } 646 #else 647 static int init_ulpi_usb_controller(struct fdt_usb *config, 648 enum usb_init_type init) 649 { 650 printf("No code to set up ULPI controller, please enable" 651 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 652 return -1; 653 } 654 #endif 655 656 static void config_clock(const u32 timing[]) 657 { 658 clock_start_pll(CLOCK_ID_USB, 659 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 660 timing[PARAM_CPCON], timing[PARAM_LFCON]); 661 } 662 663 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 664 { 665 const char *phy, *mode; 666 667 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 668 mode = fdt_getprop(blob, node, "dr_mode", NULL); 669 if (mode) { 670 if (0 == strcmp(mode, "host")) 671 config->dr_mode = DR_MODE_HOST; 672 else if (0 == strcmp(mode, "peripheral")) 673 config->dr_mode = DR_MODE_DEVICE; 674 else if (0 == strcmp(mode, "otg")) 675 config->dr_mode = DR_MODE_OTG; 676 else { 677 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 678 mode); 679 return -FDT_ERR_NOTFOUND; 680 } 681 } else { 682 config->dr_mode = DR_MODE_HOST; 683 } 684 685 phy = fdt_getprop(blob, node, "phy_type", NULL); 686 config->utmi = phy && 0 == strcmp("utmi", phy); 687 config->ulpi = phy && 0 == strcmp("ulpi", phy); 688 config->enabled = fdtdec_get_is_enabled(blob, node); 689 config->has_legacy_mode = fdtdec_get_bool(blob, node, 690 "nvidia,has-legacy-mode"); 691 if (config->has_legacy_mode) 692 port_addr_clear_csc = (unsigned long)config->reg; 693 config->periph_id = clock_decode_periph_id(blob, node); 694 if (config->periph_id == PERIPH_ID_NONE) { 695 debug("%s: Missing/invalid peripheral ID\n", __func__); 696 return -FDT_ERR_NOTFOUND; 697 } 698 gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, 699 &config->vbus_gpio, GPIOD_IS_OUT); 700 gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, 701 &config->phy_reset_gpio, GPIOD_IS_OUT); 702 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 703 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 704 config->enabled, config->has_legacy_mode, config->utmi, 705 config->ulpi, config->periph_id, 706 gpio_get_number(&config->vbus_gpio), 707 gpio_get_number(&config->phy_reset_gpio), config->dr_mode); 708 709 return 0; 710 } 711 712 /* 713 * process_usb_nodes() - Process a list of USB nodes, adding them to our list 714 * of USB ports. 715 * @blob: fdt blob 716 * @node_list: list of nodes to process (any <=0 are ignored) 717 * @count: number of nodes to process 718 * @id: controller type (enum usb_ctlr_type) 719 * 720 * Return: 0 - ok, -1 - error 721 */ 722 static int process_usb_nodes(const void *blob, int node_list[], int count, 723 enum usb_ctlr_type id) 724 { 725 struct fdt_usb config; 726 int node, i; 727 int clk_done = 0; 728 729 port_count = 0; 730 for (i = 0; i < count; i++) { 731 if (port_count == USB_PORTS_MAX) { 732 printf("tegrausb: Cannot register more than %d ports\n", 733 USB_PORTS_MAX); 734 return -1; 735 } 736 737 debug("USB %d: ", i); 738 node = node_list[i]; 739 if (!node) 740 continue; 741 if (fdt_decode_usb(blob, node, &config)) { 742 debug("Cannot decode USB node %s\n", 743 fdt_get_name(blob, node, NULL)); 744 return -1; 745 } 746 if (!clk_done) { 747 config_clock(get_pll_timing( 748 &fdt_usb_controllers[id])); 749 clk_done = 1; 750 } 751 config.type = id; 752 config.initialized = 0; 753 754 /* add new USB port to the list of available ports */ 755 port[port_count++] = config; 756 } 757 758 return 0; 759 } 760 761 int usb_process_devicetree(const void *blob) 762 { 763 int node_list[USB_PORTS_MAX]; 764 int count, err = 0; 765 int i; 766 767 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { 768 controller = &fdt_usb_controllers[i]; 769 770 count = fdtdec_find_aliases_for_id(blob, "usb", 771 controller->compat, node_list, USB_PORTS_MAX); 772 if (count) { 773 err = process_usb_nodes(blob, node_list, count, i); 774 if (err) 775 printf("%s: Error processing USB node!\n", 776 __func__); 777 return err; 778 } 779 } 780 if (i == ARRAY_SIZE(fdt_usb_controllers)) 781 controller = NULL; 782 783 return err; 784 } 785 786 /** 787 * Start up the given port number (ports are numbered from 0 on each board). 788 * This returns values for the appropriate hccr and hcor addresses to use for 789 * USB EHCI operations. 790 * 791 * @param index port number to start 792 * @param hccr returns start address of EHCI HCCR registers 793 * @param hcor returns start address of EHCI HCOR registers 794 * @return 0 if ok, -1 on error (generally invalid port number) 795 */ 796 int ehci_hcd_init(int index, enum usb_init_type init, 797 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 798 { 799 struct fdt_usb *config; 800 struct usb_ctlr *usbctlr; 801 802 if (index >= port_count) 803 return -1; 804 805 config = &port[index]; 806 ehci_set_controller_priv(index, config); 807 808 switch (init) { 809 case USB_INIT_HOST: 810 switch (config->dr_mode) { 811 case DR_MODE_HOST: 812 case DR_MODE_OTG: 813 break; 814 default: 815 printf("tegrausb: Invalid dr_mode %d for host mode\n", 816 config->dr_mode); 817 return -1; 818 } 819 break; 820 case USB_INIT_DEVICE: 821 if (config->periph_id != PERIPH_ID_USBD) { 822 printf("tegrausb: Device mode only supported on first USB controller\n"); 823 return -1; 824 } 825 if (!config->utmi) { 826 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 827 return -1; 828 } 829 switch (config->dr_mode) { 830 case DR_MODE_DEVICE: 831 case DR_MODE_OTG: 832 break; 833 default: 834 printf("tegrausb: Invalid dr_mode %d for device mode\n", 835 config->dr_mode); 836 return -1; 837 } 838 break; 839 default: 840 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 841 return -1; 842 } 843 844 /* skip init, if the port is already initialized */ 845 if (config->initialized && config->init_type == init) 846 goto success; 847 848 if (config->utmi && init_utmi_usb_controller(config, init)) { 849 printf("tegrausb: Cannot init port %d\n", index); 850 return -1; 851 } 852 853 if (config->ulpi && init_ulpi_usb_controller(config, init)) { 854 printf("tegrausb: Cannot init port %d\n", index); 855 return -1; 856 } 857 858 set_up_vbus(config, init); 859 860 config->initialized = 1; 861 config->init_type = init; 862 863 success: 864 usbctlr = config->reg; 865 *hccr = (struct ehci_hccr *)&usbctlr->cap_length; 866 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; 867 868 return 0; 869 } 870 871 /* 872 * Bring down the specified USB controller 873 */ 874 int ehci_hcd_stop(int index) 875 { 876 struct usb_ctlr *usbctlr; 877 878 usbctlr = port[index].reg; 879 880 /* Stop controller */ 881 writel(0, &usbctlr->usb_cmd); 882 udelay(1000); 883 884 /* Initiate controller reset */ 885 writel(2, &usbctlr->usb_cmd); 886 udelay(1000); 887 888 port[index].initialized = 0; 889 890 return 0; 891 } 892