1 /* 2 * Copyright (C) 2014 Roman Byshko 3 * 4 * Roman Byshko <rbyshko@gmail.com> 5 * 6 * Based on code from 7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <asm/arch/clock.h> 13 #include <asm/gpio.h> 14 #include <asm/io.h> 15 #include <common.h> 16 #include "ehci.h" 17 18 #define SUNXI_USB1_IO_BASE 0x01c14000 19 #define SUNXI_USB2_IO_BASE 0x01c1c000 20 21 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800 22 #define SUNXI_USB_CSR 0x01c13404 23 #define SUNXI_USB_PASSBY_EN 1 24 25 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) 26 #define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9) 27 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8) 28 #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0) 29 30 static struct sunxi_ehci_hcd { 31 struct usb_hcd *hcd; 32 int usb_rst_mask; 33 int ahb_clk_mask; 34 int gpio_vbus; 35 void *csr; 36 int irq; 37 int id; 38 } sunxi_echi_hcd[] = { 39 { 40 .usb_rst_mask = CCM_USB_CTRL_PHY1_RST, 41 .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, 42 .csr = (void *)SUNXI_USB_CSR, 43 .irq = 39, 44 .id = 1, 45 }, 46 #if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) 47 { 48 .usb_rst_mask = CCM_USB_CTRL_PHY2_RST, 49 .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1, 50 .csr = (void *)SUNXI_USB_CSR, 51 .irq = 40, 52 .id = 2, 53 } 54 #endif 55 }; 56 57 static int enabled_hcd_count; 58 59 static void *get_io_base(int hcd_id) 60 { 61 if (hcd_id == 1) 62 return (void *)SUNXI_USB1_IO_BASE; 63 else if (hcd_id == 2) 64 return (void *)SUNXI_USB2_IO_BASE; 65 else 66 return NULL; 67 } 68 69 static int get_vbus_gpio(int hcd_id) 70 { 71 switch (hcd_id) { 72 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN); 73 case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN); 74 } 75 return -1; 76 } 77 78 static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr, 79 int data, int len) 80 { 81 int j = 0, usbc_bit = 0; 82 void *dest = sunxi_ehci->csr; 83 84 usbc_bit = 1 << (sunxi_ehci->id * 2); 85 for (j = 0; j < len; j++) { 86 /* set the bit address to be written */ 87 clrbits_le32(dest, 0xff << 8); 88 setbits_le32(dest, (addr + j) << 8); 89 90 clrbits_le32(dest, usbc_bit); 91 /* set data bit */ 92 if (data & 0x1) 93 setbits_le32(dest, 1 << 7); 94 else 95 clrbits_le32(dest, 1 << 7); 96 97 setbits_le32(dest, usbc_bit); 98 99 clrbits_le32(dest, usbc_bit); 100 101 data >>= 1; 102 } 103 } 104 105 static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci) 106 { 107 /* The following comments are machine 108 * translated from Chinese, you have been warned! 109 */ 110 111 /* adjust PHY's magnitude and rate */ 112 usb_phy_write(sunxi_ehci, 0x20, 0x14, 5); 113 114 /* threshold adjustment disconnect */ 115 #ifdef CONFIG_MACH_SUN4I 116 usb_phy_write(sunxi_ehci, 0x2a, 3, 2); 117 #else 118 usb_phy_write(sunxi_ehci, 0x2a, 2, 2); 119 #endif 120 121 return; 122 } 123 124 static void sunxi_usb_passby(struct sunxi_ehci_hcd *sunxi_ehci, int enable) 125 { 126 unsigned long bits = 0; 127 void *addr = get_io_base(sunxi_ehci->id) + SUNXI_USB_PMU_IRQ_ENABLE; 128 129 bits = SUNXI_EHCI_AHB_ICHR8_EN | 130 SUNXI_EHCI_AHB_INCR4_BURST_EN | 131 SUNXI_EHCI_AHB_INCRX_ALIGN_EN | 132 SUNXI_EHCI_ULPI_BYPASS_EN; 133 134 if (enable) 135 setbits_le32(addr, bits); 136 else 137 clrbits_le32(addr, bits); 138 139 return; 140 } 141 142 static void sunxi_ehci_enable(struct sunxi_ehci_hcd *sunxi_ehci) 143 { 144 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 145 146 setbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask); 147 setbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask); 148 149 sunxi_usb_phy_init(sunxi_ehci); 150 151 sunxi_usb_passby(sunxi_ehci, SUNXI_USB_PASSBY_EN); 152 153 if (sunxi_ehci->gpio_vbus != -1) 154 gpio_direction_output(sunxi_ehci->gpio_vbus, 1); 155 } 156 157 static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci) 158 { 159 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 160 161 if (sunxi_ehci->gpio_vbus != -1) 162 gpio_direction_output(sunxi_ehci->gpio_vbus, 0); 163 164 sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN); 165 166 clrbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask); 167 clrbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask); 168 } 169 170 int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, 171 struct ehci_hcor **hcor) 172 { 173 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 174 struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index]; 175 int err; 176 177 sunxi_ehci->gpio_vbus = get_vbus_gpio(sunxi_ehci->id); 178 179 /* enable common PHY only once */ 180 if (index == 0) 181 setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); 182 183 if (sunxi_ehci->gpio_vbus != -1) { 184 err = gpio_request(sunxi_ehci->gpio_vbus, "ehci_vbus"); 185 if (err) 186 return err; 187 } 188 189 sunxi_ehci_enable(sunxi_ehci); 190 191 *hccr = get_io_base(sunxi_ehci->id); 192 193 *hcor = (struct ehci_hcor *)((uint32_t) *hccr 194 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 195 196 debug("sunxi-ehci: init hccr %x and hcor %x hc_length %d\n", 197 (uint32_t)*hccr, (uint32_t)*hcor, 198 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 199 200 enabled_hcd_count++; 201 202 return 0; 203 } 204 205 int ehci_hcd_stop(int index) 206 { 207 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 208 struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index]; 209 int err; 210 211 sunxi_ehci_disable(sunxi_ehci); 212 213 if (sunxi_ehci->gpio_vbus != -1) { 214 err = gpio_free(sunxi_ehci->gpio_vbus); 215 if (err) 216 return err; 217 } 218 219 /* disable common PHY only once, for the last enabled hcd */ 220 if (enabled_hcd_count == 1) 221 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); 222 223 enabled_hcd_count--; 224 225 return 0; 226 } 227