1 /* 2 * EHCI HCD (Host Controller Driver) for USB. 3 * 4 * Copyright (C) 2013,2014 Renesas Electronics Corporation 5 * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/ehci-rmobile.h> 13 #include "ehci.h" 14 15 #if defined(CONFIG_R8A7740) 16 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 17 0xC6700000 18 }; 19 #elif defined(CONFIG_R8A7790) 20 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 21 0xEE080000, /* USB0 (EHCI) */ 22 0xEE0A0000, /* USB1 */ 23 0xEE0C0000, /* USB2 */ 24 0xEE000000 /* USB3 (USB3.0 Host)*/ 25 }; 26 #elif defined(CONFIG_R8A7791) 27 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 28 0xEE080000, /* USB0 (EHCI) */ 29 0xEE0C0000, /* USB1 */ 30 0xEE000000 /* USB3 (USB3.0 Host)*/ 31 }; 32 #elif defined(CONFIG_R8A7794) 33 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 34 0xEE080000, /* USB0 (EHCI) */ 35 0xEE0C0000, /* USB1 */ 36 /* R8A7794 does not have USB 3.0. */ 37 }; 38 #else 39 #error rmobile EHCI USB driver not supported on this platform 40 #endif 41 42 int ehci_hcd_stop(int index) 43 { 44 int i; 45 u32 base; 46 struct ahbcom_pci_bridge *ahbcom_pci; 47 48 base = usb_base_address[index]; 49 ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); 50 writel(0, &ahbcom_pci->ahb_bus_ctr); 51 52 /* reset ehci */ 53 setbits_le32(base + EHCI_USBCMD, CMD_RESET); 54 for (i = 100; i > 0; i--) { 55 if (!(readl(base + EHCI_USBCMD) & CMD_RESET)) 56 break; 57 udelay(100); 58 } 59 60 if (!i) 61 printf("error : ehci(%d) reset failed.\n", index); 62 63 if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1)) 64 setbits_le32(SMSTPCR7, SMSTPCR703); 65 66 return 0; 67 } 68 69 int ehci_hcd_init(int index, enum usb_init_type init, 70 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 71 { 72 u32 base; 73 u32 phys_base; 74 struct rmobile_ehci_reg *rehci; 75 struct ahbcom_pci_bridge *ahbcom_pci; 76 struct ahbconf_pci_bridge *ahbconf_pci; 77 struct ahb_pciconf *ahb_pciconf_ohci; 78 struct ahb_pciconf *ahb_pciconf_ehci; 79 uint32_t cap_base; 80 81 base = usb_base_address[index]; 82 phys_base = base; 83 if (index == 0) 84 clrbits_le32(SMSTPCR7, SMSTPCR703); 85 86 rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET); 87 ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); 88 ahbconf_pci = 89 (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET); 90 ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET); 91 ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET); 92 93 /* Clock & Reset & Direct Power Down */ 94 clrsetbits_le32(&ahbcom_pci->usbctr, 95 (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB); 96 clrbits_le32(&ahbcom_pci->usbctr, PLL_RST); 97 98 /* AHB-PCI Bridge Communication Registers */ 99 writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); 100 writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, 101 &ahbcom_pci->pciahb_win1_ctr); 102 writel(0xf0000000 | PCIAHB_WIN_PREFETCH, 103 &ahbcom_pci->pciahb_win2_ctr); 104 writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr); 105 106 setbits_le32(&ahbcom_pci->pci_arbiter_ctr, 107 PCIBP_MODE | PCIREQ1 | PCIREQ0); 108 109 /* PCI Configuration Registers for AHBPCI */ 110 writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, 111 &ahbcom_pci->ahbpci_win1_ctr); 112 writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); 113 writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); 114 writel(0xf0000000, &ahbconf_pci->win2_basead); 115 writel(SERREN | PERREN | MASTEREN | MEMEN, 116 &ahbconf_pci->cmnd_sts); 117 118 /* PCI Configuration Registers for EHCI */ 119 writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr); 120 writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead); 121 writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead); 122 writel(SERREN | PERREN | MASTEREN | MEMEN, 123 &ahb_pciconf_ohci->cmnd_sts); 124 writel(SERREN | PERREN | MASTEREN | MEMEN, 125 &ahb_pciconf_ehci->cmnd_sts); 126 127 /* Enable PCI interrupt */ 128 setbits_le32(&ahbcom_pci->pci_int_enable, 129 USBH_PMEEN | USBH_INTBEN | USBH_INTAEN); 130 131 *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion); 132 cap_base = ehci_readl(&(*hccr)->cr_capbase); 133 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base)); 134 135 return 0; 136 } 137