1 /* 2 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems 3 * (C) Copyright 2004-2008 4 * Texas Instruments, <www.ti.com> 5 * 6 * Derived from Beagle Board code by 7 * Sunil Kumar <sunilsaini05@gmail.com> 8 * Shashi Ranjan <shashiranjanmca05@gmail.com> 9 * 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <usb.h> 16 #include <usb/ulpi.h> 17 #include <errno.h> 18 #include <asm/io.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/ehci.h> 21 #include <asm/ehci-omap.h> 22 23 #include "ehci.h" 24 25 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE; 26 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE; 27 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE; 28 29 static int omap_uhh_reset(void) 30 { 31 /* 32 * Soft resetting the UHH module causes instability issues on 33 * all OMAPs so we just avoid it. 34 * 35 * See OMAP36xx Errata 36 * i571: USB host EHCI may stall when entering smart-standby mode 37 * i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 38 * 39 * On OMAP4/5, soft-resetting the UHH module will put it into 40 * Smart-Idle mode and lead to a deadlock. 41 * 42 * On OMAP3, this doesn't seem to be the case but still instabilities 43 * are observed on beagle (3530 ES1.0) if soft-reset is used. 44 * e.g. NFS root failures with Linux kernel. 45 */ 46 return 0; 47 } 48 49 static int omap_ehci_tll_reset(void) 50 { 51 unsigned long init = get_timer(0); 52 53 /* perform TLL soft reset, and wait until reset is complete */ 54 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc); 55 56 /* Wait for TLL reset to complete */ 57 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE)) 58 if (get_timer(init) > CONFIG_SYS_HZ) { 59 debug("OMAP EHCI error: timeout resetting TLL\n"); 60 return -EL3RST; 61 } 62 63 return 0; 64 } 65 66 static void omap_usbhs_hsic_init(int port) 67 { 68 unsigned int reg; 69 70 /* Enable channels now */ 71 reg = readl(&usbtll->channel_conf + port); 72 73 setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI 74 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF 75 | OMAP_TLL_CHANNEL_CONF_DRVVBUS 76 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS 77 | OMAP_TLL_CHANNEL_CONF_CHANEN)); 78 79 writel(reg, &usbtll->channel_conf + port); 80 } 81 82 static void omap_ehci_soft_phy_reset(int port) 83 { 84 struct ulpi_viewport ulpi_vp; 85 86 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi; 87 ulpi_vp.port_num = port; 88 89 ulpi_reset(&ulpi_vp); 90 } 91 92 inline int __board_usb_init(void) 93 { 94 return 0; 95 } 96 int board_usb_init(void) __attribute__((weak, alias("__board_usb_init"))); 97 98 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \ 99 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \ 100 defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO) 101 /* controls PHY(s) reset signal(s) */ 102 static inline void omap_ehci_phy_reset(int on, int delay) 103 { 104 /* 105 * Refer ISSUE1: 106 * Hold the PHY in RESET for enough time till 107 * PHY is settled and ready 108 */ 109 if (delay && !on) 110 udelay(delay); 111 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 112 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset"); 113 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on); 114 #endif 115 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 116 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset"); 117 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on); 118 #endif 119 #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 120 gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset"); 121 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on); 122 #endif 123 124 /* Hold the PHY in RESET for enough time till DIR is high */ 125 /* Refer: ISSUE1 */ 126 if (delay && on) 127 udelay(delay); 128 } 129 #else 130 #define omap_ehci_phy_reset(on, delay) do {} while (0) 131 #endif 132 133 /* Reset is needed otherwise the kernel-driver will throw an error. */ 134 int omap_ehci_hcd_stop(void) 135 { 136 debug("Resetting OMAP EHCI\n"); 137 omap_ehci_phy_reset(1, 0); 138 139 if (omap_uhh_reset() < 0) 140 return -1; 141 142 if (omap_ehci_tll_reset() < 0) 143 return -1; 144 145 return 0; 146 } 147 148 /* 149 * Initialize the OMAP EHCI controller and PHY. 150 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1 151 * See there for additional Copyrights. 152 */ 153 int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, 154 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 155 { 156 int ret; 157 unsigned int i, reg = 0, rev = 0; 158 159 debug("Initializing OMAP EHCI\n"); 160 161 ret = board_usb_init(); 162 if (ret < 0) 163 return ret; 164 165 /* Put the PHY in RESET */ 166 omap_ehci_phy_reset(1, 10); 167 168 ret = omap_uhh_reset(); 169 if (ret < 0) 170 return ret; 171 172 ret = omap_ehci_tll_reset(); 173 if (ret) 174 return ret; 175 176 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | 177 OMAP_USBTLL_SYSCONFIG_SIDLEMODE | 178 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc); 179 180 /* Put UHH in NoIdle/NoStandby mode */ 181 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc); 182 183 /* setup ULPI bypass and burst configurations */ 184 clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN, 185 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | 186 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | 187 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN)); 188 189 rev = readl(&uhh->rev); 190 if (rev == OMAP_USBHS_REV1) { 191 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0])) 192 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); 193 else 194 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); 195 196 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1])) 197 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); 198 else 199 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); 200 201 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2])) 202 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); 203 else 204 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); 205 } else if (rev == OMAP_USBHS_REV2) { 206 207 clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR), 208 OMAP4_UHH_HOSTCONFIG_APP_START_CLK); 209 210 /* Clear port mode fields for PHY mode */ 211 212 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) 213 setbits_le32(®, OMAP_P1_MODE_HSIC); 214 215 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1])) 216 setbits_le32(®, OMAP_P2_MODE_HSIC); 217 218 } else if (rev == OMAP_USBHS_REV2_1) { 219 220 clrsetbits_le32(®, 221 (OMAP_P1_MODE_CLEAR | 222 OMAP_P2_MODE_CLEAR | 223 OMAP_P3_MODE_CLEAR), 224 OMAP4_UHH_HOSTCONFIG_APP_START_CLK); 225 226 /* Clear port mode fields for PHY mode */ 227 228 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) 229 setbits_le32(®, OMAP_P1_MODE_HSIC); 230 231 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1])) 232 setbits_le32(®, OMAP_P2_MODE_HSIC); 233 234 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2])) 235 setbits_le32(®, OMAP_P3_MODE_HSIC); 236 } 237 238 debug("OMAP UHH_REVISION 0x%x\n", rev); 239 writel(reg, &uhh->hostconfig); 240 241 for (i = 0; i < OMAP_HS_USB_PORTS; i++) 242 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i])) 243 omap_usbhs_hsic_init(i); 244 245 omap_ehci_phy_reset(0, 10); 246 247 /* 248 * An undocumented "feature" in the OMAP3 EHCI controller, 249 * causes suspended ports to be taken out of suspend when 250 * the USBCMD.Run/Stop bit is cleared (for example when 251 * we do ehci_bus_suspend). 252 * This breaks suspend-resume if the root-hub is allowed 253 * to suspend. Writing 1 to this undocumented register bit 254 * disables this feature and restores normal behavior. 255 */ 256 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04); 257 258 for (i = 0; i < OMAP_HS_USB_PORTS; i++) 259 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i])) 260 omap_ehci_soft_phy_reset(i); 261 262 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE); 263 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10); 264 265 debug("OMAP EHCI init done\n"); 266 return 0; 267 } 268