1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 20 #include <common.h> 21 #include <usb.h> 22 #include <asm/io.h> 23 #include <asm/arch/imx-regs.h> 24 #include <usb/ehci-fsl.h> 25 #include <errno.h> 26 27 #include "ehci.h" 28 29 #define USBCTRL_OTGBASE_OFFSET 0x600 30 31 #define MX25_OTG_SIC_SHIFT 29 32 #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) 33 #define MX25_OTG_PM_BIT (1 << 24) 34 #define MX25_OTG_PP_BIT (1 << 11) 35 #define MX25_OTG_OCPOL_BIT (1 << 3) 36 37 #define MX25_H1_SIC_SHIFT 21 38 #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) 39 #define MX25_H1_PP_BIT (1 << 18) 40 #define MX25_H1_PM_BIT (1 << 8) 41 #define MX25_H1_IPPUE_UP_BIT (1 << 7) 42 #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) 43 #define MX25_H1_TLL_BIT (1 << 5) 44 #define MX25_H1_USBTE_BIT (1 << 4) 45 #define MX25_H1_OCPOL_BIT (1 << 2) 46 47 #define MX31_OTG_SIC_SHIFT 29 48 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) 49 #define MX31_OTG_PM_BIT (1 << 24) 50 51 #define MX31_H2_SIC_SHIFT 21 52 #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) 53 #define MX31_H2_PM_BIT (1 << 16) 54 #define MX31_H2_DT_BIT (1 << 5) 55 56 #define MX31_H1_SIC_SHIFT 13 57 #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) 58 #define MX31_H1_PM_BIT (1 << 8) 59 #define MX31_H1_DT_BIT (1 << 4) 60 61 static int mxc_set_usbcontrol(int port, unsigned int flags) 62 { 63 unsigned int v; 64 65 v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); 66 #if defined(CONFIG_MX25) 67 switch (port) { 68 case 0: /* OTG port */ 69 v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | 70 MX25_OTG_OCPOL_BIT); 71 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; 72 73 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 74 v |= MX25_OTG_PM_BIT; 75 76 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 77 v |= MX25_OTG_PP_BIT; 78 79 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) 80 v |= MX25_OTG_OCPOL_BIT; 81 82 break; 83 case 1: /* H1 port */ 84 v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | 85 MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | 86 MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | 87 MX25_H1_IPPUE_UP_BIT); 88 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; 89 90 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 91 v |= MX25_H1_PM_BIT; 92 93 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 94 v |= MX25_H1_PP_BIT; 95 96 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) 97 v |= MX25_H1_OCPOL_BIT; 98 99 if (!(flags & MXC_EHCI_TTL_ENABLED)) 100 v |= MX25_H1_TLL_BIT; 101 102 if (flags & MXC_EHCI_INTERNAL_PHY) 103 v |= MX25_H1_USBTE_BIT; 104 105 if (flags & MXC_EHCI_IPPUE_DOWN) 106 v |= MX25_H1_IPPUE_DOWN_BIT; 107 108 if (flags & MXC_EHCI_IPPUE_UP) 109 v |= MX25_H1_IPPUE_UP_BIT; 110 111 break; 112 default: 113 return -EINVAL; 114 } 115 #elif defined(CONFIG_MX31) 116 switch (port) { 117 case 0: /* OTG port */ 118 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); 119 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; 120 121 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 122 v |= MX31_OTG_PM_BIT; 123 124 break; 125 case 1: /* H1 port */ 126 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); 127 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; 128 129 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 130 v |= MX31_H1_PM_BIT; 131 132 if (!(flags & MXC_EHCI_TTL_ENABLED)) 133 v |= MX31_H1_DT_BIT; 134 135 break; 136 case 2: /* H2 port */ 137 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); 138 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; 139 140 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 141 v |= MX31_H2_PM_BIT; 142 143 if (!(flags & MXC_EHCI_TTL_ENABLED)) 144 v |= MX31_H2_DT_BIT; 145 146 break; 147 default: 148 return -EINVAL; 149 } 150 #else 151 #error MXC EHCI USB driver not supported on this platform 152 #endif 153 writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); 154 155 return 0; 156 } 157 158 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 159 { 160 struct usb_ehci *ehci; 161 #ifdef CONFIG_MX31 162 struct clock_control_regs *sc_regs = 163 (struct clock_control_regs *)CCM_BASE; 164 165 __raw_readl(&sc_regs->ccmr); 166 __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; 167 #endif 168 169 udelay(80); 170 171 ehci = (struct usb_ehci *)(IMX_USB_BASE + 172 IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT); 173 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 174 *hcor = (struct ehci_hcor *)((uint32_t) *hccr + 175 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 176 setbits_le32(&ehci->usbmode, CM_HOST); 177 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 178 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 179 180 udelay(10000); 181 182 return 0; 183 } 184 185 /* 186 * Destroy the appropriate control structures corresponding 187 * the the EHCI host controller. 188 */ 189 int ehci_hcd_stop(int index) 190 { 191 return 0; 192 } 193