1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 20 #include <common.h> 21 #include <usb.h> 22 #include <asm/io.h> 23 #include <asm/arch/imx-regs.h> 24 #include <usb/ehci-fsl.h> 25 #include <errno.h> 26 27 #include "ehci.h" 28 29 #define USBCTRL_OTGBASE_OFFSET 0x600 30 31 #define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) 32 #define MX25_USB_CTRL_HSTD_BIT (1<<5) 33 #define MX25_USB_CTRL_USBTE_BIT (1<<4) 34 #define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) 35 36 #define MX31_OTG_SIC_SHIFT 29 37 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) 38 #define MX31_OTG_PM_BIT (1 << 24) 39 40 #define MX31_H2_SIC_SHIFT 21 41 #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) 42 #define MX31_H2_PM_BIT (1 << 16) 43 #define MX31_H2_DT_BIT (1 << 5) 44 45 #define MX31_H1_SIC_SHIFT 13 46 #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) 47 #define MX31_H1_PM_BIT (1 << 8) 48 #define MX31_H1_DT_BIT (1 << 4) 49 50 static int mxc_set_usbcontrol(int port, unsigned int flags) 51 { 52 unsigned int v; 53 54 #if defined(CONFIG_MX25) 55 v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT | 56 MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT; 57 #elif defined(CONFIG_MX31) 58 v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); 59 60 switch (port) { 61 case 0: /* OTG port */ 62 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); 63 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; 64 65 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 66 v |= MX31_OTG_PM_BIT; 67 68 break; 69 case 1: /* H1 port */ 70 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); 71 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; 72 73 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 74 v |= MX31_H1_PM_BIT; 75 76 if (!(flags & MXC_EHCI_TTL_ENABLED)) 77 v |= MX31_H1_DT_BIT; 78 79 break; 80 case 2: /* H2 port */ 81 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); 82 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; 83 84 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 85 v |= MX31_H2_PM_BIT; 86 87 if (!(flags & MXC_EHCI_TTL_ENABLED)) 88 v |= MX31_H2_DT_BIT; 89 90 break; 91 default: 92 return -EINVAL; 93 } 94 #else 95 #error MXC EHCI USB driver not supported on this platform 96 #endif 97 writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); 98 99 return 0; 100 } 101 102 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 103 { 104 struct usb_ehci *ehci; 105 #ifdef CONFIG_MX31 106 struct clock_control_regs *sc_regs = 107 (struct clock_control_regs *)CCM_BASE; 108 109 __raw_readl(&sc_regs->ccmr); 110 __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; 111 #endif 112 113 udelay(80); 114 115 ehci = (struct usb_ehci *)(IMX_USB_BASE + 116 (0x200 * CONFIG_MXC_USB_PORT)); 117 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 118 *hcor = (struct ehci_hcor *)((uint32_t) *hccr + 119 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 120 setbits_le32(&ehci->usbmode, CM_HOST); 121 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 122 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 123 124 udelay(10000); 125 126 return 0; 127 } 128 129 /* 130 * Destroy the appropriate control structures corresponding 131 * the the EHCI host controller. 132 */ 133 int ehci_hcd_stop(int index) 134 { 135 return 0; 136 } 137