1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <usb.h> 10 #include <errno.h> 11 #include <linux/compiler.h> 12 #include <usb/ehci-fsl.h> 13 #include <asm/io.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/clock.h> 16 #include <asm/imx-common/iomux-v3.h> 17 18 #include "ehci.h" 19 20 #define USB_OTGREGS_OFFSET 0x000 21 #define USB_H1REGS_OFFSET 0x200 22 #define USB_H2REGS_OFFSET 0x400 23 #define USB_H3REGS_OFFSET 0x600 24 #define USB_OTHERREGS_OFFSET 0x800 25 26 #define USB_H1_CTRL_OFFSET 0x04 27 28 #define USBPHY_CTRL 0x00000030 29 #define USBPHY_CTRL_SET 0x00000034 30 #define USBPHY_CTRL_CLR 0x00000038 31 #define USBPHY_CTRL_TOG 0x0000003c 32 33 #define USBPHY_PWD 0x00000000 34 #define USBPHY_CTRL_SFTRST 0x80000000 35 #define USBPHY_CTRL_CLKGATE 0x40000000 36 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000 37 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000 38 #define USBPHY_CTRL_OTG_ID 0x08000000 39 40 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 41 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 42 43 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 44 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 45 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 46 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 47 48 #define USBNC_OFFSET 0x200 49 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */ 50 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */ 51 #define UCTRL_PM (1 << 9) /* OTG Power Mask */ 52 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ 53 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ 54 55 /* USBCMD */ 56 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ 57 #define UCMD_RESET (1 << 1) /* controller reset */ 58 59 #if defined(CONFIG_MX6) 60 static const unsigned phy_bases[] = { 61 USB_PHY0_BASE_ADDR, 62 USB_PHY1_BASE_ADDR, 63 }; 64 65 static void usb_internal_phy_clock_gate(int index, int on) 66 { 67 void __iomem *phy_reg; 68 69 if (index >= ARRAY_SIZE(phy_bases)) 70 return; 71 72 phy_reg = (void __iomem *)phy_bases[index]; 73 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; 74 writel(USBPHY_CTRL_CLKGATE, phy_reg); 75 } 76 77 static void usb_power_config(int index) 78 { 79 struct anatop_regs __iomem *anatop = 80 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; 81 void __iomem *chrg_detect; 82 void __iomem *pll_480_ctrl_clr; 83 void __iomem *pll_480_ctrl_set; 84 85 switch (index) { 86 case 0: 87 chrg_detect = &anatop->usb1_chrg_detect; 88 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr; 89 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set; 90 break; 91 case 1: 92 chrg_detect = &anatop->usb2_chrg_detect; 93 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr; 94 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set; 95 break; 96 default: 97 return; 98 } 99 /* 100 * Some phy and power's special controls 101 * 1. The external charger detector needs to be disabled 102 * or the signal at DP will be poor 103 * 2. The PLL's power and output to usb 104 * is totally controlled by IC, so the Software only needs 105 * to enable them at initializtion. 106 */ 107 writel(ANADIG_USB2_CHRG_DETECT_EN_B | 108 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, 109 chrg_detect); 110 111 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, 112 pll_480_ctrl_clr); 113 114 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | 115 ANADIG_USB2_PLL_480_CTRL_POWER | 116 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, 117 pll_480_ctrl_set); 118 } 119 120 /* Return 0 : host node, <>0 : device mode */ 121 static int usb_phy_enable(int index, struct usb_ehci *ehci) 122 { 123 void __iomem *phy_reg; 124 void __iomem *phy_ctrl; 125 void __iomem *usb_cmd; 126 127 if (index >= ARRAY_SIZE(phy_bases)) 128 return 0; 129 130 phy_reg = (void __iomem *)phy_bases[index]; 131 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 132 usb_cmd = (void __iomem *)&ehci->usbcmd; 133 134 /* Stop then Reset */ 135 clrbits_le32(usb_cmd, UCMD_RUN_STOP); 136 while (readl(usb_cmd) & UCMD_RUN_STOP) 137 ; 138 139 setbits_le32(usb_cmd, UCMD_RESET); 140 while (readl(usb_cmd) & UCMD_RESET) 141 ; 142 143 /* Reset USBPHY module */ 144 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); 145 udelay(10); 146 147 /* Remove CLKGATE and SFTRST */ 148 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); 149 udelay(10); 150 151 /* Power up the PHY */ 152 writel(0, phy_reg + USBPHY_PWD); 153 /* enable FS/LS device */ 154 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | 155 USBPHY_CTRL_ENUTMILEVEL3); 156 157 return 0; 158 } 159 160 int usb_phy_mode(int port) 161 { 162 void __iomem *phy_reg; 163 void __iomem *phy_ctrl; 164 u32 val; 165 166 phy_reg = (void __iomem *)phy_bases[port]; 167 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 168 169 val = readl(phy_ctrl); 170 171 if (val & USBPHY_CTRL_OTG_ID) 172 return USB_INIT_DEVICE; 173 else 174 return USB_INIT_HOST; 175 } 176 177 /* Base address for this IP block is 0x02184800 */ 178 struct usbnc_regs { 179 u32 ctrl[4]; /* otg/host1-3 */ 180 u32 uh2_hsic_ctrl; 181 u32 uh3_hsic_ctrl; 182 u32 otg_phy_ctrl_0; 183 u32 uh1_phy_ctrl_0; 184 }; 185 #elif defined(CONFIG_MX7) 186 struct usbnc_regs { 187 u32 ctrl1; 188 u32 ctrl2; 189 u32 reserve1[10]; 190 u32 phy_cfg1; 191 u32 phy_cfg2; 192 u32 phy_status; 193 u32 reserve2[4]; 194 u32 adp_cfg1; 195 u32 adp_cfg2; 196 u32 adp_status; 197 }; 198 199 static void usb_power_config(int index) 200 { 201 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 202 (0x10000 * index) + USBNC_OFFSET); 203 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); 204 205 /* Enable usb_otg_id detection */ 206 setbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); 207 } 208 209 int usb_phy_mode(int port) 210 { 211 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 212 (0x10000 * port) + USBNC_OFFSET); 213 void __iomem *status = (void __iomem *)(&usbnc->phy_status); 214 u32 val; 215 216 val = readl(status); 217 218 if (val & USBNC_PHYSTATUS_ID_DIG) 219 return USB_INIT_DEVICE; 220 else 221 return USB_INIT_HOST; 222 } 223 #endif 224 225 static void usb_oc_config(int index) 226 { 227 #if defined(CONFIG_MX6) 228 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 229 USB_OTHERREGS_OFFSET); 230 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); 231 #elif defined(CONFIG_MX7) 232 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 233 (0x10000 * index) + USBNC_OFFSET); 234 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); 235 #endif 236 237 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 238 /* mx6qarm2 seems to required a different setting*/ 239 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL); 240 #else 241 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); 242 #endif 243 244 #if defined(CONFIG_MX6) 245 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); 246 #elif defined(CONFIG_MX7) 247 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM); 248 #endif 249 } 250 251 /** 252 * board_ehci_hcd_init - override usb phy mode 253 * @port: usb host/otg port 254 * 255 * Target board specific, override usb_phy_mode. 256 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be 257 * left disconnected in this case usb_phy_mode will not be able to identify 258 * the phy mode that usb port is used. 259 * Machine file overrides board_usb_phy_mode. 260 * 261 * Return: USB_INIT_DEVICE or USB_INIT_HOST 262 */ 263 int __weak board_usb_phy_mode(int port) 264 { 265 return usb_phy_mode(port); 266 } 267 268 /** 269 * board_ehci_hcd_init - set usb vbus voltage 270 * @port: usb otg port 271 * 272 * Target board specific, setup iomux pad to setup supply vbus voltage 273 * for usb otg port. Machine board file overrides board_ehci_hcd_init 274 * 275 * Return: 0 Success 276 */ 277 int __weak board_ehci_hcd_init(int port) 278 { 279 return 0; 280 } 281 282 /** 283 * board_ehci_power - enables/disables usb vbus voltage 284 * @port: usb otg port 285 * @on: on/off vbus voltage 286 * 287 * Enables/disables supply vbus voltage for usb otg port. 288 * Machine board file overrides board_ehci_power 289 * 290 * Return: 0 Success 291 */ 292 int __weak board_ehci_power(int port, int on) 293 { 294 return 0; 295 } 296 297 int ehci_hcd_init(int index, enum usb_init_type init, 298 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 299 { 300 enum usb_init_type type; 301 #if defined(CONFIG_MX6) 302 u32 controller_spacing = 0x200; 303 #elif defined(CONFIG_MX7) 304 u32 controller_spacing = 0x10000; 305 #endif 306 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + 307 (controller_spacing * index)); 308 309 if (index > 3) 310 return -EINVAL; 311 enable_usboh3_clk(1); 312 mdelay(1); 313 314 /* Do board specific initialization */ 315 board_ehci_hcd_init(index); 316 317 usb_power_config(index); 318 usb_oc_config(index); 319 320 #if defined(CONFIG_MX6) 321 usb_internal_phy_clock_gate(index, 1); 322 usb_phy_enable(index, ehci); 323 #endif 324 type = board_usb_phy_mode(index); 325 326 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 327 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 328 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 329 330 if ((type == init) || (type == USB_INIT_DEVICE)) 331 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1); 332 if (type != init) 333 return -ENODEV; 334 if (type == USB_INIT_DEVICE) 335 return 0; 336 337 setbits_le32(&ehci->usbmode, CM_HOST); 338 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 339 setbits_le32(&ehci->portsc, USB_EN); 340 341 mdelay(10); 342 343 return 0; 344 } 345 346 int ehci_hcd_stop(int index) 347 { 348 return 0; 349 } 350