1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <usb.h> 10 #include <errno.h> 11 #include <linux/compiler.h> 12 #include <usb/ehci-ci.h> 13 #include <asm/io.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/clock.h> 16 #include <dm.h> 17 #include <power/regulator.h> 18 19 #include "ehci.h" 20 21 #define MX5_USBOTHER_REGS_OFFSET 0x800 22 23 24 #define MXC_OTG_OFFSET 0 25 #define MXC_H1_OFFSET 0x200 26 #define MXC_H2_OFFSET 0x400 27 #define MXC_H3_OFFSET 0x600 28 29 #define MXC_USBCTRL_OFFSET 0 30 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 31 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc 32 #define MXC_USB_CTRL_1_OFFSET 0x10 33 #define MXC_USBH2CTRL_OFFSET 0x14 34 #define MXC_USBH3CTRL_OFFSET 0x18 35 36 /* USB_CTRL */ 37 /* OTG wakeup intr enable */ 38 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) 39 /* OTG power mask */ 40 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) 41 /* OTG power pin polarity */ 42 #define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) 43 /* Host1 ULPI interrupt enable */ 44 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) 45 /* HOST1 wakeup intr enable */ 46 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) 47 /* HOST1 power mask */ 48 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) 49 /* HOST1 power pin polarity */ 50 #define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) 51 52 /* USB_PHY_CTRL_FUNC */ 53 /* OTG Polarity of Overcurrent */ 54 #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) 55 /* OTG Disable Overcurrent Event */ 56 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) 57 /* UH1 Polarity of Overcurrent */ 58 #define MXC_H1_OC_POL_BIT (1 << 6) 59 /* UH1 Disable Overcurrent Event */ 60 #define MXC_H1_OC_DIS_BIT (1 << 5) 61 /* OTG Power Pin Polarity */ 62 #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) 63 64 /* USBH2CTRL */ 65 #define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31) 66 #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) 67 #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) 68 #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) 69 #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) 70 #define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4) 71 72 /* USBH3CTRL */ 73 #define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31) 74 #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) 75 #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) 76 #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) 77 #define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4) 78 79 /* USB_CTRL_1 */ 80 #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) 81 82 int mxc_set_usbcontrol(int port, unsigned int flags) 83 { 84 unsigned int v; 85 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR; 86 void __iomem *usbother_base; 87 int ret = 0; 88 89 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 90 91 switch (port) { 92 case 0: /* OTG port */ 93 if (flags & MXC_EHCI_INTERNAL_PHY) { 94 v = __raw_readl(usbother_base + 95 MXC_USB_PHY_CTR_FUNC_OFFSET); 96 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 97 v |= MXC_OTG_PHYCTRL_OC_POL_BIT; 98 else 99 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; 100 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 101 /* OC/USBPWR is used */ 102 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; 103 else 104 /* OC/USBPWR is not used */ 105 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; 106 #ifdef CONFIG_MX51 107 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 108 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; 109 else 110 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; 111 #endif 112 __raw_writel(v, usbother_base + 113 MXC_USB_PHY_CTR_FUNC_OFFSET); 114 115 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 116 #ifdef CONFIG_MX51 117 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 118 v &= ~MXC_OTG_UCTRL_OPM_BIT; 119 else 120 v |= MXC_OTG_UCTRL_OPM_BIT; 121 #endif 122 #ifdef CONFIG_MX53 123 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 124 v |= MXC_OTG_UCTRL_O_PWR_POL_BIT; 125 else 126 v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT; 127 #endif 128 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 129 } 130 break; 131 case 1: /* Host 1 ULPI */ 132 #ifdef CONFIG_MX51 133 /* The clock for the USBH1 ULPI port will come externally 134 from the PHY. */ 135 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET); 136 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + 137 MXC_USB_CTRL_1_OFFSET); 138 #endif 139 140 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 141 #ifdef CONFIG_MX51 142 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 143 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */ 144 else 145 v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */ 146 #endif 147 #ifdef CONFIG_MX53 148 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 149 v |= MXC_H1_UCTRL_H1_PWR_POL_BIT; 150 else 151 v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT; 152 #endif 153 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 154 155 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 156 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 157 v |= MXC_H1_OC_POL_BIT; 158 else 159 v &= ~MXC_H1_OC_POL_BIT; 160 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 161 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ 162 else 163 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ 164 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 165 166 break; 167 case 2: /* Host 2 ULPI */ 168 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); 169 #ifdef CONFIG_MX51 170 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 171 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */ 172 else 173 v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ 174 #endif 175 #ifdef CONFIG_MX53 176 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 177 v |= MXC_H2_UCTRL_H2_OC_POL_BIT; 178 else 179 v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT; 180 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 181 v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */ 182 else 183 v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */ 184 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 185 v |= MXC_H2_UCTRL_H2_PWR_POL_BIT; 186 else 187 v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT; 188 #endif 189 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); 190 break; 191 #ifdef CONFIG_MX53 192 case 3: /* Host 3 ULPI */ 193 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); 194 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 195 v |= MXC_H3_UCTRL_H3_OC_POL_BIT; 196 else 197 v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT; 198 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 199 v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */ 200 else 201 v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */ 202 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 203 v |= MXC_H3_UCTRL_H3_PWR_POL_BIT; 204 else 205 v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT; 206 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); 207 break; 208 #endif 209 } 210 211 return ret; 212 } 213 214 int __weak board_ehci_hcd_init(int port) 215 { 216 return 0; 217 } 218 219 void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) 220 { 221 } 222 223 __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, 224 uint32_t *reg) 225 { 226 mdelay(50); 227 } 228 229 #if !CONFIG_IS_ENABLED(DM_USB) 230 static const struct ehci_ops mx5_ehci_ops = { 231 .powerup_fixup = mx5_ehci_powerup_fixup, 232 }; 233 234 int ehci_hcd_init(int index, enum usb_init_type init, 235 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 236 { 237 struct usb_ehci *ehci; 238 239 /* The only user for this is efikamx-usb */ 240 ehci_set_controller_priv(index, NULL, &mx5_ehci_ops); 241 set_usboh3_clk(); 242 enable_usboh3_clk(true); 243 set_usb_phy_clk(); 244 enable_usb_phy1_clk(true); 245 enable_usb_phy2_clk(true); 246 mdelay(1); 247 248 /* Do board specific initialization */ 249 board_ehci_hcd_init(CONFIG_MXC_USB_PORT); 250 251 ehci = (struct usb_ehci *)(OTG_BASE_ADDR + 252 (0x200 * CONFIG_MXC_USB_PORT)); 253 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 254 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 255 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 256 setbits_le32(&ehci->usbmode, CM_HOST); 257 258 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 259 setbits_le32(&ehci->portsc, USB_EN); 260 261 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 262 mdelay(10); 263 264 /* Do board specific post-initialization */ 265 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); 266 267 return 0; 268 } 269 270 int ehci_hcd_stop(int index) 271 { 272 return 0; 273 } 274 #else /* CONFIG_IS_ENABLED(DM_USB) */ 275 struct ehci_mx5_priv_data { 276 struct ehci_ctrl ctrl; 277 struct usb_ehci *ehci; 278 struct udevice *vbus_supply; 279 enum usb_init_type init_type; 280 int portnr; 281 }; 282 283 static const struct ehci_ops mx5_ehci_ops = { 284 .powerup_fixup = mx5_ehci_powerup_fixup, 285 }; 286 287 static int ehci_usb_ofdata_to_platdata(struct udevice *dev) 288 { 289 struct usb_platdata *plat = dev_get_platdata(dev); 290 const char *mode; 291 292 mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL); 293 if (mode) { 294 if (strcmp(mode, "peripheral") == 0) 295 plat->init_type = USB_INIT_DEVICE; 296 else if (strcmp(mode, "host") == 0) 297 plat->init_type = USB_INIT_HOST; 298 else 299 return -EINVAL; 300 } 301 302 return 0; 303 } 304 305 static int ehci_usb_probe(struct udevice *dev) 306 { 307 struct usb_platdata *plat = dev_get_platdata(dev); 308 struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev); 309 struct ehci_mx5_priv_data *priv = dev_get_priv(dev); 310 enum usb_init_type type = plat->init_type; 311 struct ehci_hccr *hccr; 312 struct ehci_hcor *hcor; 313 int ret; 314 315 set_usboh3_clk(); 316 enable_usboh3_clk(true); 317 set_usb_phy_clk(); 318 enable_usb_phy1_clk(true); 319 enable_usb_phy2_clk(true); 320 mdelay(1); 321 322 priv->ehci = ehci; 323 priv->portnr = dev->seq; 324 priv->init_type = type; 325 326 ret = device_get_supply_regulator(dev, "vbus-supply", 327 &priv->vbus_supply); 328 if (ret) 329 debug("%s: No vbus supply\n", dev->name); 330 331 if (!ret && priv->vbus_supply) { 332 ret = regulator_set_enable(priv->vbus_supply, 333 (type == USB_INIT_DEVICE) ? 334 false : true); 335 if (ret) { 336 puts("Error enabling VBUS supply\n"); 337 return ret; 338 } 339 } 340 341 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 342 hcor = (struct ehci_hcor *)((uint32_t)hccr + 343 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); 344 setbits_le32(&ehci->usbmode, CM_HOST); 345 346 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 347 setbits_le32(&ehci->portsc, USB_EN); 348 349 mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS); 350 mdelay(10); 351 352 return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0, 353 priv->init_type); 354 } 355 356 static const struct udevice_id mx5_usb_ids[] = { 357 { .compatible = "fsl,imx53-usb" }, 358 { } 359 }; 360 361 U_BOOT_DRIVER(usb_mx5) = { 362 .name = "ehci_mx5", 363 .id = UCLASS_USB, 364 .of_match = mx5_usb_ids, 365 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, 366 .probe = ehci_usb_probe, 367 .remove = ehci_deregister, 368 .ops = &ehci_usb_ops, 369 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 370 .priv_auto_alloc_size = sizeof(struct ehci_mx5_priv_data), 371 .flags = DM_FLAG_ALLOC_PRIV_DMA, 372 }; 373 #endif /* !CONFIG_IS_ENABLED(DM_USB) */ 374