1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15 16 #include <common.h> 17 #include <usb.h> 18 #include <errno.h> 19 #include <linux/compiler.h> 20 #include <usb/ehci-fsl.h> 21 #include <asm/io.h> 22 #include <asm/arch/imx-regs.h> 23 #include <asm/arch/clock.h> 24 #include <asm/arch/mx5x_pins.h> 25 #include <asm/arch/iomux.h> 26 27 #include "ehci.h" 28 29 #define MX5_USBOTHER_REGS_OFFSET 0x800 30 31 32 #define MXC_OTG_OFFSET 0 33 #define MXC_H1_OFFSET 0x200 34 #define MXC_H2_OFFSET 0x400 35 36 #define MXC_USBCTRL_OFFSET 0 37 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 38 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc 39 #define MXC_USB_CTRL_1_OFFSET 0x10 40 #define MXC_USBH2CTRL_OFFSET 0x14 41 42 /* USB_CTRL */ 43 /* OTG wakeup intr enable */ 44 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) 45 /* OTG power mask */ 46 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) 47 /* Host1 ULPI interrupt enable */ 48 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) 49 /* HOST1 wakeup intr enable */ 50 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) 51 /* HOST1 power mask */ 52 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) 53 54 /* USB_PHY_CTRL_FUNC */ 55 /* OTG Disable Overcurrent Event */ 56 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) 57 /* UH1 Disable Overcurrent Event */ 58 #define MXC_H1_OC_DIS_BIT (1 << 5) 59 60 /* USBH2CTRL */ 61 #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) 62 #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) 63 #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) 64 65 /* USB_CTRL_1 */ 66 #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) 67 68 /* USB pin configuration */ 69 #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ 70 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \ 71 PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL) 72 73 #ifdef CONFIG_MX51 74 /* 75 * Configure the MX51 USB H1 IOMUX 76 */ 77 void setup_iomux_usb_h1(void) 78 { 79 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0); 80 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG); 81 mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0); 82 mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG); 83 mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0); 84 mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG); 85 mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0); 86 mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG); 87 88 mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0); 89 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG); 90 mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0); 91 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG); 92 mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0); 93 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG); 94 mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0); 95 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG); 96 mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0); 97 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG); 98 mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0); 99 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG); 100 mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0); 101 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG); 102 mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0); 103 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG); 104 } 105 106 /* 107 * Configure the MX51 USB H2 IOMUX 108 */ 109 void setup_iomux_usb_h2(void) 110 { 111 mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2); 112 mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG); 113 mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2); 114 mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG); 115 mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2); 116 mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG); 117 mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2); 118 mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG); 119 120 mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2); 121 mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG); 122 mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2); 123 mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG); 124 mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2); 125 mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG); 126 mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2); 127 mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG); 128 mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2); 129 mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG); 130 mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2); 131 mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG); 132 mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2); 133 mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG); 134 mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2); 135 mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG); 136 } 137 #endif 138 139 int mxc_set_usbcontrol(int port, unsigned int flags) 140 { 141 unsigned int v; 142 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR; 143 void __iomem *usbother_base; 144 int ret = 0; 145 146 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 147 148 switch (port) { 149 case 0: /* OTG port */ 150 if (flags & MXC_EHCI_INTERNAL_PHY) { 151 v = __raw_readl(usbother_base + 152 MXC_USB_PHY_CTR_FUNC_OFFSET); 153 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 154 /* OC/USBPWR is used */ 155 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; 156 else 157 /* OC/USBPWR is not used */ 158 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; 159 __raw_writel(v, usbother_base + 160 MXC_USB_PHY_CTR_FUNC_OFFSET); 161 162 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 163 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 164 v |= MXC_OTG_UCTRL_OPM_BIT; 165 else 166 v &= ~MXC_OTG_UCTRL_OPM_BIT; 167 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 168 } 169 break; 170 case 1: /* Host 1 ULPI */ 171 #ifdef CONFIG_MX51 172 /* The clock for the USBH1 ULPI port will come externally 173 from the PHY. */ 174 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET); 175 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + 176 MXC_USB_CTRL_1_OFFSET); 177 #endif 178 179 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 180 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 181 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */ 182 else 183 v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */ 184 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 185 186 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 187 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 188 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ 189 else 190 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ 191 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 192 193 break; 194 case 2: /* Host 2 ULPI */ 195 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); 196 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 197 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */ 198 else 199 v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ 200 201 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); 202 break; 203 } 204 205 return ret; 206 } 207 208 void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) 209 { 210 } 211 212 void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) 213 __attribute((weak, alias("__board_ehci_hcd_postinit"))); 214 215 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 216 { 217 struct usb_ehci *ehci; 218 #ifdef CONFIG_MX53 219 struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR; 220 u32 reg; 221 222 reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26); 223 /* derive USB PHY clock multiplexer from PLL3 */ 224 reg |= 1 << 26; 225 __raw_writel(reg, &sc_regs->cscmr1); 226 #endif 227 228 set_usboh3_clk(); 229 enable_usboh3_clk(1); 230 set_usb_phy_clk(); 231 enable_usb_phy1_clk(1); 232 enable_usb_phy2_clk(1); 233 mdelay(1); 234 235 /* Do board specific initialization */ 236 board_ehci_hcd_init(CONFIG_MXC_USB_PORT); 237 238 ehci = (struct usb_ehci *)(OTG_BASE_ADDR + 239 (0x200 * CONFIG_MXC_USB_PORT)); 240 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 241 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 242 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 243 setbits_le32(&ehci->usbmode, CM_HOST); 244 245 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 246 setbits_le32(&ehci->portsc, USB_EN); 247 248 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 249 mdelay(10); 250 251 /* Do board specific post-initialization */ 252 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); 253 254 return 0; 255 } 256 257 int ehci_hcd_stop(int index) 258 { 259 return 0; 260 } 261