1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15 16 #include <common.h> 17 #include <usb.h> 18 #include <errno.h> 19 #include <linux/compiler.h> 20 #include <usb/ehci-fsl.h> 21 #include <asm/io.h> 22 #include <asm/arch/imx-regs.h> 23 #include <asm/arch/clock.h> 24 #include <asm/arch/mx5x_pins.h> 25 #include <asm/arch/iomux.h> 26 27 #include "ehci.h" 28 29 #define MX5_USBOTHER_REGS_OFFSET 0x800 30 31 32 #define MXC_OTG_OFFSET 0 33 #define MXC_H1_OFFSET 0x200 34 #define MXC_H2_OFFSET 0x400 35 #define MXC_H3_OFFSET 0x600 36 37 #define MXC_USBCTRL_OFFSET 0 38 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 39 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc 40 #define MXC_USB_CTRL_1_OFFSET 0x10 41 #define MXC_USBH2CTRL_OFFSET 0x14 42 #define MXC_USBH3CTRL_OFFSET 0x18 43 44 /* USB_CTRL */ 45 /* OTG wakeup intr enable */ 46 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) 47 /* OTG power mask */ 48 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) 49 /* Host1 ULPI interrupt enable */ 50 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) 51 /* HOST1 wakeup intr enable */ 52 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) 53 /* HOST1 power mask */ 54 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) 55 56 /* USB_PHY_CTRL_FUNC */ 57 /* OTG Disable Overcurrent Event */ 58 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) 59 /* UH1 Disable Overcurrent Event */ 60 #define MXC_H1_OC_DIS_BIT (1 << 5) 61 62 /* USBH2CTRL */ 63 #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) 64 #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) 65 #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) 66 #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) 67 68 /* USBH3CTRL */ 69 #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) 70 #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) 71 #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) 72 73 /* USB_CTRL_1 */ 74 #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) 75 76 /* USB pin configuration */ 77 #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ 78 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \ 79 PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL) 80 81 #ifdef CONFIG_MX51 82 /* 83 * Configure the MX51 USB H1 IOMUX 84 */ 85 void setup_iomux_usb_h1(void) 86 { 87 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0); 88 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG); 89 mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0); 90 mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG); 91 mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0); 92 mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG); 93 mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0); 94 mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG); 95 96 mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0); 97 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG); 98 mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0); 99 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG); 100 mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0); 101 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG); 102 mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0); 103 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG); 104 mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0); 105 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG); 106 mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0); 107 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG); 108 mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0); 109 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG); 110 mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0); 111 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG); 112 } 113 114 /* 115 * Configure the MX51 USB H2 IOMUX 116 */ 117 void setup_iomux_usb_h2(void) 118 { 119 mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2); 120 mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG); 121 mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2); 122 mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG); 123 mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2); 124 mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG); 125 mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2); 126 mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG); 127 128 mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2); 129 mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG); 130 mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2); 131 mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG); 132 mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2); 133 mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG); 134 mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2); 135 mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG); 136 mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2); 137 mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG); 138 mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2); 139 mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG); 140 mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2); 141 mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG); 142 mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2); 143 mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG); 144 } 145 #endif 146 147 int mxc_set_usbcontrol(int port, unsigned int flags) 148 { 149 unsigned int v; 150 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR; 151 void __iomem *usbother_base; 152 int ret = 0; 153 154 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 155 156 switch (port) { 157 case 0: /* OTG port */ 158 if (flags & MXC_EHCI_INTERNAL_PHY) { 159 v = __raw_readl(usbother_base + 160 MXC_USB_PHY_CTR_FUNC_OFFSET); 161 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 162 /* OC/USBPWR is used */ 163 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; 164 else 165 /* OC/USBPWR is not used */ 166 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; 167 __raw_writel(v, usbother_base + 168 MXC_USB_PHY_CTR_FUNC_OFFSET); 169 170 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 171 #ifdef CONFIG_MX51 172 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 173 v &= ~MXC_OTG_UCTRL_OPM_BIT; 174 else 175 v |= MXC_OTG_UCTRL_OPM_BIT; 176 #endif 177 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 178 } 179 break; 180 case 1: /* Host 1 ULPI */ 181 #ifdef CONFIG_MX51 182 /* The clock for the USBH1 ULPI port will come externally 183 from the PHY. */ 184 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET); 185 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + 186 MXC_USB_CTRL_1_OFFSET); 187 #endif 188 189 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 190 #ifdef CONFIG_MX51 191 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 192 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */ 193 else 194 v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */ 195 #endif 196 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 197 198 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 199 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 200 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ 201 else 202 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ 203 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 204 205 break; 206 case 2: /* Host 2 ULPI */ 207 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); 208 #ifdef CONFIG_MX51 209 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 210 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */ 211 else 212 v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ 213 #endif 214 #ifdef CONFIG_MX53 215 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 216 v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */ 217 else 218 v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */ 219 #endif 220 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); 221 break; 222 #ifdef CONFIG_MX53 223 case 3: /* Host 3 ULPI */ 224 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); 225 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 226 v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */ 227 else 228 v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */ 229 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); 230 break; 231 #endif 232 } 233 234 return ret; 235 } 236 237 void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) 238 { 239 } 240 241 void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) 242 __attribute((weak, alias("__board_ehci_hcd_postinit"))); 243 244 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 245 { 246 struct usb_ehci *ehci; 247 #ifdef CONFIG_MX53 248 struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR; 249 u32 reg; 250 251 reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26); 252 /* derive USB PHY clock multiplexer from PLL3 */ 253 reg |= 1 << 26; 254 __raw_writel(reg, &sc_regs->cscmr1); 255 #endif 256 257 set_usboh3_clk(); 258 enable_usboh3_clk(1); 259 set_usb_phy_clk(); 260 enable_usb_phy1_clk(1); 261 enable_usb_phy2_clk(1); 262 mdelay(1); 263 264 /* Do board specific initialization */ 265 board_ehci_hcd_init(CONFIG_MXC_USB_PORT); 266 267 ehci = (struct usb_ehci *)(OTG_BASE_ADDR + 268 (0x200 * CONFIG_MXC_USB_PORT)); 269 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 270 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 271 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 272 setbits_le32(&ehci->usbmode, CM_HOST); 273 274 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 275 setbits_le32(&ehci->portsc, USB_EN); 276 277 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 278 mdelay(10); 279 280 /* Do board specific post-initialization */ 281 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); 282 283 return 0; 284 } 285 286 int ehci_hcd_stop(int index) 287 { 288 return 0; 289 } 290