1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Excito Elektronik i Skåne AB 4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 5 * 6 * All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2 of 11 * the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <errno.h> 25 #include <asm/byteorder.h> 26 #include <asm/unaligned.h> 27 #include <usb.h> 28 #include <asm/io.h> 29 #include <malloc.h> 30 #include <watchdog.h> 31 #include <linux/compiler.h> 32 33 #include "ehci.h" 34 35 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 37 #endif 38 39 static struct ehci_ctrl { 40 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ 41 struct ehci_hcor *hcor; 42 int rootdev; 43 uint16_t portreset; 44 struct QH qh_list __aligned(USB_DMA_MINALIGN); 45 struct QH periodic_queue __aligned(USB_DMA_MINALIGN); 46 uint32_t *periodic_list; 47 int ntds; 48 } ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; 49 50 #define ALIGN_END_ADDR(type, ptr, size) \ 51 ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN)) 52 53 static struct descriptor { 54 struct usb_hub_descriptor hub; 55 struct usb_device_descriptor device; 56 struct usb_linux_config_descriptor config; 57 struct usb_linux_interface_descriptor interface; 58 struct usb_endpoint_descriptor endpoint; 59 } __attribute__ ((packed)) descriptor = { 60 { 61 0x8, /* bDescLength */ 62 0x29, /* bDescriptorType: hub descriptor */ 63 2, /* bNrPorts -- runtime modified */ 64 0, /* wHubCharacteristics */ 65 10, /* bPwrOn2PwrGood */ 66 0, /* bHubCntrCurrent */ 67 {}, /* Device removable */ 68 {} /* at most 7 ports! XXX */ 69 }, 70 { 71 0x12, /* bLength */ 72 1, /* bDescriptorType: UDESC_DEVICE */ 73 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 74 9, /* bDeviceClass: UDCLASS_HUB */ 75 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 76 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 77 64, /* bMaxPacketSize: 64 bytes */ 78 0x0000, /* idVendor */ 79 0x0000, /* idProduct */ 80 cpu_to_le16(0x0100), /* bcdDevice */ 81 1, /* iManufacturer */ 82 2, /* iProduct */ 83 0, /* iSerialNumber */ 84 1 /* bNumConfigurations: 1 */ 85 }, 86 { 87 0x9, 88 2, /* bDescriptorType: UDESC_CONFIG */ 89 cpu_to_le16(0x19), 90 1, /* bNumInterface */ 91 1, /* bConfigurationValue */ 92 0, /* iConfiguration */ 93 0x40, /* bmAttributes: UC_SELF_POWER */ 94 0 /* bMaxPower */ 95 }, 96 { 97 0x9, /* bLength */ 98 4, /* bDescriptorType: UDESC_INTERFACE */ 99 0, /* bInterfaceNumber */ 100 0, /* bAlternateSetting */ 101 1, /* bNumEndpoints */ 102 9, /* bInterfaceClass: UICLASS_HUB */ 103 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 104 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 105 0 /* iInterface */ 106 }, 107 { 108 0x7, /* bLength */ 109 5, /* bDescriptorType: UDESC_ENDPOINT */ 110 0x81, /* bEndpointAddress: 111 * UE_DIR_IN | EHCI_INTR_ENDPT 112 */ 113 3, /* bmAttributes: UE_INTERRUPT */ 114 8, /* wMaxPacketSize */ 115 255 /* bInterval */ 116 }, 117 }; 118 119 #if defined(CONFIG_EHCI_IS_TDI) 120 #define ehci_is_TDI() (1) 121 #else 122 #define ehci_is_TDI() (0) 123 #endif 124 125 int __ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) 126 { 127 return PORTSC_PSPD(reg); 128 } 129 130 int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) 131 __attribute__((weak, alias("__ehci_get_port_speed"))); 132 133 void __ehci_set_usbmode(int index) 134 { 135 uint32_t tmp; 136 uint32_t *reg_ptr; 137 138 reg_ptr = (uint32_t *)((u8 *)&ehcic[index].hcor->or_usbcmd + USBMODE); 139 tmp = ehci_readl(reg_ptr); 140 tmp |= USBMODE_CM_HC; 141 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) 142 tmp |= USBMODE_BE; 143 #endif 144 ehci_writel(reg_ptr, tmp); 145 } 146 147 void ehci_set_usbmode(int index) 148 __attribute__((weak, alias("__ehci_set_usbmode"))); 149 150 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 151 { 152 mdelay(50); 153 } 154 155 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 156 __attribute__((weak, alias("__ehci_powerup_fixup"))); 157 158 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) 159 { 160 uint32_t result; 161 do { 162 result = ehci_readl(ptr); 163 udelay(5); 164 if (result == ~(uint32_t)0) 165 return -1; 166 result &= mask; 167 if (result == done) 168 return 0; 169 usec--; 170 } while (usec > 0); 171 return -1; 172 } 173 174 static int ehci_reset(int index) 175 { 176 uint32_t cmd; 177 int ret = 0; 178 179 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd); 180 cmd = (cmd & ~CMD_RUN) | CMD_RESET; 181 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd); 182 ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd, 183 CMD_RESET, 0, 250 * 1000); 184 if (ret < 0) { 185 printf("EHCI fail to reset\n"); 186 goto out; 187 } 188 189 if (ehci_is_TDI()) 190 ehci_set_usbmode(index); 191 192 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH 193 cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning); 194 cmd &= ~TXFIFO_THRESH_MASK; 195 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); 196 ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd); 197 #endif 198 out: 199 return ret; 200 } 201 202 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) 203 { 204 uint32_t delta, next; 205 uint32_t addr = (uint32_t)buf; 206 int idx; 207 208 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN)) 209 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf); 210 211 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN)); 212 213 idx = 0; 214 while (idx < QT_BUFFER_CNT) { 215 td->qt_buffer[idx] = cpu_to_hc32(addr); 216 td->qt_buffer_hi[idx] = 0; 217 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1); 218 delta = next - addr; 219 if (delta >= sz) 220 break; 221 sz -= delta; 222 addr = next; 223 idx++; 224 } 225 226 if (idx == QT_BUFFER_CNT) { 227 printf("out of buffer pointers (%u bytes left)\n", sz); 228 return -1; 229 } 230 231 return 0; 232 } 233 234 static inline u8 ehci_encode_speed(enum usb_device_speed speed) 235 { 236 #define QH_HIGH_SPEED 2 237 #define QH_FULL_SPEED 0 238 #define QH_LOW_SPEED 1 239 if (speed == USB_SPEED_HIGH) 240 return QH_HIGH_SPEED; 241 if (speed == USB_SPEED_LOW) 242 return QH_LOW_SPEED; 243 return QH_FULL_SPEED; 244 } 245 246 static int 247 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, 248 int length, struct devrequest *req) 249 { 250 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN); 251 struct qTD *qtd; 252 int qtd_count = 0; 253 int qtd_counter = 0; 254 volatile struct qTD *vtd; 255 unsigned long ts; 256 uint32_t *tdp; 257 uint32_t endpt, maxpacket, token, usbsts; 258 uint32_t c, toggle; 259 uint32_t cmd; 260 int timeout; 261 int ret = 0; 262 struct ehci_ctrl *ctrl = dev->controller; 263 264 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, 265 buffer, length, req); 266 if (req != NULL) 267 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", 268 req->request, req->request, 269 req->requesttype, req->requesttype, 270 le16_to_cpu(req->value), le16_to_cpu(req->value), 271 le16_to_cpu(req->index)); 272 273 #define PKT_ALIGN 512 274 /* 275 * The USB transfer is split into qTD transfers. Eeach qTD transfer is 276 * described by a transfer descriptor (the qTD). The qTDs form a linked 277 * list with a queue head (QH). 278 * 279 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot 280 * have its beginning in a qTD transfer and its end in the following 281 * one, so the qTD transfer lengths have to be chosen accordingly. 282 * 283 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to 284 * single pages. The first data buffer can start at any offset within a 285 * page (not considering the cache-line alignment issues), while the 286 * following buffers must be page-aligned. There is no alignment 287 * constraint on the size of a qTD transfer. 288 */ 289 if (req != NULL) 290 /* 1 qTD will be needed for SETUP, and 1 for ACK. */ 291 qtd_count += 1 + 1; 292 if (length > 0 || req == NULL) { 293 /* 294 * Determine the qTD transfer size that will be used for the 295 * data payload (not considering the first qTD transfer, which 296 * may be longer or shorter, and the final one, which may be 297 * shorter). 298 * 299 * In order to keep each packet within a qTD transfer, the qTD 300 * transfer size is aligned to PKT_ALIGN, which is a multiple of 301 * wMaxPacketSize (except in some cases for interrupt transfers, 302 * see comment in submit_int_msg()). 303 * 304 * By default, i.e. if the input buffer is aligned to PKT_ALIGN, 305 * QT_BUFFER_CNT full pages will be used. 306 */ 307 int xfr_sz = QT_BUFFER_CNT; 308 /* 309 * However, if the input buffer is not aligned to PKT_ALIGN, the 310 * qTD transfer size will be one page shorter, and the first qTD 311 * data buffer of each transfer will be page-unaligned. 312 */ 313 if ((uint32_t)buffer & (PKT_ALIGN - 1)) 314 xfr_sz--; 315 /* Convert the qTD transfer size to bytes. */ 316 xfr_sz *= EHCI_PAGE_SIZE; 317 /* 318 * Approximate by excess the number of qTDs that will be 319 * required for the data payload. The exact formula is way more 320 * complicated and saves at most 2 qTDs, i.e. a total of 128 321 * bytes. 322 */ 323 qtd_count += 2 + length / xfr_sz; 324 } 325 /* 326 * Threshold value based on the worst-case total size of the allocated qTDs for 327 * a mass-storage transfer of 65535 blocks of 512 bytes. 328 */ 329 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024 330 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI 331 #endif 332 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD)); 333 if (qtd == NULL) { 334 printf("unable to allocate TDs\n"); 335 return -1; 336 } 337 338 memset(qh, 0, sizeof(struct QH)); 339 memset(qtd, 0, qtd_count * sizeof(*qtd)); 340 341 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 342 343 /* 344 * Setup QH (3.6 in ehci-r10.pdf) 345 * 346 * qh_link ................. 03-00 H 347 * qh_endpt1 ............... 07-04 H 348 * qh_endpt2 ............... 0B-08 H 349 * - qh_curtd 350 * qh_overlay.qt_next ...... 13-10 H 351 * - qh_overlay.qt_altnext 352 */ 353 qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | QH_LINK_TYPE_QH); 354 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe); 355 maxpacket = usb_maxpacket(dev, pipe); 356 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) | 357 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) | 358 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) | 359 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | 360 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | 361 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); 362 qh->qh_endpt1 = cpu_to_hc32(endpt); 363 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) | 364 QH_ENDPT2_HUBADDR(dev->parent->devnum) | 365 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); 366 qh->qh_endpt2 = cpu_to_hc32(endpt); 367 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 368 369 tdp = &qh->qh_overlay.qt_next; 370 371 if (req != NULL) { 372 /* 373 * Setup request qTD (3.5 in ehci-r10.pdf) 374 * 375 * qt_next ................ 03-00 H 376 * qt_altnext ............. 07-04 H 377 * qt_token ............... 0B-08 H 378 * 379 * [ buffer, buffer_hi ] loaded with "req". 380 */ 381 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 382 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 383 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) | 384 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 385 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) | 386 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 387 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 388 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) { 389 printf("unable to construct SETUP TD\n"); 390 goto fail; 391 } 392 /* Update previous qTD! */ 393 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); 394 tdp = &qtd[qtd_counter++].qt_next; 395 toggle = 1; 396 } 397 398 if (length > 0 || req == NULL) { 399 uint8_t *buf_ptr = buffer; 400 int left_length = length; 401 402 do { 403 /* 404 * Determine the size of this qTD transfer. By default, 405 * QT_BUFFER_CNT full pages can be used. 406 */ 407 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE; 408 /* 409 * However, if the input buffer is not page-aligned, the 410 * portion of the first page before the buffer start 411 * offset within that page is unusable. 412 */ 413 xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1); 414 /* 415 * In order to keep each packet within a qTD transfer, 416 * align the qTD transfer size to PKT_ALIGN. 417 */ 418 xfr_bytes &= ~(PKT_ALIGN - 1); 419 /* 420 * This transfer may be shorter than the available qTD 421 * transfer size that has just been computed. 422 */ 423 xfr_bytes = min(xfr_bytes, left_length); 424 425 /* 426 * Setup request qTD (3.5 in ehci-r10.pdf) 427 * 428 * qt_next ................ 03-00 H 429 * qt_altnext ............. 07-04 H 430 * qt_token ............... 0B-08 H 431 * 432 * [ buffer, buffer_hi ] loaded with "buffer". 433 */ 434 qtd[qtd_counter].qt_next = 435 cpu_to_hc32(QT_NEXT_TERMINATE); 436 qtd[qtd_counter].qt_altnext = 437 cpu_to_hc32(QT_NEXT_TERMINATE); 438 token = QT_TOKEN_DT(toggle) | 439 QT_TOKEN_TOTALBYTES(xfr_bytes) | 440 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) | 441 QT_TOKEN_CERR(3) | 442 QT_TOKEN_PID(usb_pipein(pipe) ? 443 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) | 444 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 445 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 446 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr, 447 xfr_bytes)) { 448 printf("unable to construct DATA TD\n"); 449 goto fail; 450 } 451 /* Update previous qTD! */ 452 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); 453 tdp = &qtd[qtd_counter++].qt_next; 454 /* 455 * Data toggle has to be adjusted since the qTD transfer 456 * size is not always an even multiple of 457 * wMaxPacketSize. 458 */ 459 if ((xfr_bytes / maxpacket) & 1) 460 toggle ^= 1; 461 buf_ptr += xfr_bytes; 462 left_length -= xfr_bytes; 463 } while (left_length > 0); 464 } 465 466 if (req != NULL) { 467 /* 468 * Setup request qTD (3.5 in ehci-r10.pdf) 469 * 470 * qt_next ................ 03-00 H 471 * qt_altnext ............. 07-04 H 472 * qt_token ............... 0B-08 H 473 */ 474 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 475 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 476 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) | 477 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 478 QT_TOKEN_PID(usb_pipein(pipe) ? 479 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) | 480 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 481 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 482 /* Update previous qTD! */ 483 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); 484 tdp = &qtd[qtd_counter++].qt_next; 485 } 486 487 ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH); 488 489 /* Flush dcache */ 490 flush_dcache_range((uint32_t)&ctrl->qh_list, 491 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 492 flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1)); 493 flush_dcache_range((uint32_t)qtd, 494 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 495 496 /* Set async. queue head pointer. */ 497 ehci_writel(&ctrl->hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list); 498 499 usbsts = ehci_readl(&ctrl->hcor->or_usbsts); 500 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f)); 501 502 /* Enable async. schedule. */ 503 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 504 cmd |= CMD_ASE; 505 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 506 507 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS, 508 100 * 1000); 509 if (ret < 0) { 510 printf("EHCI fail timeout STS_ASS set\n"); 511 goto fail; 512 } 513 514 /* Wait for TDs to be processed. */ 515 ts = get_timer(0); 516 vtd = &qtd[qtd_counter - 1]; 517 timeout = USB_TIMEOUT_MS(pipe); 518 do { 519 /* Invalidate dcache */ 520 invalidate_dcache_range((uint32_t)&ctrl->qh_list, 521 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 522 invalidate_dcache_range((uint32_t)qh, 523 ALIGN_END_ADDR(struct QH, qh, 1)); 524 invalidate_dcache_range((uint32_t)qtd, 525 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 526 527 token = hc32_to_cpu(vtd->qt_token); 528 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) 529 break; 530 WATCHDOG_RESET(); 531 } while (get_timer(ts) < timeout); 532 533 /* 534 * Invalidate the memory area occupied by buffer 535 * Don't try to fix the buffer alignment, if it isn't properly 536 * aligned it's upper layer's fault so let invalidate_dcache_range() 537 * vow about it. But we have to fix the length as it's actual 538 * transfer length and can be unaligned. This is potentially 539 * dangerous operation, it's responsibility of the calling 540 * code to make sure enough space is reserved. 541 */ 542 invalidate_dcache_range((uint32_t)buffer, 543 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN)); 544 545 /* Check that the TD processing happened */ 546 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) 547 printf("EHCI timed out on TD - token=%#x\n", token); 548 549 /* Disable async schedule. */ 550 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 551 cmd &= ~CMD_ASE; 552 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 553 554 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0, 555 100 * 1000); 556 if (ret < 0) { 557 printf("EHCI fail timeout STS_ASS reset\n"); 558 goto fail; 559 } 560 561 token = hc32_to_cpu(qh->qh_overlay.qt_token); 562 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) { 563 debug("TOKEN=%#x\n", token); 564 switch (QT_TOKEN_GET_STATUS(token) & 565 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) { 566 case 0: 567 toggle = QT_TOKEN_GET_DT(token); 568 usb_settoggle(dev, usb_pipeendpoint(pipe), 569 usb_pipeout(pipe), toggle); 570 dev->status = 0; 571 break; 572 case QT_TOKEN_STATUS_HALTED: 573 dev->status = USB_ST_STALLED; 574 break; 575 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR: 576 case QT_TOKEN_STATUS_DATBUFERR: 577 dev->status = USB_ST_BUF_ERR; 578 break; 579 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET: 580 case QT_TOKEN_STATUS_BABBLEDET: 581 dev->status = USB_ST_BABBLE_DET; 582 break; 583 default: 584 dev->status = USB_ST_CRC_ERR; 585 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED) 586 dev->status |= USB_ST_STALLED; 587 break; 588 } 589 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token); 590 } else { 591 dev->act_len = 0; 592 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", 593 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts), 594 ehci_readl(&ctrl->hcor->or_portsc[0]), 595 ehci_readl(&ctrl->hcor->or_portsc[1])); 596 } 597 598 free(qtd); 599 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; 600 601 fail: 602 free(qtd); 603 return -1; 604 } 605 606 int 607 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, 608 int length, struct devrequest *req) 609 { 610 uint8_t tmpbuf[4]; 611 u16 typeReq; 612 void *srcptr = NULL; 613 int len, srclen; 614 uint32_t reg; 615 uint32_t *status_reg; 616 int port = le16_to_cpu(req->index) & 0xff; 617 struct ehci_ctrl *ctrl = dev->controller; 618 619 if (port > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { 620 printf("The request port(%d) is not configured\n", port - 1); 621 return -1; 622 } 623 status_reg = (uint32_t *)&ctrl->hcor->or_portsc[port - 1]; 624 srclen = 0; 625 626 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", 627 req->request, req->request, 628 req->requesttype, req->requesttype, 629 le16_to_cpu(req->value), le16_to_cpu(req->index)); 630 631 typeReq = req->request | req->requesttype << 8; 632 633 switch (typeReq) { 634 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 635 switch (le16_to_cpu(req->value) >> 8) { 636 case USB_DT_DEVICE: 637 debug("USB_DT_DEVICE request\n"); 638 srcptr = &descriptor.device; 639 srclen = descriptor.device.bLength; 640 break; 641 case USB_DT_CONFIG: 642 debug("USB_DT_CONFIG config\n"); 643 srcptr = &descriptor.config; 644 srclen = descriptor.config.bLength + 645 descriptor.interface.bLength + 646 descriptor.endpoint.bLength; 647 break; 648 case USB_DT_STRING: 649 debug("USB_DT_STRING config\n"); 650 switch (le16_to_cpu(req->value) & 0xff) { 651 case 0: /* Language */ 652 srcptr = "\4\3\1\0"; 653 srclen = 4; 654 break; 655 case 1: /* Vendor */ 656 srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; 657 srclen = 14; 658 break; 659 case 2: /* Product */ 660 srcptr = "\52\3E\0H\0C\0I\0 " 661 "\0H\0o\0s\0t\0 " 662 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 663 srclen = 42; 664 break; 665 default: 666 debug("unknown value DT_STRING %x\n", 667 le16_to_cpu(req->value)); 668 goto unknown; 669 } 670 break; 671 default: 672 debug("unknown value %x\n", le16_to_cpu(req->value)); 673 goto unknown; 674 } 675 break; 676 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 677 switch (le16_to_cpu(req->value) >> 8) { 678 case USB_DT_HUB: 679 debug("USB_DT_HUB config\n"); 680 srcptr = &descriptor.hub; 681 srclen = descriptor.hub.bLength; 682 break; 683 default: 684 debug("unknown value %x\n", le16_to_cpu(req->value)); 685 goto unknown; 686 } 687 break; 688 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 689 debug("USB_REQ_SET_ADDRESS\n"); 690 ctrl->rootdev = le16_to_cpu(req->value); 691 break; 692 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 693 debug("USB_REQ_SET_CONFIGURATION\n"); 694 /* Nothing to do */ 695 break; 696 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 697 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 698 tmpbuf[1] = 0; 699 srcptr = tmpbuf; 700 srclen = 2; 701 break; 702 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 703 memset(tmpbuf, 0, 4); 704 reg = ehci_readl(status_reg); 705 if (reg & EHCI_PS_CS) 706 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 707 if (reg & EHCI_PS_PE) 708 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 709 if (reg & EHCI_PS_SUSP) 710 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 711 if (reg & EHCI_PS_OCA) 712 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 713 if (reg & EHCI_PS_PR) 714 tmpbuf[0] |= USB_PORT_STAT_RESET; 715 if (reg & EHCI_PS_PP) 716 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 717 718 if (ehci_is_TDI()) { 719 switch (ehci_get_port_speed(ctrl->hcor, reg)) { 720 case PORTSC_PSPD_FS: 721 break; 722 case PORTSC_PSPD_LS: 723 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 724 break; 725 case PORTSC_PSPD_HS: 726 default: 727 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 728 break; 729 } 730 } else { 731 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 732 } 733 734 if (reg & EHCI_PS_CSC) 735 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 736 if (reg & EHCI_PS_PEC) 737 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 738 if (reg & EHCI_PS_OCC) 739 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 740 if (ctrl->portreset & (1 << port)) 741 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 742 743 srcptr = tmpbuf; 744 srclen = 4; 745 break; 746 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 747 reg = ehci_readl(status_reg); 748 reg &= ~EHCI_PS_CLEAR; 749 switch (le16_to_cpu(req->value)) { 750 case USB_PORT_FEAT_ENABLE: 751 reg |= EHCI_PS_PE; 752 ehci_writel(status_reg, reg); 753 break; 754 case USB_PORT_FEAT_POWER: 755 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) { 756 reg |= EHCI_PS_PP; 757 ehci_writel(status_reg, reg); 758 } 759 break; 760 case USB_PORT_FEAT_RESET: 761 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && 762 !ehci_is_TDI() && 763 EHCI_PS_IS_LOWSPEED(reg)) { 764 /* Low speed device, give up ownership. */ 765 debug("port %d low speed --> companion\n", 766 port - 1); 767 reg |= EHCI_PS_PO; 768 ehci_writel(status_reg, reg); 769 break; 770 } else { 771 int ret; 772 773 reg |= EHCI_PS_PR; 774 reg &= ~EHCI_PS_PE; 775 ehci_writel(status_reg, reg); 776 /* 777 * caller must wait, then call GetPortStatus 778 * usb 2.0 specification say 50 ms resets on 779 * root 780 */ 781 ehci_powerup_fixup(status_reg, ®); 782 783 ehci_writel(status_reg, reg & ~EHCI_PS_PR); 784 /* 785 * A host controller must terminate the reset 786 * and stabilize the state of the port within 787 * 2 milliseconds 788 */ 789 ret = handshake(status_reg, EHCI_PS_PR, 0, 790 2 * 1000); 791 if (!ret) 792 ctrl->portreset |= 1 << port; 793 else 794 printf("port(%d) reset error\n", 795 port - 1); 796 } 797 break; 798 case USB_PORT_FEAT_TEST: 799 reg &= ~(0xf << 16); 800 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16; 801 ehci_writel(status_reg, reg); 802 break; 803 default: 804 debug("unknown feature %x\n", le16_to_cpu(req->value)); 805 goto unknown; 806 } 807 /* unblock posted writes */ 808 (void) ehci_readl(&ctrl->hcor->or_usbcmd); 809 break; 810 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 811 reg = ehci_readl(status_reg); 812 reg &= ~EHCI_PS_CLEAR; 813 switch (le16_to_cpu(req->value)) { 814 case USB_PORT_FEAT_ENABLE: 815 reg &= ~EHCI_PS_PE; 816 break; 817 case USB_PORT_FEAT_C_ENABLE: 818 reg |= EHCI_PS_PE; 819 break; 820 case USB_PORT_FEAT_POWER: 821 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) 822 reg &= ~EHCI_PS_PP; 823 break; 824 case USB_PORT_FEAT_C_CONNECTION: 825 reg |= EHCI_PS_CSC; 826 break; 827 case USB_PORT_FEAT_OVER_CURRENT: 828 reg |= EHCI_PS_OCC; 829 break; 830 case USB_PORT_FEAT_C_RESET: 831 ctrl->portreset &= ~(1 << port); 832 break; 833 default: 834 debug("unknown feature %x\n", le16_to_cpu(req->value)); 835 goto unknown; 836 } 837 ehci_writel(status_reg, reg); 838 /* unblock posted write */ 839 (void) ehci_readl(&ctrl->hcor->or_usbcmd); 840 break; 841 default: 842 debug("Unknown request\n"); 843 goto unknown; 844 } 845 846 mdelay(1); 847 len = min3(srclen, le16_to_cpu(req->length), length); 848 if (srcptr != NULL && len > 0) 849 memcpy(buffer, srcptr, len); 850 else 851 debug("Len is 0\n"); 852 853 dev->act_len = len; 854 dev->status = 0; 855 return 0; 856 857 unknown: 858 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", 859 req->requesttype, req->request, le16_to_cpu(req->value), 860 le16_to_cpu(req->index), le16_to_cpu(req->length)); 861 862 dev->act_len = 0; 863 dev->status = USB_ST_STALLED; 864 return -1; 865 } 866 867 int usb_lowlevel_stop(int index) 868 { 869 return ehci_hcd_stop(index); 870 } 871 872 int usb_lowlevel_init(int index, void **controller) 873 { 874 uint32_t reg; 875 uint32_t cmd; 876 struct QH *qh_list; 877 struct QH *periodic; 878 int i; 879 880 if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor)) 881 return -1; 882 883 /* EHCI spec section 4.1 */ 884 if (ehci_reset(index)) 885 return -1; 886 887 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) 888 if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor)) 889 return -1; 890 #endif 891 /* Set the high address word (aka segment) for 64-bit controller */ 892 if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1) 893 ehci_writel(ehcic[index].hcor->or_ctrldssegment, 0); 894 895 qh_list = &ehcic[index].qh_list; 896 897 /* Set head of reclaim list */ 898 memset(qh_list, 0, sizeof(*qh_list)); 899 qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); 900 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) | 901 QH_ENDPT1_EPS(USB_SPEED_HIGH)); 902 qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); 903 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 904 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 905 qh_list->qh_overlay.qt_token = 906 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED)); 907 908 /* Set async. queue head pointer. */ 909 ehci_writel(&ehcic[index].hcor->or_asynclistaddr, (uint32_t)qh_list); 910 911 /* 912 * Set up periodic list 913 * Step 1: Parent QH for all periodic transfers. 914 */ 915 periodic = &ehcic[index].periodic_queue; 916 memset(periodic, 0, sizeof(*periodic)); 917 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); 918 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 919 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 920 921 /* 922 * Step 2: Setup frame-list: Every microframe, USB tries the same list. 923 * In particular, device specifications on polling frequency 924 * are disregarded. Keyboards seem to send NAK/NYet reliably 925 * when polled with an empty buffer. 926 * 927 * Split Transactions will be spread across microframes using 928 * S-mask and C-mask. 929 */ 930 ehcic[index].periodic_list = memalign(4096, 1024*4); 931 if (!ehcic[index].periodic_list) 932 return -ENOMEM; 933 for (i = 0; i < 1024; i++) { 934 ehcic[index].periodic_list[i] = (uint32_t)periodic 935 | QH_LINK_TYPE_QH; 936 } 937 938 /* Set periodic list base address */ 939 ehci_writel(&ehcic[index].hcor->or_periodiclistbase, 940 (uint32_t)ehcic[index].periodic_list); 941 942 reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams); 943 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); 944 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 945 /* Port Indicators */ 946 if (HCS_INDICATOR(reg)) 947 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 948 | 0x80, &descriptor.hub.wHubCharacteristics); 949 /* Port Power Control */ 950 if (HCS_PPC(reg)) 951 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 952 | 0x01, &descriptor.hub.wHubCharacteristics); 953 954 /* Start the host controller. */ 955 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd); 956 /* 957 * Philips, Intel, and maybe others need CMD_RUN before the 958 * root hub will detect new devices (why?); NEC doesn't 959 */ 960 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 961 cmd |= CMD_RUN; 962 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd); 963 964 /* take control over the ports */ 965 cmd = ehci_readl(&ehcic[index].hcor->or_configflag); 966 cmd |= FLAG_CF; 967 ehci_writel(&ehcic[index].hcor->or_configflag, cmd); 968 /* unblock posted write */ 969 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd); 970 mdelay(5); 971 reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase)); 972 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); 973 974 ehcic[index].rootdev = 0; 975 976 *controller = &ehcic[index]; 977 return 0; 978 } 979 980 int 981 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 982 int length) 983 { 984 985 if (usb_pipetype(pipe) != PIPE_BULK) { 986 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 987 return -1; 988 } 989 return ehci_submit_async(dev, pipe, buffer, length, NULL); 990 } 991 992 int 993 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 994 int length, struct devrequest *setup) 995 { 996 struct ehci_ctrl *ctrl = dev->controller; 997 998 if (usb_pipetype(pipe) != PIPE_CONTROL) { 999 debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); 1000 return -1; 1001 } 1002 1003 if (usb_pipedevice(pipe) == ctrl->rootdev) { 1004 if (!ctrl->rootdev) 1005 dev->speed = USB_SPEED_HIGH; 1006 return ehci_submit_root(dev, pipe, buffer, length, setup); 1007 } 1008 return ehci_submit_async(dev, pipe, buffer, length, setup); 1009 } 1010 1011 struct int_queue { 1012 struct QH *first; 1013 struct QH *current; 1014 struct QH *last; 1015 struct qTD *tds; 1016 }; 1017 1018 #define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f) 1019 1020 static int 1021 enable_periodic(struct ehci_ctrl *ctrl) 1022 { 1023 uint32_t cmd; 1024 struct ehci_hcor *hcor = ctrl->hcor; 1025 int ret; 1026 1027 cmd = ehci_readl(&hcor->or_usbcmd); 1028 cmd |= CMD_PSE; 1029 ehci_writel(&hcor->or_usbcmd, cmd); 1030 1031 ret = handshake((uint32_t *)&hcor->or_usbsts, 1032 STS_PSS, STS_PSS, 100 * 1000); 1033 if (ret < 0) { 1034 printf("EHCI failed: timeout when enabling periodic list\n"); 1035 return -ETIMEDOUT; 1036 } 1037 udelay(1000); 1038 return 0; 1039 } 1040 1041 static int 1042 disable_periodic(struct ehci_ctrl *ctrl) 1043 { 1044 uint32_t cmd; 1045 struct ehci_hcor *hcor = ctrl->hcor; 1046 int ret; 1047 1048 cmd = ehci_readl(&hcor->or_usbcmd); 1049 cmd &= ~CMD_PSE; 1050 ehci_writel(&hcor->or_usbcmd, cmd); 1051 1052 ret = handshake((uint32_t *)&hcor->or_usbsts, 1053 STS_PSS, 0, 100 * 1000); 1054 if (ret < 0) { 1055 printf("EHCI failed: timeout when disabling periodic list\n"); 1056 return -ETIMEDOUT; 1057 } 1058 return 0; 1059 } 1060 1061 static int periodic_schedules; 1062 1063 struct int_queue * 1064 create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, 1065 int elementsize, void *buffer) 1066 { 1067 struct ehci_ctrl *ctrl = dev->controller; 1068 struct int_queue *result = NULL; 1069 int i; 1070 1071 debug("Enter create_int_queue\n"); 1072 if (usb_pipetype(pipe) != PIPE_INTERRUPT) { 1073 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); 1074 return NULL; 1075 } 1076 1077 /* limit to 4 full pages worth of data - 1078 * we can safely fit them in a single TD, 1079 * no matter the alignment 1080 */ 1081 if (elementsize >= 16384) { 1082 debug("too large elements for interrupt transfers\n"); 1083 return NULL; 1084 } 1085 1086 result = malloc(sizeof(*result)); 1087 if (!result) { 1088 debug("ehci intr queue: out of memory\n"); 1089 goto fail1; 1090 } 1091 result->first = memalign(32, sizeof(struct QH) * queuesize); 1092 if (!result->first) { 1093 debug("ehci intr queue: out of memory\n"); 1094 goto fail2; 1095 } 1096 result->current = result->first; 1097 result->last = result->first + queuesize - 1; 1098 result->tds = memalign(32, sizeof(struct qTD) * queuesize); 1099 if (!result->tds) { 1100 debug("ehci intr queue: out of memory\n"); 1101 goto fail3; 1102 } 1103 memset(result->first, 0, sizeof(struct QH) * queuesize); 1104 memset(result->tds, 0, sizeof(struct qTD) * queuesize); 1105 1106 for (i = 0; i < queuesize; i++) { 1107 struct QH *qh = result->first + i; 1108 struct qTD *td = result->tds + i; 1109 void **buf = &qh->buffer; 1110 1111 qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH; 1112 if (i == queuesize - 1) 1113 qh->qh_link = QH_LINK_TERMINATE; 1114 1115 qh->qh_overlay.qt_next = (uint32_t)td; 1116 qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */ 1117 (usb_maxpacket(dev, pipe) << 16) | /* MPS */ 1118 (1 << 14) | 1119 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | 1120 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ 1121 (usb_pipedevice(pipe) << 0); 1122 qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */ 1123 (1 << 0); /* S-mask: microframe 0 */ 1124 if (dev->speed == USB_SPEED_LOW || 1125 dev->speed == USB_SPEED_FULL) { 1126 debug("TT: port: %d, hub address: %d\n", 1127 dev->portnr, dev->parent->devnum); 1128 qh->qh_endpt2 |= (dev->portnr << 23) | 1129 (dev->parent->devnum << 16) | 1130 (0x1c << 8); /* C-mask: microframes 2-4 */ 1131 } 1132 1133 td->qt_next = QT_NEXT_TERMINATE; 1134 td->qt_altnext = QT_NEXT_TERMINATE; 1135 debug("communication direction is '%s'\n", 1136 usb_pipein(pipe) ? "in" : "out"); 1137 td->qt_token = (elementsize << 16) | 1138 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ 1139 0x80; /* active */ 1140 td->qt_buffer[0] = (uint32_t)buffer + i * elementsize; 1141 td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff; 1142 td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff; 1143 td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff; 1144 td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff; 1145 1146 *buf = buffer + i * elementsize; 1147 } 1148 1149 if (disable_periodic(ctrl) < 0) { 1150 debug("FATAL: periodic should never fail, but did"); 1151 goto fail3; 1152 } 1153 1154 /* hook up to periodic list */ 1155 struct QH *list = &ctrl->periodic_queue; 1156 result->last->qh_link = list->qh_link; 1157 list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH; 1158 1159 if (enable_periodic(ctrl) < 0) { 1160 debug("FATAL: periodic should never fail, but did"); 1161 goto fail3; 1162 } 1163 periodic_schedules++; 1164 1165 debug("Exit create_int_queue\n"); 1166 return result; 1167 fail3: 1168 if (result->tds) 1169 free(result->tds); 1170 fail2: 1171 if (result->first) 1172 free(result->first); 1173 if (result) 1174 free(result); 1175 fail1: 1176 return NULL; 1177 } 1178 1179 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) 1180 { 1181 struct QH *cur = queue->current; 1182 1183 /* depleted queue */ 1184 if (cur == NULL) { 1185 debug("Exit poll_int_queue with completed queue\n"); 1186 return NULL; 1187 } 1188 /* still active */ 1189 if (cur->qh_overlay.qt_token & 0x80) { 1190 debug("Exit poll_int_queue with no completed intr transfer. " 1191 "token is %x\n", cur->qh_overlay.qt_token); 1192 return NULL; 1193 } 1194 if (!(cur->qh_link & QH_LINK_TERMINATE)) 1195 queue->current++; 1196 else 1197 queue->current = NULL; 1198 debug("Exit poll_int_queue with completed intr transfer. " 1199 "token is %x at %p (first at %p)\n", cur->qh_overlay.qt_token, 1200 &cur->qh_overlay.qt_token, queue->first); 1201 return cur->buffer; 1202 } 1203 1204 /* Do not free buffers associated with QHs, they're owned by someone else */ 1205 int 1206 destroy_int_queue(struct usb_device *dev, struct int_queue *queue) 1207 { 1208 struct ehci_ctrl *ctrl = dev->controller; 1209 int result = -1; 1210 unsigned long timeout; 1211 1212 if (disable_periodic(ctrl) < 0) { 1213 debug("FATAL: periodic should never fail, but did"); 1214 goto out; 1215 } 1216 periodic_schedules--; 1217 1218 struct QH *cur = &ctrl->periodic_queue; 1219 timeout = get_timer(0) + 500; /* abort after 500ms */ 1220 while (!(cur->qh_link & QH_LINK_TERMINATE)) { 1221 debug("considering %p, with qh_link %x\n", cur, cur->qh_link); 1222 if (NEXT_QH(cur) == queue->first) { 1223 debug("found candidate. removing from chain\n"); 1224 cur->qh_link = queue->last->qh_link; 1225 result = 0; 1226 break; 1227 } 1228 cur = NEXT_QH(cur); 1229 if (get_timer(0) > timeout) { 1230 printf("Timeout destroying interrupt endpoint queue\n"); 1231 result = -1; 1232 goto out; 1233 } 1234 } 1235 1236 if (periodic_schedules > 0) { 1237 result = enable_periodic(ctrl); 1238 if (result < 0) 1239 debug("FATAL: periodic should never fail, but did"); 1240 } 1241 1242 out: 1243 free(queue->tds); 1244 free(queue->first); 1245 free(queue); 1246 1247 return result; 1248 } 1249 1250 int 1251 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1252 int length, int interval) 1253 { 1254 void *backbuffer; 1255 struct int_queue *queue; 1256 unsigned long timeout; 1257 int result = 0, ret; 1258 1259 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", 1260 dev, pipe, buffer, length, interval); 1261 1262 /* 1263 * Interrupt transfers requiring several transactions are not supported 1264 * because bInterval is ignored. 1265 * 1266 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 1267 * <= PKT_ALIGN if several qTDs are required, while the USB 1268 * specification does not constrain this for interrupt transfers. That 1269 * means that ehci_submit_async() would support interrupt transfers 1270 * requiring several transactions only as long as the transfer size does 1271 * not require more than a single qTD. 1272 */ 1273 if (length > usb_maxpacket(dev, pipe)) { 1274 printf("%s: Interrupt transfers requiring several " 1275 "transactions are not supported.\n", __func__); 1276 return -1; 1277 } 1278 1279 queue = create_int_queue(dev, pipe, 1, length, buffer); 1280 1281 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1282 while ((backbuffer = poll_int_queue(dev, queue)) == NULL) 1283 if (get_timer(0) > timeout) { 1284 printf("Timeout poll on interrupt endpoint\n"); 1285 result = -ETIMEDOUT; 1286 break; 1287 } 1288 1289 if (backbuffer != buffer) { 1290 debug("got wrong buffer back (%x instead of %x)\n", 1291 (uint32_t)backbuffer, (uint32_t)buffer); 1292 return -EINVAL; 1293 } 1294 1295 ret = destroy_int_queue(dev, queue); 1296 if (ret < 0) 1297 return ret; 1298 1299 /* everything worked out fine */ 1300 return result; 1301 } 1302