1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Excito Elektronik i Skåne AB 4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 5 * 6 * All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2 of 11 * the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <asm/byteorder.h> 25 #include <usb.h> 26 #include <asm/io.h> 27 #include <malloc.h> 28 #include <watchdog.h> 29 30 #include "ehci.h" 31 32 int rootdev; 33 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ 34 volatile struct ehci_hcor *hcor; 35 36 static uint16_t portreset; 37 DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN); 38 39 #define ALIGN_END_ADDR(type, ptr, size) \ 40 ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN)) 41 42 static struct descriptor { 43 struct usb_hub_descriptor hub; 44 struct usb_device_descriptor device; 45 struct usb_linux_config_descriptor config; 46 struct usb_linux_interface_descriptor interface; 47 struct usb_endpoint_descriptor endpoint; 48 } __attribute__ ((packed)) descriptor = { 49 { 50 0x8, /* bDescLength */ 51 0x29, /* bDescriptorType: hub descriptor */ 52 2, /* bNrPorts -- runtime modified */ 53 0, /* wHubCharacteristics */ 54 10, /* bPwrOn2PwrGood */ 55 0, /* bHubCntrCurrent */ 56 {}, /* Device removable */ 57 {} /* at most 7 ports! XXX */ 58 }, 59 { 60 0x12, /* bLength */ 61 1, /* bDescriptorType: UDESC_DEVICE */ 62 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 63 9, /* bDeviceClass: UDCLASS_HUB */ 64 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 65 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 66 64, /* bMaxPacketSize: 64 bytes */ 67 0x0000, /* idVendor */ 68 0x0000, /* idProduct */ 69 cpu_to_le16(0x0100), /* bcdDevice */ 70 1, /* iManufacturer */ 71 2, /* iProduct */ 72 0, /* iSerialNumber */ 73 1 /* bNumConfigurations: 1 */ 74 }, 75 { 76 0x9, 77 2, /* bDescriptorType: UDESC_CONFIG */ 78 cpu_to_le16(0x19), 79 1, /* bNumInterface */ 80 1, /* bConfigurationValue */ 81 0, /* iConfiguration */ 82 0x40, /* bmAttributes: UC_SELF_POWER */ 83 0 /* bMaxPower */ 84 }, 85 { 86 0x9, /* bLength */ 87 4, /* bDescriptorType: UDESC_INTERFACE */ 88 0, /* bInterfaceNumber */ 89 0, /* bAlternateSetting */ 90 1, /* bNumEndpoints */ 91 9, /* bInterfaceClass: UICLASS_HUB */ 92 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 93 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 94 0 /* iInterface */ 95 }, 96 { 97 0x7, /* bLength */ 98 5, /* bDescriptorType: UDESC_ENDPOINT */ 99 0x81, /* bEndpointAddress: 100 * UE_DIR_IN | EHCI_INTR_ENDPT 101 */ 102 3, /* bmAttributes: UE_INTERRUPT */ 103 8, /* wMaxPacketSize */ 104 255 /* bInterval */ 105 }, 106 }; 107 108 #if defined(CONFIG_EHCI_IS_TDI) 109 #define ehci_is_TDI() (1) 110 #else 111 #define ehci_is_TDI() (0) 112 #endif 113 114 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 115 { 116 mdelay(50); 117 } 118 119 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 120 __attribute__((weak, alias("__ehci_powerup_fixup"))); 121 122 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) 123 { 124 uint32_t result; 125 do { 126 result = ehci_readl(ptr); 127 udelay(5); 128 if (result == ~(uint32_t)0) 129 return -1; 130 result &= mask; 131 if (result == done) 132 return 0; 133 usec--; 134 } while (usec > 0); 135 return -1; 136 } 137 138 static int ehci_reset(void) 139 { 140 uint32_t cmd; 141 uint32_t tmp; 142 uint32_t *reg_ptr; 143 int ret = 0; 144 145 cmd = ehci_readl(&hcor->or_usbcmd); 146 cmd = (cmd & ~CMD_RUN) | CMD_RESET; 147 ehci_writel(&hcor->or_usbcmd, cmd); 148 ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000); 149 if (ret < 0) { 150 printf("EHCI fail to reset\n"); 151 goto out; 152 } 153 154 if (ehci_is_TDI()) { 155 reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE); 156 tmp = ehci_readl(reg_ptr); 157 tmp |= USBMODE_CM_HC; 158 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) 159 tmp |= USBMODE_BE; 160 #endif 161 ehci_writel(reg_ptr, tmp); 162 } 163 164 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH 165 cmd = ehci_readl(&hcor->or_txfilltuning); 166 cmd &= ~TXFIFO_THRESH_MASK; 167 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); 168 ehci_writel(&hcor->or_txfilltuning, cmd); 169 #endif 170 out: 171 return ret; 172 } 173 174 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) 175 { 176 uint32_t delta, next; 177 uint32_t addr = (uint32_t)buf; 178 int idx; 179 180 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN)) 181 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf); 182 183 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN)); 184 185 idx = 0; 186 while (idx < QT_BUFFER_CNT) { 187 td->qt_buffer[idx] = cpu_to_hc32(addr); 188 td->qt_buffer_hi[idx] = 0; 189 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1); 190 delta = next - addr; 191 if (delta >= sz) 192 break; 193 sz -= delta; 194 addr = next; 195 idx++; 196 } 197 198 if (idx == QT_BUFFER_CNT) { 199 printf("out of buffer pointers (%u bytes left)\n", sz); 200 return -1; 201 } 202 203 return 0; 204 } 205 206 static int 207 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, 208 int length, struct devrequest *req) 209 { 210 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN); 211 struct qTD *qtd; 212 int qtd_count = 0; 213 int qtd_counter = 0; 214 215 volatile struct qTD *vtd; 216 unsigned long ts; 217 uint32_t *tdp; 218 uint32_t endpt, token, usbsts; 219 uint32_t c, toggle; 220 uint32_t cmd; 221 int timeout; 222 int ret = 0; 223 224 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, 225 buffer, length, req); 226 if (req != NULL) 227 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", 228 req->request, req->request, 229 req->requesttype, req->requesttype, 230 le16_to_cpu(req->value), le16_to_cpu(req->value), 231 le16_to_cpu(req->index)); 232 233 /* 234 * The USB transfer is split into qTD transfers. Eeach qTD transfer is 235 * described by a transfer descriptor (the qTD). The qTDs form a linked 236 * list with a queue head (QH). 237 * 238 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot 239 * have its beginning in a qTD transfer and its end in the following 240 * one, so the qTD transfer lengths have to be chosen accordingly. 241 * 242 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to 243 * single pages. The first data buffer can start at any offset within a 244 * page (not considering the cache-line alignment issues), while the 245 * following buffers must be page-aligned. There is no alignment 246 * constraint on the size of a qTD transfer. 247 */ 248 if (req != NULL) 249 /* 1 qTD will be needed for SETUP, and 1 for ACK. */ 250 qtd_count += 1 + 1; 251 if (length > 0 || req == NULL) { 252 /* 253 * Determine the qTD transfer size that will be used for the 254 * data payload (not considering the final qTD transfer, which 255 * may be shorter). 256 * 257 * In order to keep each packet within a qTD transfer, the qTD 258 * transfer size is aligned to EHCI_PAGE_SIZE, which is a 259 * multiple of wMaxPacketSize (except in some cases for 260 * interrupt transfers, see comment in submit_int_msg()). 261 * 262 * By default, i.e. if the input buffer is page-aligned, 263 * QT_BUFFER_CNT full pages will be used. 264 */ 265 int xfr_sz = QT_BUFFER_CNT; 266 /* 267 * However, if the input buffer is not page-aligned, the qTD 268 * transfer size will be one page shorter, and the first qTD 269 * data buffer of each transfer will be page-unaligned. 270 */ 271 if ((uint32_t)buffer & (EHCI_PAGE_SIZE - 1)) 272 xfr_sz--; 273 /* Convert the qTD transfer size to bytes. */ 274 xfr_sz *= EHCI_PAGE_SIZE; 275 /* 276 * Determine the number of qTDs that will be required for the 277 * data payload. This value has to be rounded up since the final 278 * qTD transfer may be shorter than the regular qTD transfer 279 * size that has just been computed. 280 */ 281 qtd_count += DIV_ROUND_UP(length, xfr_sz); 282 /* ZLPs also need a qTD. */ 283 if (!qtd_count) 284 qtd_count++; 285 } 286 /* 287 * Threshold value based on the worst-case total size of the qTDs to allocate 288 * for a mass-storage transfer of 65535 blocks of 512 bytes. 289 */ 290 #if CONFIG_SYS_MALLOC_LEN <= 128 * 1024 291 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI 292 #endif 293 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD)); 294 if (qtd == NULL) { 295 printf("unable to allocate TDs\n"); 296 return -1; 297 } 298 299 memset(qh, 0, sizeof(struct QH)); 300 memset(qtd, 0, qtd_count * sizeof(*qtd)); 301 302 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 303 304 /* 305 * Setup QH (3.6 in ehci-r10.pdf) 306 * 307 * qh_link ................. 03-00 H 308 * qh_endpt1 ............... 07-04 H 309 * qh_endpt2 ............... 0B-08 H 310 * - qh_curtd 311 * qh_overlay.qt_next ...... 13-10 H 312 * - qh_overlay.qt_altnext 313 */ 314 qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); 315 c = usb_pipespeed(pipe) != USB_SPEED_HIGH && !usb_pipeendpoint(pipe); 316 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) | 317 QH_ENDPT1_MAXPKTLEN(usb_maxpacket(dev, pipe)) | QH_ENDPT1_H(0) | 318 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) | 319 QH_ENDPT1_EPS(usb_pipespeed(pipe)) | 320 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | 321 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); 322 qh->qh_endpt1 = cpu_to_hc32(endpt); 323 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) | 324 QH_ENDPT2_HUBADDR(dev->parent->devnum) | 325 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); 326 qh->qh_endpt2 = cpu_to_hc32(endpt); 327 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 328 329 tdp = &qh->qh_overlay.qt_next; 330 331 if (req != NULL) { 332 /* 333 * Setup request qTD (3.5 in ehci-r10.pdf) 334 * 335 * qt_next ................ 03-00 H 336 * qt_altnext ............. 07-04 H 337 * qt_token ............... 0B-08 H 338 * 339 * [ buffer, buffer_hi ] loaded with "req". 340 */ 341 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 342 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 343 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) | 344 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 345 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) | 346 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 347 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 348 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) { 349 printf("unable to construct SETUP TD\n"); 350 goto fail; 351 } 352 /* Update previous qTD! */ 353 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); 354 tdp = &qtd[qtd_counter++].qt_next; 355 toggle = 1; 356 } 357 358 if (length > 0 || req == NULL) { 359 uint8_t *buf_ptr = buffer; 360 int left_length = length; 361 362 do { 363 /* 364 * Determine the size of this qTD transfer. By default, 365 * QT_BUFFER_CNT full pages can be used. 366 */ 367 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE; 368 /* 369 * However, if the input buffer is not page-aligned, the 370 * portion of the first page before the buffer start 371 * offset within that page is unusable. 372 */ 373 xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1); 374 /* 375 * In order to keep each packet within a qTD transfer, 376 * align the qTD transfer size to EHCI_PAGE_SIZE. 377 */ 378 xfr_bytes &= ~(EHCI_PAGE_SIZE - 1); 379 /* 380 * This transfer may be shorter than the available qTD 381 * transfer size that has just been computed. 382 */ 383 xfr_bytes = min(xfr_bytes, left_length); 384 385 /* 386 * Setup request qTD (3.5 in ehci-r10.pdf) 387 * 388 * qt_next ................ 03-00 H 389 * qt_altnext ............. 07-04 H 390 * qt_token ............... 0B-08 H 391 * 392 * [ buffer, buffer_hi ] loaded with "buffer". 393 */ 394 qtd[qtd_counter].qt_next = 395 cpu_to_hc32(QT_NEXT_TERMINATE); 396 qtd[qtd_counter].qt_altnext = 397 cpu_to_hc32(QT_NEXT_TERMINATE); 398 token = QT_TOKEN_DT(toggle) | 399 QT_TOKEN_TOTALBYTES(xfr_bytes) | 400 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) | 401 QT_TOKEN_CERR(3) | 402 QT_TOKEN_PID(usb_pipein(pipe) ? 403 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) | 404 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 405 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 406 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr, 407 xfr_bytes)) { 408 printf("unable to construct DATA TD\n"); 409 goto fail; 410 } 411 /* Update previous qTD! */ 412 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); 413 tdp = &qtd[qtd_counter++].qt_next; 414 buf_ptr += xfr_bytes; 415 left_length -= xfr_bytes; 416 } while (left_length > 0); 417 } 418 419 if (req != NULL) { 420 /* 421 * Setup request qTD (3.5 in ehci-r10.pdf) 422 * 423 * qt_next ................ 03-00 H 424 * qt_altnext ............. 07-04 H 425 * qt_token ............... 0B-08 H 426 */ 427 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 428 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 429 token = QT_TOKEN_DT(toggle) | QT_TOKEN_TOTALBYTES(0) | 430 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 431 QT_TOKEN_PID(usb_pipein(pipe) ? 432 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) | 433 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 434 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 435 /* Update previous qTD! */ 436 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); 437 tdp = &qtd[qtd_counter++].qt_next; 438 } 439 440 qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH); 441 442 /* Flush dcache */ 443 flush_dcache_range((uint32_t)qh_list, 444 ALIGN_END_ADDR(struct QH, qh_list, 1)); 445 flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1)); 446 flush_dcache_range((uint32_t)qtd, 447 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 448 449 /* Set async. queue head pointer. */ 450 ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list); 451 452 usbsts = ehci_readl(&hcor->or_usbsts); 453 ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f)); 454 455 /* Enable async. schedule. */ 456 cmd = ehci_readl(&hcor->or_usbcmd); 457 cmd |= CMD_ASE; 458 ehci_writel(&hcor->or_usbcmd, cmd); 459 460 ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, STS_ASS, 461 100 * 1000); 462 if (ret < 0) { 463 printf("EHCI fail timeout STS_ASS set\n"); 464 goto fail; 465 } 466 467 /* Wait for TDs to be processed. */ 468 ts = get_timer(0); 469 vtd = &qtd[qtd_counter - 1]; 470 timeout = USB_TIMEOUT_MS(pipe); 471 do { 472 /* Invalidate dcache */ 473 invalidate_dcache_range((uint32_t)qh_list, 474 ALIGN_END_ADDR(struct QH, qh_list, 1)); 475 invalidate_dcache_range((uint32_t)qh, 476 ALIGN_END_ADDR(struct QH, qh, 1)); 477 invalidate_dcache_range((uint32_t)qtd, 478 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 479 480 token = hc32_to_cpu(vtd->qt_token); 481 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) 482 break; 483 WATCHDOG_RESET(); 484 } while (get_timer(ts) < timeout); 485 486 /* 487 * Invalidate the memory area occupied by buffer 488 * Don't try to fix the buffer alignment, if it isn't properly 489 * aligned it's upper layer's fault so let invalidate_dcache_range() 490 * vow about it. But we have to fix the length as it's actual 491 * transfer length and can be unaligned. This is potentially 492 * dangerous operation, it's responsibility of the calling 493 * code to make sure enough space is reserved. 494 */ 495 invalidate_dcache_range((uint32_t)buffer, 496 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN)); 497 498 /* Check that the TD processing happened */ 499 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) 500 printf("EHCI timed out on TD - token=%#x\n", token); 501 502 /* Disable async schedule. */ 503 cmd = ehci_readl(&hcor->or_usbcmd); 504 cmd &= ~CMD_ASE; 505 ehci_writel(&hcor->or_usbcmd, cmd); 506 507 ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, 0, 508 100 * 1000); 509 if (ret < 0) { 510 printf("EHCI fail timeout STS_ASS reset\n"); 511 goto fail; 512 } 513 514 token = hc32_to_cpu(qh->qh_overlay.qt_token); 515 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) { 516 debug("TOKEN=%#x\n", token); 517 switch (QT_TOKEN_GET_STATUS(token) & 518 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) { 519 case 0: 520 toggle = QT_TOKEN_GET_DT(token); 521 usb_settoggle(dev, usb_pipeendpoint(pipe), 522 usb_pipeout(pipe), toggle); 523 dev->status = 0; 524 break; 525 case QT_TOKEN_STATUS_HALTED: 526 dev->status = USB_ST_STALLED; 527 break; 528 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR: 529 case QT_TOKEN_STATUS_DATBUFERR: 530 dev->status = USB_ST_BUF_ERR; 531 break; 532 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET: 533 case QT_TOKEN_STATUS_BABBLEDET: 534 dev->status = USB_ST_BABBLE_DET; 535 break; 536 default: 537 dev->status = USB_ST_CRC_ERR; 538 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED) 539 dev->status |= USB_ST_STALLED; 540 break; 541 } 542 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token); 543 } else { 544 dev->act_len = 0; 545 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", 546 dev->devnum, ehci_readl(&hcor->or_usbsts), 547 ehci_readl(&hcor->or_portsc[0]), 548 ehci_readl(&hcor->or_portsc[1])); 549 } 550 551 free(qtd); 552 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; 553 554 fail: 555 free(qtd); 556 return -1; 557 } 558 559 static inline int min3(int a, int b, int c) 560 { 561 562 if (b < a) 563 a = b; 564 if (c < a) 565 a = c; 566 return a; 567 } 568 569 int 570 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, 571 int length, struct devrequest *req) 572 { 573 uint8_t tmpbuf[4]; 574 u16 typeReq; 575 void *srcptr = NULL; 576 int len, srclen; 577 uint32_t reg; 578 uint32_t *status_reg; 579 580 if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { 581 printf("The request port(%d) is not configured\n", 582 le16_to_cpu(req->index) - 1); 583 return -1; 584 } 585 status_reg = (uint32_t *)&hcor->or_portsc[ 586 le16_to_cpu(req->index) - 1]; 587 srclen = 0; 588 589 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", 590 req->request, req->request, 591 req->requesttype, req->requesttype, 592 le16_to_cpu(req->value), le16_to_cpu(req->index)); 593 594 typeReq = req->request | req->requesttype << 8; 595 596 switch (typeReq) { 597 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 598 switch (le16_to_cpu(req->value) >> 8) { 599 case USB_DT_DEVICE: 600 debug("USB_DT_DEVICE request\n"); 601 srcptr = &descriptor.device; 602 srclen = descriptor.device.bLength; 603 break; 604 case USB_DT_CONFIG: 605 debug("USB_DT_CONFIG config\n"); 606 srcptr = &descriptor.config; 607 srclen = descriptor.config.bLength + 608 descriptor.interface.bLength + 609 descriptor.endpoint.bLength; 610 break; 611 case USB_DT_STRING: 612 debug("USB_DT_STRING config\n"); 613 switch (le16_to_cpu(req->value) & 0xff) { 614 case 0: /* Language */ 615 srcptr = "\4\3\1\0"; 616 srclen = 4; 617 break; 618 case 1: /* Vendor */ 619 srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; 620 srclen = 14; 621 break; 622 case 2: /* Product */ 623 srcptr = "\52\3E\0H\0C\0I\0 " 624 "\0H\0o\0s\0t\0 " 625 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 626 srclen = 42; 627 break; 628 default: 629 debug("unknown value DT_STRING %x\n", 630 le16_to_cpu(req->value)); 631 goto unknown; 632 } 633 break; 634 default: 635 debug("unknown value %x\n", le16_to_cpu(req->value)); 636 goto unknown; 637 } 638 break; 639 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 640 switch (le16_to_cpu(req->value) >> 8) { 641 case USB_DT_HUB: 642 debug("USB_DT_HUB config\n"); 643 srcptr = &descriptor.hub; 644 srclen = descriptor.hub.bLength; 645 break; 646 default: 647 debug("unknown value %x\n", le16_to_cpu(req->value)); 648 goto unknown; 649 } 650 break; 651 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 652 debug("USB_REQ_SET_ADDRESS\n"); 653 rootdev = le16_to_cpu(req->value); 654 break; 655 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 656 debug("USB_REQ_SET_CONFIGURATION\n"); 657 /* Nothing to do */ 658 break; 659 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 660 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 661 tmpbuf[1] = 0; 662 srcptr = tmpbuf; 663 srclen = 2; 664 break; 665 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 666 memset(tmpbuf, 0, 4); 667 reg = ehci_readl(status_reg); 668 if (reg & EHCI_PS_CS) 669 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 670 if (reg & EHCI_PS_PE) 671 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 672 if (reg & EHCI_PS_SUSP) 673 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 674 if (reg & EHCI_PS_OCA) 675 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 676 if (reg & EHCI_PS_PR) 677 tmpbuf[0] |= USB_PORT_STAT_RESET; 678 if (reg & EHCI_PS_PP) 679 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 680 681 if (ehci_is_TDI()) { 682 switch (PORTSC_PSPD(reg)) { 683 case PORTSC_PSPD_FS: 684 break; 685 case PORTSC_PSPD_LS: 686 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 687 break; 688 case PORTSC_PSPD_HS: 689 default: 690 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 691 break; 692 } 693 } else { 694 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 695 } 696 697 if (reg & EHCI_PS_CSC) 698 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 699 if (reg & EHCI_PS_PEC) 700 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 701 if (reg & EHCI_PS_OCC) 702 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 703 if (portreset & (1 << le16_to_cpu(req->index))) 704 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 705 706 srcptr = tmpbuf; 707 srclen = 4; 708 break; 709 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 710 reg = ehci_readl(status_reg); 711 reg &= ~EHCI_PS_CLEAR; 712 switch (le16_to_cpu(req->value)) { 713 case USB_PORT_FEAT_ENABLE: 714 reg |= EHCI_PS_PE; 715 ehci_writel(status_reg, reg); 716 break; 717 case USB_PORT_FEAT_POWER: 718 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) { 719 reg |= EHCI_PS_PP; 720 ehci_writel(status_reg, reg); 721 } 722 break; 723 case USB_PORT_FEAT_RESET: 724 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && 725 !ehci_is_TDI() && 726 EHCI_PS_IS_LOWSPEED(reg)) { 727 /* Low speed device, give up ownership. */ 728 debug("port %d low speed --> companion\n", 729 req->index - 1); 730 reg |= EHCI_PS_PO; 731 ehci_writel(status_reg, reg); 732 break; 733 } else { 734 int ret; 735 736 reg |= EHCI_PS_PR; 737 reg &= ~EHCI_PS_PE; 738 ehci_writel(status_reg, reg); 739 /* 740 * caller must wait, then call GetPortStatus 741 * usb 2.0 specification say 50 ms resets on 742 * root 743 */ 744 ehci_powerup_fixup(status_reg, ®); 745 746 ehci_writel(status_reg, reg & ~EHCI_PS_PR); 747 /* 748 * A host controller must terminate the reset 749 * and stabilize the state of the port within 750 * 2 milliseconds 751 */ 752 ret = handshake(status_reg, EHCI_PS_PR, 0, 753 2 * 1000); 754 if (!ret) 755 portreset |= 756 1 << le16_to_cpu(req->index); 757 else 758 printf("port(%d) reset error\n", 759 le16_to_cpu(req->index) - 1); 760 } 761 break; 762 default: 763 debug("unknown feature %x\n", le16_to_cpu(req->value)); 764 goto unknown; 765 } 766 /* unblock posted writes */ 767 (void) ehci_readl(&hcor->or_usbcmd); 768 break; 769 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 770 reg = ehci_readl(status_reg); 771 switch (le16_to_cpu(req->value)) { 772 case USB_PORT_FEAT_ENABLE: 773 reg &= ~EHCI_PS_PE; 774 break; 775 case USB_PORT_FEAT_C_ENABLE: 776 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE; 777 break; 778 case USB_PORT_FEAT_POWER: 779 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) 780 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP); 781 case USB_PORT_FEAT_C_CONNECTION: 782 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC; 783 break; 784 case USB_PORT_FEAT_OVER_CURRENT: 785 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC; 786 break; 787 case USB_PORT_FEAT_C_RESET: 788 portreset &= ~(1 << le16_to_cpu(req->index)); 789 break; 790 default: 791 debug("unknown feature %x\n", le16_to_cpu(req->value)); 792 goto unknown; 793 } 794 ehci_writel(status_reg, reg); 795 /* unblock posted write */ 796 (void) ehci_readl(&hcor->or_usbcmd); 797 break; 798 default: 799 debug("Unknown request\n"); 800 goto unknown; 801 } 802 803 mdelay(1); 804 len = min3(srclen, le16_to_cpu(req->length), length); 805 if (srcptr != NULL && len > 0) 806 memcpy(buffer, srcptr, len); 807 else 808 debug("Len is 0\n"); 809 810 dev->act_len = len; 811 dev->status = 0; 812 return 0; 813 814 unknown: 815 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", 816 req->requesttype, req->request, le16_to_cpu(req->value), 817 le16_to_cpu(req->index), le16_to_cpu(req->length)); 818 819 dev->act_len = 0; 820 dev->status = USB_ST_STALLED; 821 return -1; 822 } 823 824 int usb_lowlevel_stop(void) 825 { 826 return ehci_hcd_stop(); 827 } 828 829 int usb_lowlevel_init(void) 830 { 831 uint32_t reg; 832 uint32_t cmd; 833 834 if (ehci_hcd_init()) 835 return -1; 836 837 /* EHCI spec section 4.1 */ 838 if (ehci_reset()) 839 return -1; 840 841 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) 842 if (ehci_hcd_init()) 843 return -1; 844 #endif 845 846 /* Set head of reclaim list */ 847 memset(qh_list, 0, sizeof(*qh_list)); 848 qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); 849 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) | 850 QH_ENDPT1_EPS(USB_SPEED_HIGH)); 851 qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); 852 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 853 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 854 qh_list->qh_overlay.qt_token = 855 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED)); 856 857 reg = ehci_readl(&hccr->cr_hcsparams); 858 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); 859 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 860 /* Port Indicators */ 861 if (HCS_INDICATOR(reg)) 862 descriptor.hub.wHubCharacteristics |= 0x80; 863 /* Port Power Control */ 864 if (HCS_PPC(reg)) 865 descriptor.hub.wHubCharacteristics |= 0x01; 866 867 /* Start the host controller. */ 868 cmd = ehci_readl(&hcor->or_usbcmd); 869 /* 870 * Philips, Intel, and maybe others need CMD_RUN before the 871 * root hub will detect new devices (why?); NEC doesn't 872 */ 873 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 874 cmd |= CMD_RUN; 875 ehci_writel(&hcor->or_usbcmd, cmd); 876 877 /* take control over the ports */ 878 cmd = ehci_readl(&hcor->or_configflag); 879 cmd |= FLAG_CF; 880 ehci_writel(&hcor->or_configflag, cmd); 881 /* unblock posted write */ 882 cmd = ehci_readl(&hcor->or_usbcmd); 883 mdelay(5); 884 reg = HC_VERSION(ehci_readl(&hccr->cr_capbase)); 885 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); 886 887 rootdev = 0; 888 889 return 0; 890 } 891 892 int 893 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 894 int length) 895 { 896 897 if (usb_pipetype(pipe) != PIPE_BULK) { 898 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 899 return -1; 900 } 901 return ehci_submit_async(dev, pipe, buffer, length, NULL); 902 } 903 904 int 905 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 906 int length, struct devrequest *setup) 907 { 908 909 if (usb_pipetype(pipe) != PIPE_CONTROL) { 910 debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); 911 return -1; 912 } 913 914 if (usb_pipedevice(pipe) == rootdev) { 915 if (!rootdev) 916 dev->speed = USB_SPEED_HIGH; 917 return ehci_submit_root(dev, pipe, buffer, length, setup); 918 } 919 return ehci_submit_async(dev, pipe, buffer, length, setup); 920 } 921 922 int 923 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 924 int length, int interval) 925 { 926 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", 927 dev, pipe, buffer, length, interval); 928 929 /* 930 * Interrupt transfers requiring several transactions are not supported 931 * because bInterval is ignored. 932 * 933 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 934 * if several qTDs are required, while the USB specification does not 935 * constrain this for interrupt transfers. That means that 936 * ehci_submit_async() would support interrupt transfers requiring 937 * several transactions only as long as the transfer size does not 938 * require more than a single qTD. 939 */ 940 if (length > usb_maxpacket(dev, pipe)) { 941 printf("%s: Interrupt transfers requiring several transactions " 942 "are not supported.\n", __func__); 943 return -1; 944 } 945 return ehci_submit_async(dev, pipe, buffer, length, NULL); 946 } 947