1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Excito Elektronik i Skåne AB 4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 5 * 6 * All rights reserved. 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 #include <common.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <asm/byteorder.h> 14 #include <asm/unaligned.h> 15 #include <usb.h> 16 #include <asm/io.h> 17 #include <malloc.h> 18 #include <memalign.h> 19 #include <watchdog.h> 20 #include <linux/compiler.h> 21 22 #include "ehci.h" 23 24 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 25 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 26 #endif 27 28 /* 29 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt. 30 * Let's time out after 8 to have a little safety margin on top of that. 31 */ 32 #define HCHALT_TIMEOUT (8 * 1000) 33 34 #ifndef CONFIG_DM_USB 35 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; 36 #endif 37 38 #define ALIGN_END_ADDR(type, ptr, size) \ 39 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN)) 40 41 static struct descriptor { 42 struct usb_hub_descriptor hub; 43 struct usb_device_descriptor device; 44 struct usb_linux_config_descriptor config; 45 struct usb_linux_interface_descriptor interface; 46 struct usb_endpoint_descriptor endpoint; 47 } __attribute__ ((packed)) descriptor = { 48 { 49 0x8, /* bDescLength */ 50 0x29, /* bDescriptorType: hub descriptor */ 51 2, /* bNrPorts -- runtime modified */ 52 0, /* wHubCharacteristics */ 53 10, /* bPwrOn2PwrGood */ 54 0, /* bHubCntrCurrent */ 55 {}, /* Device removable */ 56 {} /* at most 7 ports! XXX */ 57 }, 58 { 59 0x12, /* bLength */ 60 1, /* bDescriptorType: UDESC_DEVICE */ 61 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 62 9, /* bDeviceClass: UDCLASS_HUB */ 63 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 64 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 65 64, /* bMaxPacketSize: 64 bytes */ 66 0x0000, /* idVendor */ 67 0x0000, /* idProduct */ 68 cpu_to_le16(0x0100), /* bcdDevice */ 69 1, /* iManufacturer */ 70 2, /* iProduct */ 71 0, /* iSerialNumber */ 72 1 /* bNumConfigurations: 1 */ 73 }, 74 { 75 0x9, 76 2, /* bDescriptorType: UDESC_CONFIG */ 77 cpu_to_le16(0x19), 78 1, /* bNumInterface */ 79 1, /* bConfigurationValue */ 80 0, /* iConfiguration */ 81 0x40, /* bmAttributes: UC_SELF_POWER */ 82 0 /* bMaxPower */ 83 }, 84 { 85 0x9, /* bLength */ 86 4, /* bDescriptorType: UDESC_INTERFACE */ 87 0, /* bInterfaceNumber */ 88 0, /* bAlternateSetting */ 89 1, /* bNumEndpoints */ 90 9, /* bInterfaceClass: UICLASS_HUB */ 91 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 92 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 93 0 /* iInterface */ 94 }, 95 { 96 0x7, /* bLength */ 97 5, /* bDescriptorType: UDESC_ENDPOINT */ 98 0x81, /* bEndpointAddress: 99 * UE_DIR_IN | EHCI_INTR_ENDPT 100 */ 101 3, /* bmAttributes: UE_INTERRUPT */ 102 8, /* wMaxPacketSize */ 103 255 /* bInterval */ 104 }, 105 }; 106 107 #if defined(CONFIG_EHCI_IS_TDI) 108 #define ehci_is_TDI() (1) 109 #else 110 #define ehci_is_TDI() (0) 111 #endif 112 113 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev) 114 { 115 #ifdef CONFIG_DM_USB 116 return dev_get_priv(usb_get_bus(udev->dev)); 117 #else 118 return udev->controller; 119 #endif 120 } 121 122 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 123 { 124 return PORTSC_PSPD(reg); 125 } 126 127 static void ehci_set_usbmode(struct ehci_ctrl *ctrl) 128 { 129 uint32_t tmp; 130 uint32_t *reg_ptr; 131 132 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE); 133 tmp = ehci_readl(reg_ptr); 134 tmp |= USBMODE_CM_HC; 135 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) 136 tmp |= USBMODE_BE; 137 #endif 138 ehci_writel(reg_ptr, tmp); 139 } 140 141 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, 142 uint32_t *reg) 143 { 144 mdelay(50); 145 } 146 147 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) 148 { 149 if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { 150 /* Printing the message would cause a scan failure! */ 151 debug("The request port(%u) is not configured\n", port); 152 return NULL; 153 } 154 155 return (uint32_t *)&ctrl->hcor->or_portsc[port]; 156 } 157 158 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) 159 { 160 uint32_t result; 161 do { 162 result = ehci_readl(ptr); 163 udelay(5); 164 if (result == ~(uint32_t)0) 165 return -1; 166 result &= mask; 167 if (result == done) 168 return 0; 169 usec--; 170 } while (usec > 0); 171 return -1; 172 } 173 174 static int ehci_reset(struct ehci_ctrl *ctrl) 175 { 176 uint32_t cmd; 177 int ret = 0; 178 179 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 180 cmd = (cmd & ~CMD_RUN) | CMD_RESET; 181 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 182 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd, 183 CMD_RESET, 0, 250 * 1000); 184 if (ret < 0) { 185 printf("EHCI fail to reset\n"); 186 goto out; 187 } 188 189 if (ehci_is_TDI()) 190 ctrl->ops.set_usb_mode(ctrl); 191 192 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH 193 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning); 194 cmd &= ~TXFIFO_THRESH_MASK; 195 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); 196 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd); 197 #endif 198 out: 199 return ret; 200 } 201 202 static int ehci_shutdown(struct ehci_ctrl *ctrl) 203 { 204 int i, ret = 0; 205 uint32_t cmd, reg; 206 207 if (!ctrl || !ctrl->hcor) 208 return -EINVAL; 209 210 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 211 cmd &= ~(CMD_PSE | CMD_ASE); 212 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 213 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0, 214 100 * 1000); 215 216 if (!ret) { 217 for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) { 218 reg = ehci_readl(&ctrl->hcor->or_portsc[i]); 219 reg |= EHCI_PS_SUSP; 220 ehci_writel(&ctrl->hcor->or_portsc[i], reg); 221 } 222 223 cmd &= ~CMD_RUN; 224 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 225 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT, 226 HCHALT_TIMEOUT); 227 } 228 229 if (ret) 230 puts("EHCI failed to shut down host controller.\n"); 231 232 return ret; 233 } 234 235 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) 236 { 237 uint32_t delta, next; 238 uint32_t addr = (unsigned long)buf; 239 int idx; 240 241 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN)) 242 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf); 243 244 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN)); 245 246 idx = 0; 247 while (idx < QT_BUFFER_CNT) { 248 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr)); 249 td->qt_buffer_hi[idx] = 0; 250 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1); 251 delta = next - addr; 252 if (delta >= sz) 253 break; 254 sz -= delta; 255 addr = next; 256 idx++; 257 } 258 259 if (idx == QT_BUFFER_CNT) { 260 printf("out of buffer pointers (%zu bytes left)\n", sz); 261 return -1; 262 } 263 264 return 0; 265 } 266 267 static inline u8 ehci_encode_speed(enum usb_device_speed speed) 268 { 269 #define QH_HIGH_SPEED 2 270 #define QH_FULL_SPEED 0 271 #define QH_LOW_SPEED 1 272 if (speed == USB_SPEED_HIGH) 273 return QH_HIGH_SPEED; 274 if (speed == USB_SPEED_LOW) 275 return QH_LOW_SPEED; 276 return QH_FULL_SPEED; 277 } 278 279 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev, 280 struct QH *qh) 281 { 282 uint8_t portnr = 0; 283 uint8_t hubaddr = 0; 284 285 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL) 286 return; 287 288 usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr); 289 290 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) | 291 QH_ENDPT2_HUBADDR(hubaddr)); 292 } 293 294 static int 295 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, 296 int length, struct devrequest *req) 297 { 298 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN); 299 struct qTD *qtd; 300 int qtd_count = 0; 301 int qtd_counter = 0; 302 volatile struct qTD *vtd; 303 unsigned long ts; 304 uint32_t *tdp; 305 uint32_t endpt, maxpacket, token, usbsts; 306 uint32_t c, toggle; 307 uint32_t cmd; 308 int timeout; 309 int ret = 0; 310 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 311 312 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, 313 buffer, length, req); 314 if (req != NULL) 315 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", 316 req->request, req->request, 317 req->requesttype, req->requesttype, 318 le16_to_cpu(req->value), le16_to_cpu(req->value), 319 le16_to_cpu(req->index)); 320 321 #define PKT_ALIGN 512 322 /* 323 * The USB transfer is split into qTD transfers. Eeach qTD transfer is 324 * described by a transfer descriptor (the qTD). The qTDs form a linked 325 * list with a queue head (QH). 326 * 327 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot 328 * have its beginning in a qTD transfer and its end in the following 329 * one, so the qTD transfer lengths have to be chosen accordingly. 330 * 331 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to 332 * single pages. The first data buffer can start at any offset within a 333 * page (not considering the cache-line alignment issues), while the 334 * following buffers must be page-aligned. There is no alignment 335 * constraint on the size of a qTD transfer. 336 */ 337 if (req != NULL) 338 /* 1 qTD will be needed for SETUP, and 1 for ACK. */ 339 qtd_count += 1 + 1; 340 if (length > 0 || req == NULL) { 341 /* 342 * Determine the qTD transfer size that will be used for the 343 * data payload (not considering the first qTD transfer, which 344 * may be longer or shorter, and the final one, which may be 345 * shorter). 346 * 347 * In order to keep each packet within a qTD transfer, the qTD 348 * transfer size is aligned to PKT_ALIGN, which is a multiple of 349 * wMaxPacketSize (except in some cases for interrupt transfers, 350 * see comment in submit_int_msg()). 351 * 352 * By default, i.e. if the input buffer is aligned to PKT_ALIGN, 353 * QT_BUFFER_CNT full pages will be used. 354 */ 355 int xfr_sz = QT_BUFFER_CNT; 356 /* 357 * However, if the input buffer is not aligned to PKT_ALIGN, the 358 * qTD transfer size will be one page shorter, and the first qTD 359 * data buffer of each transfer will be page-unaligned. 360 */ 361 if ((unsigned long)buffer & (PKT_ALIGN - 1)) 362 xfr_sz--; 363 /* Convert the qTD transfer size to bytes. */ 364 xfr_sz *= EHCI_PAGE_SIZE; 365 /* 366 * Approximate by excess the number of qTDs that will be 367 * required for the data payload. The exact formula is way more 368 * complicated and saves at most 2 qTDs, i.e. a total of 128 369 * bytes. 370 */ 371 qtd_count += 2 + length / xfr_sz; 372 } 373 /* 374 * Threshold value based on the worst-case total size of the allocated qTDs for 375 * a mass-storage transfer of 65535 blocks of 512 bytes. 376 */ 377 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024 378 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI 379 #endif 380 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD)); 381 if (qtd == NULL) { 382 printf("unable to allocate TDs\n"); 383 return -1; 384 } 385 386 memset(qh, 0, sizeof(struct QH)); 387 memset(qtd, 0, qtd_count * sizeof(*qtd)); 388 389 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 390 391 /* 392 * Setup QH (3.6 in ehci-r10.pdf) 393 * 394 * qh_link ................. 03-00 H 395 * qh_endpt1 ............... 07-04 H 396 * qh_endpt2 ............... 0B-08 H 397 * - qh_curtd 398 * qh_overlay.qt_next ...... 13-10 H 399 * - qh_overlay.qt_altnext 400 */ 401 qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH); 402 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe); 403 maxpacket = usb_maxpacket(dev, pipe); 404 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) | 405 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) | 406 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) | 407 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | 408 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | 409 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); 410 qh->qh_endpt1 = cpu_to_hc32(endpt); 411 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); 412 qh->qh_endpt2 = cpu_to_hc32(endpt); 413 ehci_update_endpt2_dev_n_port(dev, qh); 414 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 415 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 416 417 tdp = &qh->qh_overlay.qt_next; 418 if (req != NULL) { 419 /* 420 * Setup request qTD (3.5 in ehci-r10.pdf) 421 * 422 * qt_next ................ 03-00 H 423 * qt_altnext ............. 07-04 H 424 * qt_token ............... 0B-08 H 425 * 426 * [ buffer, buffer_hi ] loaded with "req". 427 */ 428 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 429 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 430 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) | 431 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 432 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) | 433 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 434 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 435 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) { 436 printf("unable to construct SETUP TD\n"); 437 goto fail; 438 } 439 /* Update previous qTD! */ 440 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter])); 441 tdp = &qtd[qtd_counter++].qt_next; 442 toggle = 1; 443 } 444 445 if (length > 0 || req == NULL) { 446 uint8_t *buf_ptr = buffer; 447 int left_length = length; 448 449 do { 450 /* 451 * Determine the size of this qTD transfer. By default, 452 * QT_BUFFER_CNT full pages can be used. 453 */ 454 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE; 455 /* 456 * However, if the input buffer is not page-aligned, the 457 * portion of the first page before the buffer start 458 * offset within that page is unusable. 459 */ 460 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1); 461 /* 462 * In order to keep each packet within a qTD transfer, 463 * align the qTD transfer size to PKT_ALIGN. 464 */ 465 xfr_bytes &= ~(PKT_ALIGN - 1); 466 /* 467 * This transfer may be shorter than the available qTD 468 * transfer size that has just been computed. 469 */ 470 xfr_bytes = min(xfr_bytes, left_length); 471 472 /* 473 * Setup request qTD (3.5 in ehci-r10.pdf) 474 * 475 * qt_next ................ 03-00 H 476 * qt_altnext ............. 07-04 H 477 * qt_token ............... 0B-08 H 478 * 479 * [ buffer, buffer_hi ] loaded with "buffer". 480 */ 481 qtd[qtd_counter].qt_next = 482 cpu_to_hc32(QT_NEXT_TERMINATE); 483 qtd[qtd_counter].qt_altnext = 484 cpu_to_hc32(QT_NEXT_TERMINATE); 485 token = QT_TOKEN_DT(toggle) | 486 QT_TOKEN_TOTALBYTES(xfr_bytes) | 487 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) | 488 QT_TOKEN_CERR(3) | 489 QT_TOKEN_PID(usb_pipein(pipe) ? 490 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) | 491 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 492 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 493 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr, 494 xfr_bytes)) { 495 printf("unable to construct DATA TD\n"); 496 goto fail; 497 } 498 /* Update previous qTD! */ 499 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter])); 500 tdp = &qtd[qtd_counter++].qt_next; 501 /* 502 * Data toggle has to be adjusted since the qTD transfer 503 * size is not always an even multiple of 504 * wMaxPacketSize. 505 */ 506 if ((xfr_bytes / maxpacket) & 1) 507 toggle ^= 1; 508 buf_ptr += xfr_bytes; 509 left_length -= xfr_bytes; 510 } while (left_length > 0); 511 } 512 513 if (req != NULL) { 514 /* 515 * Setup request qTD (3.5 in ehci-r10.pdf) 516 * 517 * qt_next ................ 03-00 H 518 * qt_altnext ............. 07-04 H 519 * qt_token ............... 0B-08 H 520 */ 521 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 522 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 523 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) | 524 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 525 QT_TOKEN_PID(usb_pipein(pipe) ? 526 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) | 527 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 528 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 529 /* Update previous qTD! */ 530 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter])); 531 tdp = &qtd[qtd_counter++].qt_next; 532 } 533 534 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH); 535 536 /* Flush dcache */ 537 flush_dcache_range((unsigned long)&ctrl->qh_list, 538 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 539 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1)); 540 flush_dcache_range((unsigned long)qtd, 541 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 542 543 /* Set async. queue head pointer. */ 544 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(&ctrl->qh_list)); 545 546 usbsts = ehci_readl(&ctrl->hcor->or_usbsts); 547 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f)); 548 549 /* Enable async. schedule. */ 550 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 551 cmd |= CMD_ASE; 552 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 553 554 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS, 555 100 * 1000); 556 if (ret < 0) { 557 printf("EHCI fail timeout STS_ASS set\n"); 558 goto fail; 559 } 560 561 /* Wait for TDs to be processed. */ 562 ts = get_timer(0); 563 vtd = &qtd[qtd_counter - 1]; 564 timeout = USB_TIMEOUT_MS(pipe); 565 do { 566 /* Invalidate dcache */ 567 invalidate_dcache_range((unsigned long)&ctrl->qh_list, 568 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 569 invalidate_dcache_range((unsigned long)qh, 570 ALIGN_END_ADDR(struct QH, qh, 1)); 571 invalidate_dcache_range((unsigned long)qtd, 572 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 573 574 token = hc32_to_cpu(vtd->qt_token); 575 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) 576 break; 577 WATCHDOG_RESET(); 578 } while (get_timer(ts) < timeout); 579 580 /* 581 * Invalidate the memory area occupied by buffer 582 * Don't try to fix the buffer alignment, if it isn't properly 583 * aligned it's upper layer's fault so let invalidate_dcache_range() 584 * vow about it. But we have to fix the length as it's actual 585 * transfer length and can be unaligned. This is potentially 586 * dangerous operation, it's responsibility of the calling 587 * code to make sure enough space is reserved. 588 */ 589 invalidate_dcache_range((unsigned long)buffer, 590 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN)); 591 592 /* Check that the TD processing happened */ 593 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) 594 printf("EHCI timed out on TD - token=%#x\n", token); 595 596 /* Disable async schedule. */ 597 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 598 cmd &= ~CMD_ASE; 599 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 600 601 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0, 602 100 * 1000); 603 if (ret < 0) { 604 printf("EHCI fail timeout STS_ASS reset\n"); 605 goto fail; 606 } 607 608 token = hc32_to_cpu(qh->qh_overlay.qt_token); 609 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) { 610 debug("TOKEN=%#x\n", token); 611 switch (QT_TOKEN_GET_STATUS(token) & 612 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) { 613 case 0: 614 toggle = QT_TOKEN_GET_DT(token); 615 usb_settoggle(dev, usb_pipeendpoint(pipe), 616 usb_pipeout(pipe), toggle); 617 dev->status = 0; 618 break; 619 case QT_TOKEN_STATUS_HALTED: 620 dev->status = USB_ST_STALLED; 621 break; 622 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR: 623 case QT_TOKEN_STATUS_DATBUFERR: 624 dev->status = USB_ST_BUF_ERR; 625 break; 626 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET: 627 case QT_TOKEN_STATUS_BABBLEDET: 628 dev->status = USB_ST_BABBLE_DET; 629 break; 630 default: 631 dev->status = USB_ST_CRC_ERR; 632 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED) 633 dev->status |= USB_ST_STALLED; 634 break; 635 } 636 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token); 637 } else { 638 dev->act_len = 0; 639 #ifndef CONFIG_USB_EHCI_FARADAY 640 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", 641 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts), 642 ehci_readl(&ctrl->hcor->or_portsc[0]), 643 ehci_readl(&ctrl->hcor->or_portsc[1])); 644 #endif 645 } 646 647 free(qtd); 648 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; 649 650 fail: 651 free(qtd); 652 return -1; 653 } 654 655 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe, 656 void *buffer, int length, struct devrequest *req) 657 { 658 uint8_t tmpbuf[4]; 659 u16 typeReq; 660 void *srcptr = NULL; 661 int len, srclen; 662 uint32_t reg; 663 uint32_t *status_reg; 664 int port = le16_to_cpu(req->index) & 0xff; 665 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 666 667 srclen = 0; 668 669 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", 670 req->request, req->request, 671 req->requesttype, req->requesttype, 672 le16_to_cpu(req->value), le16_to_cpu(req->index)); 673 674 typeReq = req->request | req->requesttype << 8; 675 676 switch (typeReq) { 677 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 678 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 679 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 680 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1); 681 if (!status_reg) 682 return -1; 683 break; 684 default: 685 status_reg = NULL; 686 break; 687 } 688 689 switch (typeReq) { 690 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 691 switch (le16_to_cpu(req->value) >> 8) { 692 case USB_DT_DEVICE: 693 debug("USB_DT_DEVICE request\n"); 694 srcptr = &descriptor.device; 695 srclen = descriptor.device.bLength; 696 break; 697 case USB_DT_CONFIG: 698 debug("USB_DT_CONFIG config\n"); 699 srcptr = &descriptor.config; 700 srclen = descriptor.config.bLength + 701 descriptor.interface.bLength + 702 descriptor.endpoint.bLength; 703 break; 704 case USB_DT_STRING: 705 debug("USB_DT_STRING config\n"); 706 switch (le16_to_cpu(req->value) & 0xff) { 707 case 0: /* Language */ 708 srcptr = "\4\3\1\0"; 709 srclen = 4; 710 break; 711 case 1: /* Vendor */ 712 srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; 713 srclen = 14; 714 break; 715 case 2: /* Product */ 716 srcptr = "\52\3E\0H\0C\0I\0 " 717 "\0H\0o\0s\0t\0 " 718 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 719 srclen = 42; 720 break; 721 default: 722 debug("unknown value DT_STRING %x\n", 723 le16_to_cpu(req->value)); 724 goto unknown; 725 } 726 break; 727 default: 728 debug("unknown value %x\n", le16_to_cpu(req->value)); 729 goto unknown; 730 } 731 break; 732 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 733 switch (le16_to_cpu(req->value) >> 8) { 734 case USB_DT_HUB: 735 debug("USB_DT_HUB config\n"); 736 srcptr = &descriptor.hub; 737 srclen = descriptor.hub.bLength; 738 break; 739 default: 740 debug("unknown value %x\n", le16_to_cpu(req->value)); 741 goto unknown; 742 } 743 break; 744 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 745 debug("USB_REQ_SET_ADDRESS\n"); 746 ctrl->rootdev = le16_to_cpu(req->value); 747 break; 748 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 749 debug("USB_REQ_SET_CONFIGURATION\n"); 750 /* Nothing to do */ 751 break; 752 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 753 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 754 tmpbuf[1] = 0; 755 srcptr = tmpbuf; 756 srclen = 2; 757 break; 758 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 759 memset(tmpbuf, 0, 4); 760 reg = ehci_readl(status_reg); 761 if (reg & EHCI_PS_CS) 762 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 763 if (reg & EHCI_PS_PE) 764 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 765 if (reg & EHCI_PS_SUSP) 766 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 767 if (reg & EHCI_PS_OCA) 768 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 769 if (reg & EHCI_PS_PR) 770 tmpbuf[0] |= USB_PORT_STAT_RESET; 771 if (reg & EHCI_PS_PP) 772 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 773 774 if (ehci_is_TDI()) { 775 switch (ctrl->ops.get_port_speed(ctrl, reg)) { 776 case PORTSC_PSPD_FS: 777 break; 778 case PORTSC_PSPD_LS: 779 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 780 break; 781 case PORTSC_PSPD_HS: 782 default: 783 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 784 break; 785 } 786 } else { 787 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 788 } 789 790 if (reg & EHCI_PS_CSC) 791 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 792 if (reg & EHCI_PS_PEC) 793 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 794 if (reg & EHCI_PS_OCC) 795 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 796 if (ctrl->portreset & (1 << port)) 797 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 798 799 srcptr = tmpbuf; 800 srclen = 4; 801 break; 802 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 803 reg = ehci_readl(status_reg); 804 reg &= ~EHCI_PS_CLEAR; 805 switch (le16_to_cpu(req->value)) { 806 case USB_PORT_FEAT_ENABLE: 807 reg |= EHCI_PS_PE; 808 ehci_writel(status_reg, reg); 809 break; 810 case USB_PORT_FEAT_POWER: 811 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) { 812 reg |= EHCI_PS_PP; 813 ehci_writel(status_reg, reg); 814 } 815 break; 816 case USB_PORT_FEAT_RESET: 817 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && 818 !ehci_is_TDI() && 819 EHCI_PS_IS_LOWSPEED(reg)) { 820 /* Low speed device, give up ownership. */ 821 debug("port %d low speed --> companion\n", 822 port - 1); 823 reg |= EHCI_PS_PO; 824 ehci_writel(status_reg, reg); 825 return -ENXIO; 826 } else { 827 int ret; 828 829 reg |= EHCI_PS_PR; 830 reg &= ~EHCI_PS_PE; 831 ehci_writel(status_reg, reg); 832 /* 833 * caller must wait, then call GetPortStatus 834 * usb 2.0 specification say 50 ms resets on 835 * root 836 */ 837 ctrl->ops.powerup_fixup(ctrl, status_reg, ®); 838 839 ehci_writel(status_reg, reg & ~EHCI_PS_PR); 840 /* 841 * A host controller must terminate the reset 842 * and stabilize the state of the port within 843 * 2 milliseconds 844 */ 845 ret = handshake(status_reg, EHCI_PS_PR, 0, 846 2 * 1000); 847 if (!ret) { 848 reg = ehci_readl(status_reg); 849 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) 850 == EHCI_PS_CS && !ehci_is_TDI()) { 851 debug("port %d full speed --> companion\n", port - 1); 852 reg &= ~EHCI_PS_CLEAR; 853 reg |= EHCI_PS_PO; 854 ehci_writel(status_reg, reg); 855 return -ENXIO; 856 } else { 857 ctrl->portreset |= 1 << port; 858 } 859 } else { 860 printf("port(%d) reset error\n", 861 port - 1); 862 } 863 } 864 break; 865 case USB_PORT_FEAT_TEST: 866 ehci_shutdown(ctrl); 867 reg &= ~(0xf << 16); 868 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16; 869 ehci_writel(status_reg, reg); 870 break; 871 default: 872 debug("unknown feature %x\n", le16_to_cpu(req->value)); 873 goto unknown; 874 } 875 /* unblock posted writes */ 876 (void) ehci_readl(&ctrl->hcor->or_usbcmd); 877 break; 878 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 879 reg = ehci_readl(status_reg); 880 reg &= ~EHCI_PS_CLEAR; 881 switch (le16_to_cpu(req->value)) { 882 case USB_PORT_FEAT_ENABLE: 883 reg &= ~EHCI_PS_PE; 884 break; 885 case USB_PORT_FEAT_C_ENABLE: 886 reg |= EHCI_PS_PE; 887 break; 888 case USB_PORT_FEAT_POWER: 889 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) 890 reg &= ~EHCI_PS_PP; 891 break; 892 case USB_PORT_FEAT_C_CONNECTION: 893 reg |= EHCI_PS_CSC; 894 break; 895 case USB_PORT_FEAT_OVER_CURRENT: 896 reg |= EHCI_PS_OCC; 897 break; 898 case USB_PORT_FEAT_C_RESET: 899 ctrl->portreset &= ~(1 << port); 900 break; 901 default: 902 debug("unknown feature %x\n", le16_to_cpu(req->value)); 903 goto unknown; 904 } 905 ehci_writel(status_reg, reg); 906 /* unblock posted write */ 907 (void) ehci_readl(&ctrl->hcor->or_usbcmd); 908 break; 909 default: 910 debug("Unknown request\n"); 911 goto unknown; 912 } 913 914 mdelay(1); 915 len = min3(srclen, (int)le16_to_cpu(req->length), length); 916 if (srcptr != NULL && len > 0) 917 memcpy(buffer, srcptr, len); 918 else 919 debug("Len is 0\n"); 920 921 dev->act_len = len; 922 dev->status = 0; 923 return 0; 924 925 unknown: 926 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", 927 req->requesttype, req->request, le16_to_cpu(req->value), 928 le16_to_cpu(req->index), le16_to_cpu(req->length)); 929 930 dev->act_len = 0; 931 dev->status = USB_ST_STALLED; 932 return -1; 933 } 934 935 const struct ehci_ops default_ehci_ops = { 936 .set_usb_mode = ehci_set_usbmode, 937 .get_port_speed = ehci_get_port_speed, 938 .powerup_fixup = ehci_powerup_fixup, 939 .get_portsc_register = ehci_get_portsc_register, 940 }; 941 942 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops) 943 { 944 if (!ops) { 945 ctrl->ops = default_ehci_ops; 946 } else { 947 ctrl->ops = *ops; 948 if (!ctrl->ops.set_usb_mode) 949 ctrl->ops.set_usb_mode = ehci_set_usbmode; 950 if (!ctrl->ops.get_port_speed) 951 ctrl->ops.get_port_speed = ehci_get_port_speed; 952 if (!ctrl->ops.powerup_fixup) 953 ctrl->ops.powerup_fixup = ehci_powerup_fixup; 954 if (!ctrl->ops.get_portsc_register) 955 ctrl->ops.get_portsc_register = 956 ehci_get_portsc_register; 957 } 958 } 959 960 #ifndef CONFIG_DM_USB 961 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops) 962 { 963 struct ehci_ctrl *ctrl = &ehcic[index]; 964 965 ctrl->priv = priv; 966 ehci_setup_ops(ctrl, ops); 967 } 968 969 void *ehci_get_controller_priv(int index) 970 { 971 return ehcic[index].priv; 972 } 973 #endif 974 975 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks) 976 { 977 struct QH *qh_list; 978 struct QH *periodic; 979 uint32_t reg; 980 uint32_t cmd; 981 int i; 982 983 /* Set the high address word (aka segment) for 64-bit controller */ 984 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1) 985 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0); 986 987 qh_list = &ctrl->qh_list; 988 989 /* Set head of reclaim list */ 990 memset(qh_list, 0, sizeof(*qh_list)); 991 qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH); 992 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) | 993 QH_ENDPT1_EPS(USB_SPEED_HIGH)); 994 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 995 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 996 qh_list->qh_overlay.qt_token = 997 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED)); 998 999 flush_dcache_range((unsigned long)qh_list, 1000 ALIGN_END_ADDR(struct QH, qh_list, 1)); 1001 1002 /* Set async. queue head pointer. */ 1003 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list)); 1004 1005 /* 1006 * Set up periodic list 1007 * Step 1: Parent QH for all periodic transfers. 1008 */ 1009 ctrl->periodic_schedules = 0; 1010 periodic = &ctrl->periodic_queue; 1011 memset(periodic, 0, sizeof(*periodic)); 1012 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); 1013 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 1014 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 1015 1016 flush_dcache_range((unsigned long)periodic, 1017 ALIGN_END_ADDR(struct QH, periodic, 1)); 1018 1019 /* 1020 * Step 2: Setup frame-list: Every microframe, USB tries the same list. 1021 * In particular, device specifications on polling frequency 1022 * are disregarded. Keyboards seem to send NAK/NYet reliably 1023 * when polled with an empty buffer. 1024 * 1025 * Split Transactions will be spread across microframes using 1026 * S-mask and C-mask. 1027 */ 1028 if (ctrl->periodic_list == NULL) 1029 ctrl->periodic_list = memalign(4096, 1024 * 4); 1030 1031 if (!ctrl->periodic_list) 1032 return -ENOMEM; 1033 for (i = 0; i < 1024; i++) { 1034 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic 1035 | QH_LINK_TYPE_QH); 1036 } 1037 1038 flush_dcache_range((unsigned long)ctrl->periodic_list, 1039 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list, 1040 1024)); 1041 1042 /* Set periodic list base address */ 1043 ehci_writel(&ctrl->hcor->or_periodiclistbase, 1044 (unsigned long)ctrl->periodic_list); 1045 1046 reg = ehci_readl(&ctrl->hccr->cr_hcsparams); 1047 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); 1048 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 1049 /* Port Indicators */ 1050 if (HCS_INDICATOR(reg)) 1051 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 1052 | 0x80, &descriptor.hub.wHubCharacteristics); 1053 /* Port Power Control */ 1054 if (HCS_PPC(reg)) 1055 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 1056 | 0x01, &descriptor.hub.wHubCharacteristics); 1057 1058 /* Start the host controller. */ 1059 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 1060 /* 1061 * Philips, Intel, and maybe others need CMD_RUN before the 1062 * root hub will detect new devices (why?); NEC doesn't 1063 */ 1064 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 1065 cmd |= CMD_RUN; 1066 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 1067 1068 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) { 1069 /* take control over the ports */ 1070 cmd = ehci_readl(&ctrl->hcor->or_configflag); 1071 cmd |= FLAG_CF; 1072 ehci_writel(&ctrl->hcor->or_configflag, cmd); 1073 } 1074 1075 /* unblock posted write */ 1076 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 1077 mdelay(5); 1078 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase)); 1079 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); 1080 1081 return 0; 1082 } 1083 1084 #ifndef CONFIG_DM_USB 1085 int usb_lowlevel_stop(int index) 1086 { 1087 ehci_shutdown(&ehcic[index]); 1088 return ehci_hcd_stop(index); 1089 } 1090 1091 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1092 { 1093 struct ehci_ctrl *ctrl = &ehcic[index]; 1094 uint tweaks = 0; 1095 int rc; 1096 1097 /** 1098 * Set ops to default_ehci_ops, ehci_hcd_init should call 1099 * ehci_set_controller_priv to change any of these function pointers. 1100 */ 1101 ctrl->ops = default_ehci_ops; 1102 1103 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); 1104 if (rc) 1105 return rc; 1106 if (init == USB_INIT_DEVICE) 1107 goto done; 1108 1109 /* EHCI spec section 4.1 */ 1110 if (ehci_reset(ctrl)) 1111 return -1; 1112 1113 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) 1114 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); 1115 if (rc) 1116 return rc; 1117 #endif 1118 #ifdef CONFIG_USB_EHCI_FARADAY 1119 tweaks |= EHCI_TWEAK_NO_INIT_CF; 1120 #endif 1121 rc = ehci_common_init(ctrl, tweaks); 1122 if (rc) 1123 return rc; 1124 1125 ctrl->rootdev = 0; 1126 done: 1127 *controller = &ehcic[index]; 1128 return 0; 1129 } 1130 #endif 1131 1132 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe, 1133 void *buffer, int length) 1134 { 1135 1136 if (usb_pipetype(pipe) != PIPE_BULK) { 1137 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 1138 return -1; 1139 } 1140 return ehci_submit_async(dev, pipe, buffer, length, NULL); 1141 } 1142 1143 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe, 1144 void *buffer, int length, 1145 struct devrequest *setup) 1146 { 1147 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 1148 1149 if (usb_pipetype(pipe) != PIPE_CONTROL) { 1150 debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); 1151 return -1; 1152 } 1153 1154 if (usb_pipedevice(pipe) == ctrl->rootdev) { 1155 if (!ctrl->rootdev) 1156 dev->speed = USB_SPEED_HIGH; 1157 return ehci_submit_root(dev, pipe, buffer, length, setup); 1158 } 1159 return ehci_submit_async(dev, pipe, buffer, length, setup); 1160 } 1161 1162 struct int_queue { 1163 int elementsize; 1164 unsigned long pipe; 1165 struct QH *first; 1166 struct QH *current; 1167 struct QH *last; 1168 struct qTD *tds; 1169 }; 1170 1171 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f) 1172 1173 static int 1174 enable_periodic(struct ehci_ctrl *ctrl) 1175 { 1176 uint32_t cmd; 1177 struct ehci_hcor *hcor = ctrl->hcor; 1178 int ret; 1179 1180 cmd = ehci_readl(&hcor->or_usbcmd); 1181 cmd |= CMD_PSE; 1182 ehci_writel(&hcor->or_usbcmd, cmd); 1183 1184 ret = handshake((uint32_t *)&hcor->or_usbsts, 1185 STS_PSS, STS_PSS, 100 * 1000); 1186 if (ret < 0) { 1187 printf("EHCI failed: timeout when enabling periodic list\n"); 1188 return -ETIMEDOUT; 1189 } 1190 udelay(1000); 1191 return 0; 1192 } 1193 1194 static int 1195 disable_periodic(struct ehci_ctrl *ctrl) 1196 { 1197 uint32_t cmd; 1198 struct ehci_hcor *hcor = ctrl->hcor; 1199 int ret; 1200 1201 cmd = ehci_readl(&hcor->or_usbcmd); 1202 cmd &= ~CMD_PSE; 1203 ehci_writel(&hcor->or_usbcmd, cmd); 1204 1205 ret = handshake((uint32_t *)&hcor->or_usbsts, 1206 STS_PSS, 0, 100 * 1000); 1207 if (ret < 0) { 1208 printf("EHCI failed: timeout when disabling periodic list\n"); 1209 return -ETIMEDOUT; 1210 } 1211 return 0; 1212 } 1213 1214 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev, 1215 unsigned long pipe, int queuesize, int elementsize, 1216 void *buffer, int interval) 1217 { 1218 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 1219 struct int_queue *result = NULL; 1220 uint32_t i, toggle; 1221 1222 /* 1223 * Interrupt transfers requiring several transactions are not supported 1224 * because bInterval is ignored. 1225 * 1226 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 1227 * <= PKT_ALIGN if several qTDs are required, while the USB 1228 * specification does not constrain this for interrupt transfers. That 1229 * means that ehci_submit_async() would support interrupt transfers 1230 * requiring several transactions only as long as the transfer size does 1231 * not require more than a single qTD. 1232 */ 1233 if (elementsize > usb_maxpacket(dev, pipe)) { 1234 printf("%s: xfers requiring several transactions are not supported.\n", 1235 __func__); 1236 return NULL; 1237 } 1238 1239 debug("Enter create_int_queue\n"); 1240 if (usb_pipetype(pipe) != PIPE_INTERRUPT) { 1241 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); 1242 return NULL; 1243 } 1244 1245 /* limit to 4 full pages worth of data - 1246 * we can safely fit them in a single TD, 1247 * no matter the alignment 1248 */ 1249 if (elementsize >= 16384) { 1250 debug("too large elements for interrupt transfers\n"); 1251 return NULL; 1252 } 1253 1254 result = malloc(sizeof(*result)); 1255 if (!result) { 1256 debug("ehci intr queue: out of memory\n"); 1257 goto fail1; 1258 } 1259 result->elementsize = elementsize; 1260 result->pipe = pipe; 1261 result->first = memalign(USB_DMA_MINALIGN, 1262 sizeof(struct QH) * queuesize); 1263 if (!result->first) { 1264 debug("ehci intr queue: out of memory\n"); 1265 goto fail2; 1266 } 1267 result->current = result->first; 1268 result->last = result->first + queuesize - 1; 1269 result->tds = memalign(USB_DMA_MINALIGN, 1270 sizeof(struct qTD) * queuesize); 1271 if (!result->tds) { 1272 debug("ehci intr queue: out of memory\n"); 1273 goto fail3; 1274 } 1275 memset(result->first, 0, sizeof(struct QH) * queuesize); 1276 memset(result->tds, 0, sizeof(struct qTD) * queuesize); 1277 1278 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 1279 1280 for (i = 0; i < queuesize; i++) { 1281 struct QH *qh = result->first + i; 1282 struct qTD *td = result->tds + i; 1283 void **buf = &qh->buffer; 1284 1285 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH); 1286 if (i == queuesize - 1) 1287 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); 1288 1289 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td); 1290 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 1291 qh->qh_endpt1 = 1292 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */ 1293 (usb_maxpacket(dev, pipe) << 16) | /* MPS */ 1294 (1 << 14) | 1295 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | 1296 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ 1297 (usb_pipedevice(pipe) << 0)); 1298 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */ 1299 (1 << 0)); /* S-mask: microframe 0 */ 1300 if (dev->speed == USB_SPEED_LOW || 1301 dev->speed == USB_SPEED_FULL) { 1302 /* C-mask: microframes 2-4 */ 1303 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8)); 1304 } 1305 ehci_update_endpt2_dev_n_port(dev, qh); 1306 1307 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 1308 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 1309 debug("communication direction is '%s'\n", 1310 usb_pipein(pipe) ? "in" : "out"); 1311 td->qt_token = cpu_to_hc32( 1312 QT_TOKEN_DT(toggle) | 1313 (elementsize << 16) | 1314 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ 1315 0x80); /* active */ 1316 td->qt_buffer[0] = 1317 cpu_to_hc32((unsigned long)buffer + i * elementsize); 1318 td->qt_buffer[1] = 1319 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff); 1320 td->qt_buffer[2] = 1321 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff); 1322 td->qt_buffer[3] = 1323 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff); 1324 td->qt_buffer[4] = 1325 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff); 1326 1327 *buf = buffer + i * elementsize; 1328 toggle ^= 1; 1329 } 1330 1331 flush_dcache_range((unsigned long)buffer, 1332 ALIGN_END_ADDR(char, buffer, 1333 queuesize * elementsize)); 1334 flush_dcache_range((unsigned long)result->first, 1335 ALIGN_END_ADDR(struct QH, result->first, 1336 queuesize)); 1337 flush_dcache_range((unsigned long)result->tds, 1338 ALIGN_END_ADDR(struct qTD, result->tds, 1339 queuesize)); 1340 1341 if (ctrl->periodic_schedules > 0) { 1342 if (disable_periodic(ctrl) < 0) { 1343 debug("FATAL: periodic should never fail, but did"); 1344 goto fail3; 1345 } 1346 } 1347 1348 /* hook up to periodic list */ 1349 struct QH *list = &ctrl->periodic_queue; 1350 result->last->qh_link = list->qh_link; 1351 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH); 1352 1353 flush_dcache_range((unsigned long)result->last, 1354 ALIGN_END_ADDR(struct QH, result->last, 1)); 1355 flush_dcache_range((unsigned long)list, 1356 ALIGN_END_ADDR(struct QH, list, 1)); 1357 1358 if (enable_periodic(ctrl) < 0) { 1359 debug("FATAL: periodic should never fail, but did"); 1360 goto fail3; 1361 } 1362 ctrl->periodic_schedules++; 1363 1364 debug("Exit create_int_queue\n"); 1365 return result; 1366 fail3: 1367 if (result->tds) 1368 free(result->tds); 1369 fail2: 1370 if (result->first) 1371 free(result->first); 1372 if (result) 1373 free(result); 1374 fail1: 1375 return NULL; 1376 } 1377 1378 static void *_ehci_poll_int_queue(struct usb_device *dev, 1379 struct int_queue *queue) 1380 { 1381 struct QH *cur = queue->current; 1382 struct qTD *cur_td; 1383 uint32_t token, toggle; 1384 unsigned long pipe = queue->pipe; 1385 1386 /* depleted queue */ 1387 if (cur == NULL) { 1388 debug("Exit poll_int_queue with completed queue\n"); 1389 return NULL; 1390 } 1391 /* still active */ 1392 cur_td = &queue->tds[queue->current - queue->first]; 1393 invalidate_dcache_range((unsigned long)cur_td, 1394 ALIGN_END_ADDR(struct qTD, cur_td, 1)); 1395 token = hc32_to_cpu(cur_td->qt_token); 1396 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) { 1397 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token); 1398 return NULL; 1399 } 1400 1401 toggle = QT_TOKEN_GET_DT(token); 1402 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle); 1403 1404 if (!(cur->qh_link & QH_LINK_TERMINATE)) 1405 queue->current++; 1406 else 1407 queue->current = NULL; 1408 1409 invalidate_dcache_range((unsigned long)cur->buffer, 1410 ALIGN_END_ADDR(char, cur->buffer, 1411 queue->elementsize)); 1412 1413 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n", 1414 token, cur, queue->first); 1415 return cur->buffer; 1416 } 1417 1418 /* Do not free buffers associated with QHs, they're owned by someone else */ 1419 static int _ehci_destroy_int_queue(struct usb_device *dev, 1420 struct int_queue *queue) 1421 { 1422 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 1423 int result = -1; 1424 unsigned long timeout; 1425 1426 if (disable_periodic(ctrl) < 0) { 1427 debug("FATAL: periodic should never fail, but did"); 1428 goto out; 1429 } 1430 ctrl->periodic_schedules--; 1431 1432 struct QH *cur = &ctrl->periodic_queue; 1433 timeout = get_timer(0) + 500; /* abort after 500ms */ 1434 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) { 1435 debug("considering %p, with qh_link %x\n", cur, cur->qh_link); 1436 if (NEXT_QH(cur) == queue->first) { 1437 debug("found candidate. removing from chain\n"); 1438 cur->qh_link = queue->last->qh_link; 1439 flush_dcache_range((unsigned long)cur, 1440 ALIGN_END_ADDR(struct QH, cur, 1)); 1441 result = 0; 1442 break; 1443 } 1444 cur = NEXT_QH(cur); 1445 if (get_timer(0) > timeout) { 1446 printf("Timeout destroying interrupt endpoint queue\n"); 1447 result = -1; 1448 goto out; 1449 } 1450 } 1451 1452 if (ctrl->periodic_schedules > 0) { 1453 result = enable_periodic(ctrl); 1454 if (result < 0) 1455 debug("FATAL: periodic should never fail, but did"); 1456 } 1457 1458 out: 1459 free(queue->tds); 1460 free(queue->first); 1461 free(queue); 1462 1463 return result; 1464 } 1465 1466 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe, 1467 void *buffer, int length, int interval) 1468 { 1469 void *backbuffer; 1470 struct int_queue *queue; 1471 unsigned long timeout; 1472 int result = 0, ret; 1473 1474 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", 1475 dev, pipe, buffer, length, interval); 1476 1477 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval); 1478 if (!queue) 1479 return -1; 1480 1481 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1482 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL) 1483 if (get_timer(0) > timeout) { 1484 printf("Timeout poll on interrupt endpoint\n"); 1485 result = -ETIMEDOUT; 1486 break; 1487 } 1488 1489 if (backbuffer != buffer) { 1490 debug("got wrong buffer back (%p instead of %p)\n", 1491 backbuffer, buffer); 1492 return -EINVAL; 1493 } 1494 1495 ret = _ehci_destroy_int_queue(dev, queue); 1496 if (ret < 0) 1497 return ret; 1498 1499 /* everything worked out fine */ 1500 return result; 1501 } 1502 1503 #ifndef CONFIG_DM_USB 1504 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, 1505 void *buffer, int length) 1506 { 1507 return _ehci_submit_bulk_msg(dev, pipe, buffer, length); 1508 } 1509 1510 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1511 int length, struct devrequest *setup) 1512 { 1513 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup); 1514 } 1515 1516 int submit_int_msg(struct usb_device *dev, unsigned long pipe, 1517 void *buffer, int length, int interval) 1518 { 1519 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval); 1520 } 1521 1522 struct int_queue *create_int_queue(struct usb_device *dev, 1523 unsigned long pipe, int queuesize, int elementsize, 1524 void *buffer, int interval) 1525 { 1526 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize, 1527 buffer, interval); 1528 } 1529 1530 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) 1531 { 1532 return _ehci_poll_int_queue(dev, queue); 1533 } 1534 1535 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) 1536 { 1537 return _ehci_destroy_int_queue(dev, queue); 1538 } 1539 #endif 1540 1541 #ifdef CONFIG_DM_USB 1542 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1543 unsigned long pipe, void *buffer, int length, 1544 struct devrequest *setup) 1545 { 1546 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1547 dev->name, udev, udev->dev->name, udev->portnr); 1548 1549 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup); 1550 } 1551 1552 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1553 unsigned long pipe, void *buffer, int length) 1554 { 1555 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1556 return _ehci_submit_bulk_msg(udev, pipe, buffer, length); 1557 } 1558 1559 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1560 unsigned long pipe, void *buffer, int length, 1561 int interval) 1562 { 1563 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1564 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval); 1565 } 1566 1567 static struct int_queue *ehci_create_int_queue(struct udevice *dev, 1568 struct usb_device *udev, unsigned long pipe, int queuesize, 1569 int elementsize, void *buffer, int interval) 1570 { 1571 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1572 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize, 1573 buffer, interval); 1574 } 1575 1576 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev, 1577 struct int_queue *queue) 1578 { 1579 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1580 return _ehci_poll_int_queue(udev, queue); 1581 } 1582 1583 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev, 1584 struct int_queue *queue) 1585 { 1586 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1587 return _ehci_destroy_int_queue(udev, queue); 1588 } 1589 1590 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, 1591 struct ehci_hcor *hcor, const struct ehci_ops *ops, 1592 uint tweaks, enum usb_init_type init) 1593 { 1594 struct usb_bus_priv *priv = dev_get_uclass_priv(dev); 1595 struct ehci_ctrl *ctrl = dev_get_priv(dev); 1596 int ret; 1597 1598 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__, 1599 dev->name, ctrl, hccr, hcor, init); 1600 1601 priv->desc_before_addr = true; 1602 1603 ehci_setup_ops(ctrl, ops); 1604 ctrl->hccr = hccr; 1605 ctrl->hcor = hcor; 1606 ctrl->priv = ctrl; 1607 1608 ctrl->init = init; 1609 if (ctrl->init == USB_INIT_DEVICE) 1610 goto done; 1611 1612 ret = ehci_reset(ctrl); 1613 if (ret) 1614 goto err; 1615 1616 ret = ehci_common_init(ctrl, tweaks); 1617 if (ret) 1618 goto err; 1619 done: 1620 return 0; 1621 err: 1622 free(ctrl); 1623 debug("%s: failed, ret=%d\n", __func__, ret); 1624 return ret; 1625 } 1626 1627 int ehci_deregister(struct udevice *dev) 1628 { 1629 struct ehci_ctrl *ctrl = dev_get_priv(dev); 1630 1631 if (ctrl->init == USB_INIT_DEVICE) 1632 return 0; 1633 1634 ehci_shutdown(ctrl); 1635 1636 return 0; 1637 } 1638 1639 struct dm_usb_ops ehci_usb_ops = { 1640 .control = ehci_submit_control_msg, 1641 .bulk = ehci_submit_bulk_msg, 1642 .interrupt = ehci_submit_int_msg, 1643 .create_int_queue = ehci_create_int_queue, 1644 .poll_int_queue = ehci_poll_int_queue, 1645 .destroy_int_queue = ehci_destroy_int_queue, 1646 }; 1647 1648 #endif 1649