1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Excito Elektronik i Skåne AB 4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 5 * 6 * All rights reserved. 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 #include <common.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <asm/byteorder.h> 14 #include <asm/unaligned.h> 15 #include <usb.h> 16 #include <asm/io.h> 17 #include <malloc.h> 18 #include <memalign.h> 19 #include <watchdog.h> 20 #include <linux/compiler.h> 21 22 #include "ehci.h" 23 24 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 25 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 26 #endif 27 28 /* 29 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt. 30 * Let's time out after 8 to have a little safety margin on top of that. 31 */ 32 #define HCHALT_TIMEOUT (8 * 1000) 33 34 #if !CONFIG_IS_ENABLED(DM_USB) 35 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; 36 #endif 37 38 #define ALIGN_END_ADDR(type, ptr, size) \ 39 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN)) 40 41 static struct descriptor { 42 struct usb_hub_descriptor hub; 43 struct usb_device_descriptor device; 44 struct usb_linux_config_descriptor config; 45 struct usb_linux_interface_descriptor interface; 46 struct usb_endpoint_descriptor endpoint; 47 } __attribute__ ((packed)) descriptor = { 48 { 49 0x8, /* bDescLength */ 50 0x29, /* bDescriptorType: hub descriptor */ 51 2, /* bNrPorts -- runtime modified */ 52 0, /* wHubCharacteristics */ 53 10, /* bPwrOn2PwrGood */ 54 0, /* bHubCntrCurrent */ 55 { /* Device removable */ 56 } /* at most 7 ports! XXX */ 57 }, 58 { 59 0x12, /* bLength */ 60 1, /* bDescriptorType: UDESC_DEVICE */ 61 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 62 9, /* bDeviceClass: UDCLASS_HUB */ 63 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 64 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 65 64, /* bMaxPacketSize: 64 bytes */ 66 0x0000, /* idVendor */ 67 0x0000, /* idProduct */ 68 cpu_to_le16(0x0100), /* bcdDevice */ 69 1, /* iManufacturer */ 70 2, /* iProduct */ 71 0, /* iSerialNumber */ 72 1 /* bNumConfigurations: 1 */ 73 }, 74 { 75 0x9, 76 2, /* bDescriptorType: UDESC_CONFIG */ 77 cpu_to_le16(0x19), 78 1, /* bNumInterface */ 79 1, /* bConfigurationValue */ 80 0, /* iConfiguration */ 81 0x40, /* bmAttributes: UC_SELF_POWER */ 82 0 /* bMaxPower */ 83 }, 84 { 85 0x9, /* bLength */ 86 4, /* bDescriptorType: UDESC_INTERFACE */ 87 0, /* bInterfaceNumber */ 88 0, /* bAlternateSetting */ 89 1, /* bNumEndpoints */ 90 9, /* bInterfaceClass: UICLASS_HUB */ 91 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 92 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 93 0 /* iInterface */ 94 }, 95 { 96 0x7, /* bLength */ 97 5, /* bDescriptorType: UDESC_ENDPOINT */ 98 0x81, /* bEndpointAddress: 99 * UE_DIR_IN | EHCI_INTR_ENDPT 100 */ 101 3, /* bmAttributes: UE_INTERRUPT */ 102 8, /* wMaxPacketSize */ 103 255 /* bInterval */ 104 }, 105 }; 106 107 #if defined(CONFIG_EHCI_IS_TDI) 108 #define ehci_is_TDI() (1) 109 #else 110 #define ehci_is_TDI() (0) 111 #endif 112 113 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev) 114 { 115 #if CONFIG_IS_ENABLED(DM_USB) 116 return dev_get_priv(usb_get_bus(udev->dev)); 117 #else 118 return udev->controller; 119 #endif 120 } 121 122 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 123 { 124 return PORTSC_PSPD(reg); 125 } 126 127 static void ehci_set_usbmode(struct ehci_ctrl *ctrl) 128 { 129 uint32_t tmp; 130 uint32_t *reg_ptr; 131 132 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE); 133 tmp = ehci_readl(reg_ptr); 134 tmp |= USBMODE_CM_HC; 135 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) 136 tmp |= USBMODE_BE; 137 #else 138 tmp &= ~USBMODE_BE; 139 #endif 140 ehci_writel(reg_ptr, tmp); 141 } 142 143 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, 144 uint32_t *reg) 145 { 146 mdelay(50); 147 } 148 149 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) 150 { 151 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams)); 152 153 if (port < 0 || port >= max_ports) { 154 /* Printing the message would cause a scan failure! */ 155 debug("The request port(%u) exceeds maximum port number\n", 156 port); 157 return NULL; 158 } 159 160 return (uint32_t *)&ctrl->hcor->or_portsc[port]; 161 } 162 163 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) 164 { 165 uint32_t result; 166 do { 167 result = ehci_readl(ptr); 168 udelay(5); 169 if (result == ~(uint32_t)0) 170 return -1; 171 result &= mask; 172 if (result == done) 173 return 0; 174 usec--; 175 } while (usec > 0); 176 return -1; 177 } 178 179 static int ehci_reset(struct ehci_ctrl *ctrl) 180 { 181 uint32_t cmd; 182 int ret = 0; 183 184 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 185 cmd = (cmd & ~CMD_RUN) | CMD_RESET; 186 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 187 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd, 188 CMD_RESET, 0, 250 * 1000); 189 if (ret < 0) { 190 printf("EHCI fail to reset\n"); 191 goto out; 192 } 193 194 if (ehci_is_TDI()) 195 ctrl->ops.set_usb_mode(ctrl); 196 197 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH 198 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning); 199 cmd &= ~TXFIFO_THRESH_MASK; 200 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); 201 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd); 202 #endif 203 out: 204 return ret; 205 } 206 207 static int ehci_shutdown(struct ehci_ctrl *ctrl) 208 { 209 int i, ret = 0; 210 uint32_t cmd, reg; 211 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams)); 212 213 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 214 /* If not run, directly return */ 215 if (!(cmd & CMD_RUN)) 216 return 0; 217 cmd &= ~(CMD_PSE | CMD_ASE); 218 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 219 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0, 220 100 * 1000); 221 222 if (!ret) { 223 for (i = 0; i < max_ports; i++) { 224 reg = ehci_readl(&ctrl->hcor->or_portsc[i]); 225 reg |= EHCI_PS_SUSP; 226 ehci_writel(&ctrl->hcor->or_portsc[i], reg); 227 } 228 229 cmd &= ~CMD_RUN; 230 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 231 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT, 232 HCHALT_TIMEOUT); 233 } 234 235 if (ret) 236 puts("EHCI failed to shut down host controller.\n"); 237 238 return ret; 239 } 240 241 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) 242 { 243 uint32_t delta, next; 244 unsigned long addr = (unsigned long)buf; 245 int idx; 246 247 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN)) 248 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf); 249 250 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN)); 251 252 idx = 0; 253 while (idx < QT_BUFFER_CNT) { 254 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr)); 255 td->qt_buffer_hi[idx] = 0; 256 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1); 257 delta = next - addr; 258 if (delta >= sz) 259 break; 260 sz -= delta; 261 addr = next; 262 idx++; 263 } 264 265 if (idx == QT_BUFFER_CNT) { 266 printf("out of buffer pointers (%zu bytes left)\n", sz); 267 return -1; 268 } 269 270 return 0; 271 } 272 273 static inline u8 ehci_encode_speed(enum usb_device_speed speed) 274 { 275 #define QH_HIGH_SPEED 2 276 #define QH_FULL_SPEED 0 277 #define QH_LOW_SPEED 1 278 if (speed == USB_SPEED_HIGH) 279 return QH_HIGH_SPEED; 280 if (speed == USB_SPEED_LOW) 281 return QH_LOW_SPEED; 282 return QH_FULL_SPEED; 283 } 284 285 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev, 286 struct QH *qh) 287 { 288 uint8_t portnr = 0; 289 uint8_t hubaddr = 0; 290 291 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL) 292 return; 293 294 usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr); 295 296 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) | 297 QH_ENDPT2_HUBADDR(hubaddr)); 298 } 299 300 static int 301 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, 302 int length, struct devrequest *req) 303 { 304 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN); 305 struct qTD *qtd; 306 int qtd_count = 0; 307 int qtd_counter = 0; 308 volatile struct qTD *vtd; 309 unsigned long ts; 310 uint32_t *tdp; 311 uint32_t endpt, maxpacket, token, usbsts, qhtoken; 312 uint32_t c, toggle; 313 uint32_t cmd; 314 int timeout; 315 int ret = 0; 316 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 317 318 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, 319 buffer, length, req); 320 if (req != NULL) 321 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", 322 req->request, req->request, 323 req->requesttype, req->requesttype, 324 le16_to_cpu(req->value), le16_to_cpu(req->value), 325 le16_to_cpu(req->index)); 326 327 #define PKT_ALIGN 512 328 /* 329 * The USB transfer is split into qTD transfers. Eeach qTD transfer is 330 * described by a transfer descriptor (the qTD). The qTDs form a linked 331 * list with a queue head (QH). 332 * 333 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot 334 * have its beginning in a qTD transfer and its end in the following 335 * one, so the qTD transfer lengths have to be chosen accordingly. 336 * 337 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to 338 * single pages. The first data buffer can start at any offset within a 339 * page (not considering the cache-line alignment issues), while the 340 * following buffers must be page-aligned. There is no alignment 341 * constraint on the size of a qTD transfer. 342 */ 343 if (req != NULL) 344 /* 1 qTD will be needed for SETUP, and 1 for ACK. */ 345 qtd_count += 1 + 1; 346 if (length > 0 || req == NULL) { 347 /* 348 * Determine the qTD transfer size that will be used for the 349 * data payload (not considering the first qTD transfer, which 350 * may be longer or shorter, and the final one, which may be 351 * shorter). 352 * 353 * In order to keep each packet within a qTD transfer, the qTD 354 * transfer size is aligned to PKT_ALIGN, which is a multiple of 355 * wMaxPacketSize (except in some cases for interrupt transfers, 356 * see comment in submit_int_msg()). 357 * 358 * By default, i.e. if the input buffer is aligned to PKT_ALIGN, 359 * QT_BUFFER_CNT full pages will be used. 360 */ 361 int xfr_sz = QT_BUFFER_CNT; 362 /* 363 * However, if the input buffer is not aligned to PKT_ALIGN, the 364 * qTD transfer size will be one page shorter, and the first qTD 365 * data buffer of each transfer will be page-unaligned. 366 */ 367 if ((unsigned long)buffer & (PKT_ALIGN - 1)) 368 xfr_sz--; 369 /* Convert the qTD transfer size to bytes. */ 370 xfr_sz *= EHCI_PAGE_SIZE; 371 /* 372 * Approximate by excess the number of qTDs that will be 373 * required for the data payload. The exact formula is way more 374 * complicated and saves at most 2 qTDs, i.e. a total of 128 375 * bytes. 376 */ 377 qtd_count += 2 + length / xfr_sz; 378 } 379 /* 380 * Threshold value based on the worst-case total size of the allocated qTDs for 381 * a mass-storage transfer of 65535 blocks of 512 bytes. 382 */ 383 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024 384 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI 385 #endif 386 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD)); 387 if (qtd == NULL) { 388 printf("unable to allocate TDs\n"); 389 return -1; 390 } 391 392 memset(qh, 0, sizeof(struct QH)); 393 memset(qtd, 0, qtd_count * sizeof(*qtd)); 394 395 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 396 397 /* 398 * Setup QH (3.6 in ehci-r10.pdf) 399 * 400 * qh_link ................. 03-00 H 401 * qh_endpt1 ............... 07-04 H 402 * qh_endpt2 ............... 0B-08 H 403 * - qh_curtd 404 * qh_overlay.qt_next ...... 13-10 H 405 * - qh_overlay.qt_altnext 406 */ 407 qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH); 408 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe); 409 maxpacket = usb_maxpacket(dev, pipe); 410 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) | 411 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) | 412 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) | 413 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | 414 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | 415 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); 416 qh->qh_endpt1 = cpu_to_hc32(endpt); 417 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); 418 qh->qh_endpt2 = cpu_to_hc32(endpt); 419 ehci_update_endpt2_dev_n_port(dev, qh); 420 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 421 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 422 423 tdp = &qh->qh_overlay.qt_next; 424 if (req != NULL) { 425 /* 426 * Setup request qTD (3.5 in ehci-r10.pdf) 427 * 428 * qt_next ................ 03-00 H 429 * qt_altnext ............. 07-04 H 430 * qt_token ............... 0B-08 H 431 * 432 * [ buffer, buffer_hi ] loaded with "req". 433 */ 434 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 435 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 436 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) | 437 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 438 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) | 439 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 440 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 441 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) { 442 printf("unable to construct SETUP TD\n"); 443 goto fail; 444 } 445 /* Update previous qTD! */ 446 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter])); 447 tdp = &qtd[qtd_counter++].qt_next; 448 toggle = 1; 449 } 450 451 if (length > 0 || req == NULL) { 452 uint8_t *buf_ptr = buffer; 453 int left_length = length; 454 455 do { 456 /* 457 * Determine the size of this qTD transfer. By default, 458 * QT_BUFFER_CNT full pages can be used. 459 */ 460 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE; 461 /* 462 * However, if the input buffer is not page-aligned, the 463 * portion of the first page before the buffer start 464 * offset within that page is unusable. 465 */ 466 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1); 467 /* 468 * In order to keep each packet within a qTD transfer, 469 * align the qTD transfer size to PKT_ALIGN. 470 */ 471 xfr_bytes &= ~(PKT_ALIGN - 1); 472 /* 473 * This transfer may be shorter than the available qTD 474 * transfer size that has just been computed. 475 */ 476 xfr_bytes = min(xfr_bytes, left_length); 477 478 /* 479 * Setup request qTD (3.5 in ehci-r10.pdf) 480 * 481 * qt_next ................ 03-00 H 482 * qt_altnext ............. 07-04 H 483 * qt_token ............... 0B-08 H 484 * 485 * [ buffer, buffer_hi ] loaded with "buffer". 486 */ 487 qtd[qtd_counter].qt_next = 488 cpu_to_hc32(QT_NEXT_TERMINATE); 489 qtd[qtd_counter].qt_altnext = 490 cpu_to_hc32(QT_NEXT_TERMINATE); 491 token = QT_TOKEN_DT(toggle) | 492 QT_TOKEN_TOTALBYTES(xfr_bytes) | 493 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) | 494 QT_TOKEN_CERR(3) | 495 QT_TOKEN_PID(usb_pipein(pipe) ? 496 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) | 497 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 498 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 499 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr, 500 xfr_bytes)) { 501 printf("unable to construct DATA TD\n"); 502 goto fail; 503 } 504 /* Update previous qTD! */ 505 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter])); 506 tdp = &qtd[qtd_counter++].qt_next; 507 /* 508 * Data toggle has to be adjusted since the qTD transfer 509 * size is not always an even multiple of 510 * wMaxPacketSize. 511 */ 512 if ((xfr_bytes / maxpacket) & 1) 513 toggle ^= 1; 514 buf_ptr += xfr_bytes; 515 left_length -= xfr_bytes; 516 } while (left_length > 0); 517 } 518 519 if (req != NULL) { 520 /* 521 * Setup request qTD (3.5 in ehci-r10.pdf) 522 * 523 * qt_next ................ 03-00 H 524 * qt_altnext ............. 07-04 H 525 * qt_token ............... 0B-08 H 526 */ 527 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 528 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 529 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) | 530 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | 531 QT_TOKEN_PID(usb_pipein(pipe) ? 532 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) | 533 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); 534 qtd[qtd_counter].qt_token = cpu_to_hc32(token); 535 /* Update previous qTD! */ 536 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter])); 537 tdp = &qtd[qtd_counter++].qt_next; 538 } 539 540 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH); 541 542 /* Flush dcache */ 543 flush_dcache_range((unsigned long)&ctrl->qh_list, 544 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 545 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1)); 546 flush_dcache_range((unsigned long)qtd, 547 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 548 549 usbsts = ehci_readl(&ctrl->hcor->or_usbsts); 550 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f)); 551 552 /* Enable async. schedule. */ 553 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 554 if (!(cmd & CMD_ASE)) { 555 cmd |= CMD_ASE; 556 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 557 558 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS, 559 100 * 1000); 560 if (ret < 0) { 561 printf("EHCI fail timeout STS_ASS set\n"); 562 goto fail; 563 } 564 } 565 566 /* Wait for TDs to be processed. */ 567 ts = get_timer(0); 568 vtd = &qtd[qtd_counter - 1]; 569 timeout = USB_TIMEOUT_MS(pipe); 570 do { 571 /* Invalidate dcache */ 572 invalidate_dcache_range((unsigned long)&ctrl->qh_list, 573 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 574 invalidate_dcache_range((unsigned long)qh, 575 ALIGN_END_ADDR(struct QH, qh, 1)); 576 invalidate_dcache_range((unsigned long)qtd, 577 ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); 578 579 token = hc32_to_cpu(vtd->qt_token); 580 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) 581 break; 582 WATCHDOG_RESET(); 583 } while (get_timer(ts) < timeout); 584 qhtoken = hc32_to_cpu(qh->qh_overlay.qt_token); 585 586 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH); 587 flush_dcache_range((unsigned long)&ctrl->qh_list, 588 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); 589 590 /* 591 * Invalidate the memory area occupied by buffer 592 * Don't try to fix the buffer alignment, if it isn't properly 593 * aligned it's upper layer's fault so let invalidate_dcache_range() 594 * vow about it. But we have to fix the length as it's actual 595 * transfer length and can be unaligned. This is potentially 596 * dangerous operation, it's responsibility of the calling 597 * code to make sure enough space is reserved. 598 */ 599 if (buffer != NULL && length > 0) 600 invalidate_dcache_range((unsigned long)buffer, 601 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN)); 602 603 /* Check that the TD processing happened */ 604 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) 605 printf("EHCI timed out on TD - token=%#x\n", token); 606 607 if (!(QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_ACTIVE)) { 608 debug("TOKEN=%#x\n", qhtoken); 609 switch (QT_TOKEN_GET_STATUS(qhtoken) & 610 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) { 611 case 0: 612 toggle = QT_TOKEN_GET_DT(qhtoken); 613 usb_settoggle(dev, usb_pipeendpoint(pipe), 614 usb_pipeout(pipe), toggle); 615 dev->status = 0; 616 break; 617 case QT_TOKEN_STATUS_HALTED: 618 dev->status = USB_ST_STALLED; 619 break; 620 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR: 621 case QT_TOKEN_STATUS_DATBUFERR: 622 dev->status = USB_ST_BUF_ERR; 623 break; 624 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET: 625 case QT_TOKEN_STATUS_BABBLEDET: 626 dev->status = USB_ST_BABBLE_DET; 627 break; 628 default: 629 dev->status = USB_ST_CRC_ERR; 630 if (QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_HALTED) 631 dev->status |= USB_ST_STALLED; 632 break; 633 } 634 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(qhtoken); 635 } else { 636 dev->act_len = 0; 637 #ifndef CONFIG_USB_EHCI_FARADAY 638 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", 639 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts), 640 ehci_readl(&ctrl->hcor->or_portsc[0]), 641 ehci_readl(&ctrl->hcor->or_portsc[1])); 642 #endif 643 } 644 645 free(qtd); 646 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; 647 648 fail: 649 free(qtd); 650 return -1; 651 } 652 653 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe, 654 void *buffer, int length, struct devrequest *req) 655 { 656 uint8_t tmpbuf[4]; 657 u16 typeReq; 658 void *srcptr = NULL; 659 int len, srclen; 660 uint32_t reg; 661 uint32_t *status_reg; 662 int port = le16_to_cpu(req->index) & 0xff; 663 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 664 665 srclen = 0; 666 667 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", 668 req->request, req->request, 669 req->requesttype, req->requesttype, 670 le16_to_cpu(req->value), le16_to_cpu(req->index)); 671 672 typeReq = req->request | req->requesttype << 8; 673 674 switch (typeReq) { 675 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 676 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 677 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 678 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1); 679 if (!status_reg) 680 return -1; 681 break; 682 default: 683 status_reg = NULL; 684 break; 685 } 686 687 switch (typeReq) { 688 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 689 switch (le16_to_cpu(req->value) >> 8) { 690 case USB_DT_DEVICE: 691 debug("USB_DT_DEVICE request\n"); 692 srcptr = &descriptor.device; 693 srclen = descriptor.device.bLength; 694 break; 695 case USB_DT_CONFIG: 696 debug("USB_DT_CONFIG config\n"); 697 srcptr = &descriptor.config; 698 srclen = descriptor.config.bLength + 699 descriptor.interface.bLength + 700 descriptor.endpoint.bLength; 701 break; 702 case USB_DT_STRING: 703 debug("USB_DT_STRING config\n"); 704 switch (le16_to_cpu(req->value) & 0xff) { 705 case 0: /* Language */ 706 srcptr = "\4\3\1\0"; 707 srclen = 4; 708 break; 709 case 1: /* Vendor */ 710 srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; 711 srclen = 14; 712 break; 713 case 2: /* Product */ 714 srcptr = "\52\3E\0H\0C\0I\0 " 715 "\0H\0o\0s\0t\0 " 716 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 717 srclen = 42; 718 break; 719 default: 720 debug("unknown value DT_STRING %x\n", 721 le16_to_cpu(req->value)); 722 goto unknown; 723 } 724 break; 725 default: 726 debug("unknown value %x\n", le16_to_cpu(req->value)); 727 goto unknown; 728 } 729 break; 730 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 731 switch (le16_to_cpu(req->value) >> 8) { 732 case USB_DT_HUB: 733 debug("USB_DT_HUB config\n"); 734 srcptr = &descriptor.hub; 735 srclen = descriptor.hub.bLength; 736 break; 737 default: 738 debug("unknown value %x\n", le16_to_cpu(req->value)); 739 goto unknown; 740 } 741 break; 742 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 743 debug("USB_REQ_SET_ADDRESS\n"); 744 ctrl->rootdev = le16_to_cpu(req->value); 745 break; 746 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 747 debug("USB_REQ_SET_CONFIGURATION\n"); 748 /* Nothing to do */ 749 break; 750 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 751 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 752 tmpbuf[1] = 0; 753 srcptr = tmpbuf; 754 srclen = 2; 755 break; 756 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 757 memset(tmpbuf, 0, 4); 758 reg = ehci_readl(status_reg); 759 if (reg & EHCI_PS_CS) 760 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 761 if (reg & EHCI_PS_PE) 762 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 763 if (reg & EHCI_PS_SUSP) 764 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 765 if (reg & EHCI_PS_OCA) 766 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 767 if (reg & EHCI_PS_PR) 768 tmpbuf[0] |= USB_PORT_STAT_RESET; 769 if (reg & EHCI_PS_PP) 770 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 771 772 if (ehci_is_TDI()) { 773 switch (ctrl->ops.get_port_speed(ctrl, reg)) { 774 case PORTSC_PSPD_FS: 775 break; 776 case PORTSC_PSPD_LS: 777 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 778 break; 779 case PORTSC_PSPD_HS: 780 default: 781 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 782 break; 783 } 784 } else { 785 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 786 } 787 788 if (reg & EHCI_PS_CSC) 789 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 790 if (reg & EHCI_PS_PEC) 791 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 792 if (reg & EHCI_PS_OCC) 793 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 794 if (ctrl->portreset & (1 << port)) 795 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 796 797 srcptr = tmpbuf; 798 srclen = 4; 799 break; 800 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 801 reg = ehci_readl(status_reg); 802 reg &= ~EHCI_PS_CLEAR; 803 switch (le16_to_cpu(req->value)) { 804 case USB_PORT_FEAT_ENABLE: 805 reg |= EHCI_PS_PE; 806 ehci_writel(status_reg, reg); 807 break; 808 case USB_PORT_FEAT_POWER: 809 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) { 810 reg |= EHCI_PS_PP; 811 ehci_writel(status_reg, reg); 812 } 813 break; 814 case USB_PORT_FEAT_RESET: 815 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && 816 !ehci_is_TDI() && 817 EHCI_PS_IS_LOWSPEED(reg)) { 818 /* Low speed device, give up ownership. */ 819 debug("port %d low speed --> companion\n", 820 port - 1); 821 reg |= EHCI_PS_PO; 822 ehci_writel(status_reg, reg); 823 return -ENXIO; 824 } else { 825 int ret; 826 827 reg |= EHCI_PS_PR; 828 reg &= ~EHCI_PS_PE; 829 ehci_writel(status_reg, reg); 830 /* 831 * caller must wait, then call GetPortStatus 832 * usb 2.0 specification say 50 ms resets on 833 * root 834 */ 835 ctrl->ops.powerup_fixup(ctrl, status_reg, ®); 836 837 ehci_writel(status_reg, reg & ~EHCI_PS_PR); 838 /* 839 * A host controller must terminate the reset 840 * and stabilize the state of the port within 841 * 2 milliseconds 842 */ 843 ret = handshake(status_reg, EHCI_PS_PR, 0, 844 2 * 1000); 845 if (!ret) { 846 reg = ehci_readl(status_reg); 847 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) 848 == EHCI_PS_CS && !ehci_is_TDI()) { 849 debug("port %d full speed --> companion\n", port - 1); 850 reg &= ~EHCI_PS_CLEAR; 851 reg |= EHCI_PS_PO; 852 ehci_writel(status_reg, reg); 853 return -ENXIO; 854 } else { 855 ctrl->portreset |= 1 << port; 856 } 857 } else { 858 printf("port(%d) reset error\n", 859 port - 1); 860 } 861 } 862 break; 863 case USB_PORT_FEAT_TEST: 864 ehci_shutdown(ctrl); 865 reg &= ~(0xf << 16); 866 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16; 867 ehci_writel(status_reg, reg); 868 break; 869 default: 870 debug("unknown feature %x\n", le16_to_cpu(req->value)); 871 goto unknown; 872 } 873 /* unblock posted writes */ 874 (void) ehci_readl(&ctrl->hcor->or_usbcmd); 875 break; 876 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 877 reg = ehci_readl(status_reg); 878 reg &= ~EHCI_PS_CLEAR; 879 switch (le16_to_cpu(req->value)) { 880 case USB_PORT_FEAT_ENABLE: 881 reg &= ~EHCI_PS_PE; 882 break; 883 case USB_PORT_FEAT_C_ENABLE: 884 reg |= EHCI_PS_PE; 885 break; 886 case USB_PORT_FEAT_POWER: 887 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) 888 reg &= ~EHCI_PS_PP; 889 break; 890 case USB_PORT_FEAT_C_CONNECTION: 891 reg |= EHCI_PS_CSC; 892 break; 893 case USB_PORT_FEAT_OVER_CURRENT: 894 reg |= EHCI_PS_OCC; 895 break; 896 case USB_PORT_FEAT_C_RESET: 897 ctrl->portreset &= ~(1 << port); 898 break; 899 default: 900 debug("unknown feature %x\n", le16_to_cpu(req->value)); 901 goto unknown; 902 } 903 ehci_writel(status_reg, reg); 904 /* unblock posted write */ 905 (void) ehci_readl(&ctrl->hcor->or_usbcmd); 906 break; 907 default: 908 debug("Unknown request\n"); 909 goto unknown; 910 } 911 912 mdelay(1); 913 len = min3(srclen, (int)le16_to_cpu(req->length), length); 914 if (srcptr != NULL && len > 0) 915 memcpy(buffer, srcptr, len); 916 else 917 debug("Len is 0\n"); 918 919 dev->act_len = len; 920 dev->status = 0; 921 return 0; 922 923 unknown: 924 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", 925 req->requesttype, req->request, le16_to_cpu(req->value), 926 le16_to_cpu(req->index), le16_to_cpu(req->length)); 927 928 dev->act_len = 0; 929 dev->status = USB_ST_STALLED; 930 return -1; 931 } 932 933 static const struct ehci_ops default_ehci_ops = { 934 .set_usb_mode = ehci_set_usbmode, 935 .get_port_speed = ehci_get_port_speed, 936 .powerup_fixup = ehci_powerup_fixup, 937 .get_portsc_register = ehci_get_portsc_register, 938 }; 939 940 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops) 941 { 942 if (!ops) { 943 ctrl->ops = default_ehci_ops; 944 } else { 945 ctrl->ops = *ops; 946 if (!ctrl->ops.set_usb_mode) 947 ctrl->ops.set_usb_mode = ehci_set_usbmode; 948 if (!ctrl->ops.get_port_speed) 949 ctrl->ops.get_port_speed = ehci_get_port_speed; 950 if (!ctrl->ops.powerup_fixup) 951 ctrl->ops.powerup_fixup = ehci_powerup_fixup; 952 if (!ctrl->ops.get_portsc_register) 953 ctrl->ops.get_portsc_register = 954 ehci_get_portsc_register; 955 } 956 } 957 958 #if !CONFIG_IS_ENABLED(DM_USB) 959 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops) 960 { 961 struct ehci_ctrl *ctrl = &ehcic[index]; 962 963 ctrl->priv = priv; 964 ehci_setup_ops(ctrl, ops); 965 } 966 967 void *ehci_get_controller_priv(int index) 968 { 969 return ehcic[index].priv; 970 } 971 #endif 972 973 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks) 974 { 975 struct QH *qh_list; 976 struct QH *periodic; 977 uint32_t reg; 978 uint32_t cmd; 979 int i; 980 981 /* Set the high address word (aka segment) for 64-bit controller */ 982 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1) 983 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0); 984 985 qh_list = &ctrl->qh_list; 986 987 /* Set head of reclaim list */ 988 memset(qh_list, 0, sizeof(*qh_list)); 989 qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH); 990 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) | 991 QH_ENDPT1_EPS(USB_SPEED_HIGH)); 992 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 993 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 994 qh_list->qh_overlay.qt_token = 995 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED)); 996 997 flush_dcache_range((unsigned long)qh_list, 998 ALIGN_END_ADDR(struct QH, qh_list, 1)); 999 1000 /* Set async. queue head pointer. */ 1001 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list)); 1002 1003 /* 1004 * Set up periodic list 1005 * Step 1: Parent QH for all periodic transfers. 1006 */ 1007 ctrl->periodic_schedules = 0; 1008 periodic = &ctrl->periodic_queue; 1009 memset(periodic, 0, sizeof(*periodic)); 1010 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); 1011 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 1012 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 1013 1014 flush_dcache_range((unsigned long)periodic, 1015 ALIGN_END_ADDR(struct QH, periodic, 1)); 1016 1017 /* 1018 * Step 2: Setup frame-list: Every microframe, USB tries the same list. 1019 * In particular, device specifications on polling frequency 1020 * are disregarded. Keyboards seem to send NAK/NYet reliably 1021 * when polled with an empty buffer. 1022 * 1023 * Split Transactions will be spread across microframes using 1024 * S-mask and C-mask. 1025 */ 1026 if (ctrl->periodic_list == NULL) 1027 ctrl->periodic_list = memalign(4096, 1024 * 4); 1028 1029 if (!ctrl->periodic_list) 1030 return -ENOMEM; 1031 for (i = 0; i < 1024; i++) { 1032 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic 1033 | QH_LINK_TYPE_QH); 1034 } 1035 1036 flush_dcache_range((unsigned long)ctrl->periodic_list, 1037 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list, 1038 1024)); 1039 1040 /* Set periodic list base address */ 1041 ehci_writel(&ctrl->hcor->or_periodiclistbase, 1042 (unsigned long)ctrl->periodic_list); 1043 1044 reg = ehci_readl(&ctrl->hccr->cr_hcsparams); 1045 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); 1046 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 1047 /* Port Indicators */ 1048 if (HCS_INDICATOR(reg)) 1049 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 1050 | 0x80, &descriptor.hub.wHubCharacteristics); 1051 /* Port Power Control */ 1052 if (HCS_PPC(reg)) 1053 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 1054 | 0x01, &descriptor.hub.wHubCharacteristics); 1055 1056 /* Start the host controller. */ 1057 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 1058 /* 1059 * Philips, Intel, and maybe others need CMD_RUN before the 1060 * root hub will detect new devices (why?); NEC doesn't 1061 */ 1062 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 1063 cmd |= CMD_RUN; 1064 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); 1065 1066 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) { 1067 /* take control over the ports */ 1068 cmd = ehci_readl(&ctrl->hcor->or_configflag); 1069 cmd |= FLAG_CF; 1070 ehci_writel(&ctrl->hcor->or_configflag, cmd); 1071 } 1072 1073 /* unblock posted write */ 1074 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); 1075 mdelay(5); 1076 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase)); 1077 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); 1078 1079 return 0; 1080 } 1081 1082 #if !CONFIG_IS_ENABLED(DM_USB) 1083 int usb_lowlevel_stop(int index) 1084 { 1085 ehci_shutdown(&ehcic[index]); 1086 return ehci_hcd_stop(index); 1087 } 1088 1089 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1090 { 1091 struct ehci_ctrl *ctrl = &ehcic[index]; 1092 uint tweaks = 0; 1093 int rc; 1094 1095 /** 1096 * Set ops to default_ehci_ops, ehci_hcd_init should call 1097 * ehci_set_controller_priv to change any of these function pointers. 1098 */ 1099 ctrl->ops = default_ehci_ops; 1100 1101 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); 1102 if (rc) 1103 return rc; 1104 if (!ctrl->hccr || !ctrl->hcor) 1105 return -1; 1106 if (init == USB_INIT_DEVICE) 1107 goto done; 1108 1109 /* EHCI spec section 4.1 */ 1110 if (ehci_reset(ctrl)) 1111 return -1; 1112 1113 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) 1114 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); 1115 if (rc) 1116 return rc; 1117 #endif 1118 #ifdef CONFIG_USB_EHCI_FARADAY 1119 tweaks |= EHCI_TWEAK_NO_INIT_CF; 1120 #endif 1121 rc = ehci_common_init(ctrl, tweaks); 1122 if (rc) 1123 return rc; 1124 1125 ctrl->rootdev = 0; 1126 done: 1127 *controller = &ehcic[index]; 1128 return 0; 1129 } 1130 #endif 1131 1132 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe, 1133 void *buffer, int length) 1134 { 1135 1136 if (usb_pipetype(pipe) != PIPE_BULK) { 1137 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 1138 return -1; 1139 } 1140 return ehci_submit_async(dev, pipe, buffer, length, NULL); 1141 } 1142 1143 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe, 1144 void *buffer, int length, 1145 struct devrequest *setup) 1146 { 1147 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 1148 1149 if (usb_pipetype(pipe) != PIPE_CONTROL) { 1150 debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); 1151 return -1; 1152 } 1153 1154 if (usb_pipedevice(pipe) == ctrl->rootdev) { 1155 if (!ctrl->rootdev) 1156 dev->speed = USB_SPEED_HIGH; 1157 return ehci_submit_root(dev, pipe, buffer, length, setup); 1158 } 1159 return ehci_submit_async(dev, pipe, buffer, length, setup); 1160 } 1161 1162 struct int_queue { 1163 int elementsize; 1164 unsigned long pipe; 1165 struct QH *first; 1166 struct QH *current; 1167 struct QH *last; 1168 struct qTD *tds; 1169 }; 1170 1171 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f) 1172 1173 static int 1174 enable_periodic(struct ehci_ctrl *ctrl) 1175 { 1176 uint32_t cmd; 1177 struct ehci_hcor *hcor = ctrl->hcor; 1178 int ret; 1179 1180 cmd = ehci_readl(&hcor->or_usbcmd); 1181 cmd |= CMD_PSE; 1182 ehci_writel(&hcor->or_usbcmd, cmd); 1183 1184 ret = handshake((uint32_t *)&hcor->or_usbsts, 1185 STS_PSS, STS_PSS, 100 * 1000); 1186 if (ret < 0) { 1187 printf("EHCI failed: timeout when enabling periodic list\n"); 1188 return -ETIMEDOUT; 1189 } 1190 udelay(1000); 1191 return 0; 1192 } 1193 1194 static int 1195 disable_periodic(struct ehci_ctrl *ctrl) 1196 { 1197 uint32_t cmd; 1198 struct ehci_hcor *hcor = ctrl->hcor; 1199 int ret; 1200 1201 cmd = ehci_readl(&hcor->or_usbcmd); 1202 cmd &= ~CMD_PSE; 1203 ehci_writel(&hcor->or_usbcmd, cmd); 1204 1205 ret = handshake((uint32_t *)&hcor->or_usbsts, 1206 STS_PSS, 0, 100 * 1000); 1207 if (ret < 0) { 1208 printf("EHCI failed: timeout when disabling periodic list\n"); 1209 return -ETIMEDOUT; 1210 } 1211 return 0; 1212 } 1213 1214 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev, 1215 unsigned long pipe, int queuesize, int elementsize, 1216 void *buffer, int interval) 1217 { 1218 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 1219 struct int_queue *result = NULL; 1220 uint32_t i, toggle; 1221 1222 /* 1223 * Interrupt transfers requiring several transactions are not supported 1224 * because bInterval is ignored. 1225 * 1226 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 1227 * <= PKT_ALIGN if several qTDs are required, while the USB 1228 * specification does not constrain this for interrupt transfers. That 1229 * means that ehci_submit_async() would support interrupt transfers 1230 * requiring several transactions only as long as the transfer size does 1231 * not require more than a single qTD. 1232 */ 1233 if (elementsize > usb_maxpacket(dev, pipe)) { 1234 printf("%s: xfers requiring several transactions are not supported.\n", 1235 __func__); 1236 return NULL; 1237 } 1238 1239 debug("Enter create_int_queue\n"); 1240 if (usb_pipetype(pipe) != PIPE_INTERRUPT) { 1241 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); 1242 return NULL; 1243 } 1244 1245 /* limit to 4 full pages worth of data - 1246 * we can safely fit them in a single TD, 1247 * no matter the alignment 1248 */ 1249 if (elementsize >= 16384) { 1250 debug("too large elements for interrupt transfers\n"); 1251 return NULL; 1252 } 1253 1254 result = malloc(sizeof(*result)); 1255 if (!result) { 1256 debug("ehci intr queue: out of memory\n"); 1257 goto fail1; 1258 } 1259 result->elementsize = elementsize; 1260 result->pipe = pipe; 1261 result->first = memalign(USB_DMA_MINALIGN, 1262 sizeof(struct QH) * queuesize); 1263 if (!result->first) { 1264 debug("ehci intr queue: out of memory\n"); 1265 goto fail2; 1266 } 1267 result->current = result->first; 1268 result->last = result->first + queuesize - 1; 1269 result->tds = memalign(USB_DMA_MINALIGN, 1270 sizeof(struct qTD) * queuesize); 1271 if (!result->tds) { 1272 debug("ehci intr queue: out of memory\n"); 1273 goto fail3; 1274 } 1275 memset(result->first, 0, sizeof(struct QH) * queuesize); 1276 memset(result->tds, 0, sizeof(struct qTD) * queuesize); 1277 1278 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); 1279 1280 for (i = 0; i < queuesize; i++) { 1281 struct QH *qh = result->first + i; 1282 struct qTD *td = result->tds + i; 1283 void **buf = &qh->buffer; 1284 1285 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH); 1286 if (i == queuesize - 1) 1287 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); 1288 1289 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td); 1290 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 1291 qh->qh_endpt1 = 1292 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */ 1293 (usb_maxpacket(dev, pipe) << 16) | /* MPS */ 1294 (1 << 14) | 1295 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | 1296 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ 1297 (usb_pipedevice(pipe) << 0)); 1298 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */ 1299 (1 << 0)); /* S-mask: microframe 0 */ 1300 if (dev->speed == USB_SPEED_LOW || 1301 dev->speed == USB_SPEED_FULL) { 1302 /* C-mask: microframes 2-4 */ 1303 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8)); 1304 } 1305 ehci_update_endpt2_dev_n_port(dev, qh); 1306 1307 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); 1308 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); 1309 debug("communication direction is '%s'\n", 1310 usb_pipein(pipe) ? "in" : "out"); 1311 td->qt_token = cpu_to_hc32( 1312 QT_TOKEN_DT(toggle) | 1313 (elementsize << 16) | 1314 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ 1315 0x80); /* active */ 1316 td->qt_buffer[0] = 1317 cpu_to_hc32((unsigned long)buffer + i * elementsize); 1318 td->qt_buffer[1] = 1319 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff); 1320 td->qt_buffer[2] = 1321 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff); 1322 td->qt_buffer[3] = 1323 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff); 1324 td->qt_buffer[4] = 1325 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff); 1326 1327 *buf = buffer + i * elementsize; 1328 toggle ^= 1; 1329 } 1330 1331 flush_dcache_range((unsigned long)buffer, 1332 ALIGN_END_ADDR(char, buffer, 1333 queuesize * elementsize)); 1334 flush_dcache_range((unsigned long)result->first, 1335 ALIGN_END_ADDR(struct QH, result->first, 1336 queuesize)); 1337 flush_dcache_range((unsigned long)result->tds, 1338 ALIGN_END_ADDR(struct qTD, result->tds, 1339 queuesize)); 1340 1341 if (ctrl->periodic_schedules > 0) { 1342 if (disable_periodic(ctrl) < 0) { 1343 debug("FATAL: periodic should never fail, but did"); 1344 goto fail3; 1345 } 1346 } 1347 1348 /* hook up to periodic list */ 1349 struct QH *list = &ctrl->periodic_queue; 1350 result->last->qh_link = list->qh_link; 1351 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH); 1352 1353 flush_dcache_range((unsigned long)result->last, 1354 ALIGN_END_ADDR(struct QH, result->last, 1)); 1355 flush_dcache_range((unsigned long)list, 1356 ALIGN_END_ADDR(struct QH, list, 1)); 1357 1358 if (enable_periodic(ctrl) < 0) { 1359 debug("FATAL: periodic should never fail, but did"); 1360 goto fail3; 1361 } 1362 ctrl->periodic_schedules++; 1363 1364 debug("Exit create_int_queue\n"); 1365 return result; 1366 fail3: 1367 if (result->tds) 1368 free(result->tds); 1369 fail2: 1370 if (result->first) 1371 free(result->first); 1372 if (result) 1373 free(result); 1374 fail1: 1375 return NULL; 1376 } 1377 1378 static void *_ehci_poll_int_queue(struct usb_device *dev, 1379 struct int_queue *queue) 1380 { 1381 struct QH *cur = queue->current; 1382 struct qTD *cur_td; 1383 uint32_t token, toggle; 1384 unsigned long pipe = queue->pipe; 1385 1386 /* depleted queue */ 1387 if (cur == NULL) { 1388 debug("Exit poll_int_queue with completed queue\n"); 1389 return NULL; 1390 } 1391 /* still active */ 1392 cur_td = &queue->tds[queue->current - queue->first]; 1393 invalidate_dcache_range((unsigned long)cur_td, 1394 ALIGN_END_ADDR(struct qTD, cur_td, 1)); 1395 token = hc32_to_cpu(cur_td->qt_token); 1396 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) { 1397 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token); 1398 return NULL; 1399 } 1400 1401 toggle = QT_TOKEN_GET_DT(token); 1402 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle); 1403 1404 if (!(cur->qh_link & QH_LINK_TERMINATE)) 1405 queue->current++; 1406 else 1407 queue->current = NULL; 1408 1409 invalidate_dcache_range((unsigned long)cur->buffer, 1410 ALIGN_END_ADDR(char, cur->buffer, 1411 queue->elementsize)); 1412 1413 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n", 1414 token, cur, queue->first); 1415 return cur->buffer; 1416 } 1417 1418 /* Do not free buffers associated with QHs, they're owned by someone else */ 1419 static int _ehci_destroy_int_queue(struct usb_device *dev, 1420 struct int_queue *queue) 1421 { 1422 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); 1423 int result = -1; 1424 unsigned long timeout; 1425 1426 if (disable_periodic(ctrl) < 0) { 1427 debug("FATAL: periodic should never fail, but did"); 1428 goto out; 1429 } 1430 ctrl->periodic_schedules--; 1431 1432 struct QH *cur = &ctrl->periodic_queue; 1433 timeout = get_timer(0) + 500; /* abort after 500ms */ 1434 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) { 1435 debug("considering %p, with qh_link %x\n", cur, cur->qh_link); 1436 if (NEXT_QH(cur) == queue->first) { 1437 debug("found candidate. removing from chain\n"); 1438 cur->qh_link = queue->last->qh_link; 1439 flush_dcache_range((unsigned long)cur, 1440 ALIGN_END_ADDR(struct QH, cur, 1)); 1441 result = 0; 1442 break; 1443 } 1444 cur = NEXT_QH(cur); 1445 if (get_timer(0) > timeout) { 1446 printf("Timeout destroying interrupt endpoint queue\n"); 1447 result = -1; 1448 goto out; 1449 } 1450 } 1451 1452 if (ctrl->periodic_schedules > 0) { 1453 result = enable_periodic(ctrl); 1454 if (result < 0) 1455 debug("FATAL: periodic should never fail, but did"); 1456 } 1457 1458 out: 1459 free(queue->tds); 1460 free(queue->first); 1461 free(queue); 1462 1463 return result; 1464 } 1465 1466 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe, 1467 void *buffer, int length, int interval, 1468 bool nonblock) 1469 { 1470 void *backbuffer; 1471 struct int_queue *queue; 1472 unsigned long timeout; 1473 int result = 0, ret; 1474 1475 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", 1476 dev, pipe, buffer, length, interval); 1477 1478 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval); 1479 if (!queue) 1480 return -1; 1481 1482 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1483 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL) 1484 if (get_timer(0) > timeout) { 1485 printf("Timeout poll on interrupt endpoint\n"); 1486 result = -ETIMEDOUT; 1487 break; 1488 } 1489 1490 if (backbuffer != buffer) { 1491 debug("got wrong buffer back (%p instead of %p)\n", 1492 backbuffer, buffer); 1493 return -EINVAL; 1494 } 1495 1496 ret = _ehci_destroy_int_queue(dev, queue); 1497 if (ret < 0) 1498 return ret; 1499 1500 /* everything worked out fine */ 1501 return result; 1502 } 1503 1504 #if !CONFIG_IS_ENABLED(DM_USB) 1505 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, 1506 void *buffer, int length) 1507 { 1508 return _ehci_submit_bulk_msg(dev, pipe, buffer, length); 1509 } 1510 1511 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1512 int length, struct devrequest *setup) 1513 { 1514 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup); 1515 } 1516 1517 int submit_int_msg(struct usb_device *dev, unsigned long pipe, 1518 void *buffer, int length, int interval, bool nonblock) 1519 { 1520 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval, 1521 nonblock); 1522 } 1523 1524 struct int_queue *create_int_queue(struct usb_device *dev, 1525 unsigned long pipe, int queuesize, int elementsize, 1526 void *buffer, int interval) 1527 { 1528 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize, 1529 buffer, interval); 1530 } 1531 1532 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) 1533 { 1534 return _ehci_poll_int_queue(dev, queue); 1535 } 1536 1537 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) 1538 { 1539 return _ehci_destroy_int_queue(dev, queue); 1540 } 1541 #endif 1542 1543 #if CONFIG_IS_ENABLED(DM_USB) 1544 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1545 unsigned long pipe, void *buffer, int length, 1546 struct devrequest *setup) 1547 { 1548 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1549 dev->name, udev, udev->dev->name, udev->portnr); 1550 1551 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup); 1552 } 1553 1554 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1555 unsigned long pipe, void *buffer, int length) 1556 { 1557 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1558 return _ehci_submit_bulk_msg(udev, pipe, buffer, length); 1559 } 1560 1561 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1562 unsigned long pipe, void *buffer, int length, 1563 int interval, bool nonblock) 1564 { 1565 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1566 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval, 1567 nonblock); 1568 } 1569 1570 static struct int_queue *ehci_create_int_queue(struct udevice *dev, 1571 struct usb_device *udev, unsigned long pipe, int queuesize, 1572 int elementsize, void *buffer, int interval) 1573 { 1574 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1575 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize, 1576 buffer, interval); 1577 } 1578 1579 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev, 1580 struct int_queue *queue) 1581 { 1582 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1583 return _ehci_poll_int_queue(udev, queue); 1584 } 1585 1586 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev, 1587 struct int_queue *queue) 1588 { 1589 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1590 return _ehci_destroy_int_queue(udev, queue); 1591 } 1592 1593 static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size) 1594 { 1595 /* 1596 * EHCD can handle any transfer length as long as there is enough 1597 * free heap space left, hence set the theoretical max number here. 1598 */ 1599 *size = SIZE_MAX; 1600 1601 return 0; 1602 } 1603 1604 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, 1605 struct ehci_hcor *hcor, const struct ehci_ops *ops, 1606 uint tweaks, enum usb_init_type init) 1607 { 1608 struct usb_bus_priv *priv = dev_get_uclass_priv(dev); 1609 struct ehci_ctrl *ctrl = dev_get_priv(dev); 1610 int ret = -1; 1611 1612 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__, 1613 dev->name, ctrl, hccr, hcor, init); 1614 1615 if (!ctrl || !hccr || !hcor) 1616 goto err; 1617 1618 priv->desc_before_addr = true; 1619 1620 ehci_setup_ops(ctrl, ops); 1621 ctrl->hccr = hccr; 1622 ctrl->hcor = hcor; 1623 ctrl->priv = ctrl; 1624 1625 ctrl->init = init; 1626 if (ctrl->init == USB_INIT_DEVICE) 1627 goto done; 1628 1629 ret = ehci_reset(ctrl); 1630 if (ret) 1631 goto err; 1632 1633 if (ctrl->ops.init_after_reset) { 1634 ret = ctrl->ops.init_after_reset(ctrl); 1635 if (ret) 1636 goto err; 1637 } 1638 1639 ret = ehci_common_init(ctrl, tweaks); 1640 if (ret) 1641 goto err; 1642 done: 1643 return 0; 1644 err: 1645 free(ctrl); 1646 debug("%s: failed, ret=%d\n", __func__, ret); 1647 return ret; 1648 } 1649 1650 int ehci_deregister(struct udevice *dev) 1651 { 1652 struct ehci_ctrl *ctrl = dev_get_priv(dev); 1653 1654 if (ctrl->init == USB_INIT_DEVICE) 1655 return 0; 1656 1657 ehci_shutdown(ctrl); 1658 1659 return 0; 1660 } 1661 1662 struct dm_usb_ops ehci_usb_ops = { 1663 .control = ehci_submit_control_msg, 1664 .bulk = ehci_submit_bulk_msg, 1665 .interrupt = ehci_submit_int_msg, 1666 .create_int_queue = ehci_create_int_queue, 1667 .poll_int_queue = ehci_poll_int_queue, 1668 .destroy_int_queue = ehci_destroy_int_queue, 1669 .get_max_xfer_size = ehci_get_max_xfer_size, 1670 }; 1671 1672 #endif 1673 1674 #ifdef CONFIG_PHY 1675 int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index) 1676 { 1677 int ret; 1678 1679 if (!phy) 1680 return 0; 1681 1682 ret = generic_phy_get_by_index(dev, index, phy); 1683 if (ret) { 1684 if (ret != -ENOENT) { 1685 dev_err(dev, "failed to get usb phy\n"); 1686 return ret; 1687 } 1688 } else { 1689 ret = generic_phy_init(phy); 1690 if (ret) { 1691 dev_err(dev, "failed to init usb phy\n"); 1692 return ret; 1693 } 1694 1695 ret = generic_phy_power_on(phy); 1696 if (ret) { 1697 dev_err(dev, "failed to power on usb phy\n"); 1698 return generic_phy_exit(phy); 1699 } 1700 } 1701 1702 return 0; 1703 } 1704 1705 int ehci_shutdown_phy(struct udevice *dev, struct phy *phy) 1706 { 1707 int ret = 0; 1708 1709 if (!phy) 1710 return 0; 1711 1712 if (generic_phy_valid(phy)) { 1713 ret = generic_phy_power_off(phy); 1714 if (ret) { 1715 dev_err(dev, "failed to power off usb phy\n"); 1716 return ret; 1717 } 1718 1719 ret = generic_phy_exit(phy); 1720 if (ret) { 1721 dev_err(dev, "failed to power off usb phy\n"); 1722 return ret; 1723 } 1724 } 1725 1726 return 0; 1727 } 1728 #else 1729 int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index) 1730 { 1731 return 0; 1732 } 1733 1734 int ehci_shutdown_phy(struct udevice *dev, struct phy *phy) 1735 { 1736 return 0; 1737 } 1738 #endif 1739