1 /* 2 * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB 5 * 6 * Author: Tor Krill tor@excito.com 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <pci.h> 13 #include <usb.h> 14 #include <asm/io.h> 15 #include <usb/ehci-ci.h> 16 #include <hwconfig.h> 17 #include <fsl_usb.h> 18 #include <fdt_support.h> 19 #include <dm.h> 20 21 #include "ehci.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 26 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 27 #endif 28 29 #if CONFIG_IS_ENABLED(DM_USB) 30 struct ehci_fsl_priv { 31 struct ehci_ctrl ehci; 32 fdt_addr_t hcd_base; 33 char *phy_type; 34 }; 35 #endif 36 37 static void set_txfifothresh(struct usb_ehci *, u32); 38 #if CONFIG_IS_ENABLED(DM_USB) 39 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, 40 struct ehci_hccr *hccr, struct ehci_hcor *hcor); 41 #else 42 static int ehci_fsl_init(int index, struct usb_ehci *ehci, 43 struct ehci_hccr *hccr, struct ehci_hcor *hcor); 44 #endif 45 46 /* Check USB PHY clock valid */ 47 static int usb_phy_clk_valid(struct usb_ehci *ehci) 48 { 49 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) || 50 in_be32(&ehci->prictrl))) { 51 printf("USB PHY clock invalid!\n"); 52 return 0; 53 } else { 54 return 1; 55 } 56 } 57 58 #if CONFIG_IS_ENABLED(DM_USB) 59 static int ehci_fsl_ofdata_to_platdata(struct udevice *dev) 60 { 61 struct ehci_fsl_priv *priv = dev_get_priv(dev); 62 const void *prop; 63 64 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type", 65 NULL); 66 if (prop) { 67 priv->phy_type = (char *)prop; 68 debug("phy_type %s\n", priv->phy_type); 69 } 70 71 return 0; 72 } 73 74 static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl) 75 { 76 struct usb_ehci *ehci = NULL; 77 struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv, 78 ehci); 79 #ifdef CONFIG_PPC 80 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base); 81 #else 82 ehci = (struct usb_ehci *)priv->hcd_base; 83 #endif 84 85 if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0) 86 return -ENXIO; 87 88 return 0; 89 } 90 91 static const struct ehci_ops fsl_ehci_ops = { 92 .init_after_reset = ehci_fsl_init_after_reset, 93 }; 94 95 static int ehci_fsl_probe(struct udevice *dev) 96 { 97 struct ehci_fsl_priv *priv = dev_get_priv(dev); 98 struct usb_ehci *ehci = NULL; 99 struct ehci_hccr *hccr; 100 struct ehci_hcor *hcor; 101 102 /* 103 * Get the base address for EHCI controller from the device node 104 */ 105 priv->hcd_base = devfdt_get_addr(dev); 106 if (priv->hcd_base == FDT_ADDR_T_NONE) { 107 debug("Can't get the EHCI register base address\n"); 108 return -ENXIO; 109 } 110 #ifdef CONFIG_PPC 111 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base); 112 #else 113 ehci = (struct usb_ehci *)priv->hcd_base; 114 #endif 115 hccr = (struct ehci_hccr *)(&ehci->caplength); 116 hcor = (struct ehci_hcor *) 117 ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 118 119 if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0) 120 return -ENXIO; 121 122 debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n", 123 (void *)hccr, (void *)hcor, 124 HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 125 126 return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST); 127 } 128 129 static const struct udevice_id ehci_usb_ids[] = { 130 { .compatible = "fsl-usb2-mph", }, 131 { .compatible = "fsl-usb2-dr", }, 132 { } 133 }; 134 135 U_BOOT_DRIVER(ehci_fsl) = { 136 .name = "ehci_fsl", 137 .id = UCLASS_USB, 138 .of_match = ehci_usb_ids, 139 .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata, 140 .probe = ehci_fsl_probe, 141 .remove = ehci_deregister, 142 .ops = &ehci_usb_ops, 143 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 144 .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv), 145 .flags = DM_FLAG_ALLOC_PRIV_DMA, 146 }; 147 #else 148 /* 149 * Create the appropriate control structures to manage 150 * a new EHCI host controller. 151 * 152 * Excerpts from linux ehci fsl driver. 153 */ 154 int ehci_hcd_init(int index, enum usb_init_type init, 155 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 156 { 157 struct usb_ehci *ehci = NULL; 158 159 switch (index) { 160 case 0: 161 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; 162 break; 163 case 1: 164 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; 165 break; 166 default: 167 printf("ERROR: wrong controller index!!\n"); 168 return -EINVAL; 169 }; 170 171 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 172 *hcor = (struct ehci_hcor *)((uint32_t) *hccr + 173 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 174 175 return ehci_fsl_init(index, ehci, *hccr, *hcor); 176 } 177 178 /* 179 * Destroy the appropriate control structures corresponding 180 * the the EHCI host controller. 181 */ 182 int ehci_hcd_stop(int index) 183 { 184 return 0; 185 } 186 #endif 187 188 #if CONFIG_IS_ENABLED(DM_USB) 189 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, 190 struct ehci_hccr *hccr, struct ehci_hcor *hcor) 191 #else 192 static int ehci_fsl_init(int index, struct usb_ehci *ehci, 193 struct ehci_hccr *hccr, struct ehci_hcor *hcor) 194 #endif 195 { 196 const char *phy_type = NULL; 197 #if !CONFIG_IS_ENABLED(DM_USB) 198 size_t len; 199 char current_usb_controller[5]; 200 #endif 201 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 202 char usb_phy[5]; 203 204 usb_phy[0] = '\0'; 205 #endif 206 if (has_erratum_a007075()) { 207 /* 208 * A 5ms delay is needed after applying soft-reset to the 209 * controller to let external ULPI phy come out of reset. 210 * This delay needs to be added before re-initializing 211 * the controller after soft-resetting completes 212 */ 213 mdelay(5); 214 } 215 216 /* Set to Host mode */ 217 setbits_le32(&ehci->usbmode, CM_HOST); 218 219 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB); 220 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); 221 222 /* Init phy */ 223 #if CONFIG_IS_ENABLED(DM_USB) 224 if (priv->phy_type) 225 phy_type = priv->phy_type; 226 #else 227 memset(current_usb_controller, '\0', 5); 228 snprintf(current_usb_controller, sizeof(current_usb_controller), 229 "usb%d", index+1); 230 231 if (hwconfig_sub(current_usb_controller, "phy_type")) 232 phy_type = hwconfig_subarg(current_usb_controller, 233 "phy_type", &len); 234 #endif 235 else 236 phy_type = env_get("usb_phy_type"); 237 238 if (!phy_type) { 239 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 240 /* if none specified assume internal UTMI */ 241 strcpy(usb_phy, "utmi"); 242 phy_type = usb_phy; 243 #else 244 printf("WARNING: USB phy type not defined !!\n"); 245 return -1; 246 #endif 247 } 248 249 if (!strncmp(phy_type, "utmi", 4)) { 250 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) 251 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 252 PHY_CLK_SEL_UTMI); 253 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 254 UTMI_PHY_EN); 255 udelay(1000); /* delay required for PHY Clk to appear */ 256 #endif 257 out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI); 258 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 259 USB_EN); 260 } else { 261 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, 262 PHY_CLK_SEL_ULPI); 263 clrsetbits_be32(&ehci->control, UTMI_PHY_EN | 264 CONTROL_REGISTER_W1C_MASK, USB_EN); 265 udelay(1000); /* delay required for PHY Clk to appear */ 266 if (!usb_phy_clk_valid(ehci)) 267 return -EINVAL; 268 out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI); 269 } 270 271 out_be32(&ehci->prictrl, 0x0000000c); 272 out_be32(&ehci->age_cnt_limit, 0x00000040); 273 out_be32(&ehci->sictrl, 0x00000001); 274 275 in_le32(&ehci->usbmode); 276 277 if (has_erratum_a007798()) 278 set_txfifothresh(ehci, TXFIFOTHRESH); 279 280 if (has_erratum_a004477()) { 281 /* 282 * When reset is issued while any ULPI transaction is ongoing 283 * then it may result to corruption of ULPI Function Control 284 * Register which eventually causes phy clock to enter low 285 * power mode which stops the clock. Thus delay is required 286 * before reset to let ongoing ULPI transaction complete. 287 */ 288 udelay(1); 289 } 290 return 0; 291 } 292 293 /* 294 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register 295 * to counter DDR latencies in writing data into Tx buffer. 296 * This prevents Tx buffer from getting underrun 297 */ 298 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh) 299 { 300 u32 cmd; 301 cmd = ehci_readl(&ehci->txfilltuning); 302 cmd &= ~TXFIFO_THRESH_MASK; 303 cmd |= TXFIFO_THRESH(txfifo_thresh); 304 ehci_writel(&ehci->txfilltuning, cmd); 305 } 306