1*7590d3ceSRajeshwari Shinde /* 2*7590d3ceSRajeshwari Shinde * SAMSUNG EXYNOS USB HOST EHCI Controller 3*7590d3ceSRajeshwari Shinde * 4*7590d3ceSRajeshwari Shinde * Copyright (C) 2012 Samsung Electronics Co.Ltd 5*7590d3ceSRajeshwari Shinde * Vivek Gautam <gautam.vivek@samsung.com> 6*7590d3ceSRajeshwari Shinde * 7*7590d3ceSRajeshwari Shinde * This program is free software; you can redistribute it and/or 8*7590d3ceSRajeshwari Shinde * modify it under the terms of the GNU General Public License as 9*7590d3ceSRajeshwari Shinde * published by the Free Software Foundation; either version 2 of 10*7590d3ceSRajeshwari Shinde * the License, or (at your option) any later version. 11*7590d3ceSRajeshwari Shinde * 12*7590d3ceSRajeshwari Shinde * This program is distributed in the hope that it will be useful, 13*7590d3ceSRajeshwari Shinde * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*7590d3ceSRajeshwari Shinde * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*7590d3ceSRajeshwari Shinde * GNU General Public License for more details. 16*7590d3ceSRajeshwari Shinde * 17*7590d3ceSRajeshwari Shinde * You should have received a copy of the GNU General Public License 18*7590d3ceSRajeshwari Shinde * along with this program; if not, write to the Free Software 19*7590d3ceSRajeshwari Shinde * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 20*7590d3ceSRajeshwari Shinde * MA 02110-1301 USA 21*7590d3ceSRajeshwari Shinde */ 22*7590d3ceSRajeshwari Shinde 23*7590d3ceSRajeshwari Shinde #include <common.h> 24*7590d3ceSRajeshwari Shinde #include <usb.h> 25*7590d3ceSRajeshwari Shinde #include <asm/arch/cpu.h> 26*7590d3ceSRajeshwari Shinde #include <asm/arch/ehci.h> 27*7590d3ceSRajeshwari Shinde #include "ehci.h" 28*7590d3ceSRajeshwari Shinde #include "ehci-core.h" 29*7590d3ceSRajeshwari Shinde 30*7590d3ceSRajeshwari Shinde /* Setup the EHCI host controller. */ 31*7590d3ceSRajeshwari Shinde static void setup_usb_phy(struct exynos_usb_phy *usb) 32*7590d3ceSRajeshwari Shinde { 33*7590d3ceSRajeshwari Shinde clrbits_le32(&usb->usbphyctrl0, 34*7590d3ceSRajeshwari Shinde HOST_CTRL0_FSEL_MASK | 35*7590d3ceSRajeshwari Shinde HOST_CTRL0_COMMONON_N | 36*7590d3ceSRajeshwari Shinde /* HOST Phy setting */ 37*7590d3ceSRajeshwari Shinde HOST_CTRL0_PHYSWRST | 38*7590d3ceSRajeshwari Shinde HOST_CTRL0_PHYSWRSTALL | 39*7590d3ceSRajeshwari Shinde HOST_CTRL0_SIDDQ | 40*7590d3ceSRajeshwari Shinde HOST_CTRL0_FORCESUSPEND | 41*7590d3ceSRajeshwari Shinde HOST_CTRL0_FORCESLEEP); 42*7590d3ceSRajeshwari Shinde 43*7590d3ceSRajeshwari Shinde setbits_le32(&usb->usbphyctrl0, 44*7590d3ceSRajeshwari Shinde /* Setting up the ref freq */ 45*7590d3ceSRajeshwari Shinde (CLK_24MHZ << 16) | 46*7590d3ceSRajeshwari Shinde /* HOST Phy setting */ 47*7590d3ceSRajeshwari Shinde HOST_CTRL0_LINKSWRST | 48*7590d3ceSRajeshwari Shinde HOST_CTRL0_UTMISWRST); 49*7590d3ceSRajeshwari Shinde udelay(10); 50*7590d3ceSRajeshwari Shinde clrbits_le32(&usb->usbphyctrl0, 51*7590d3ceSRajeshwari Shinde HOST_CTRL0_LINKSWRST | 52*7590d3ceSRajeshwari Shinde HOST_CTRL0_UTMISWRST); 53*7590d3ceSRajeshwari Shinde udelay(20); 54*7590d3ceSRajeshwari Shinde 55*7590d3ceSRajeshwari Shinde /* EHCI Ctrl setting */ 56*7590d3ceSRajeshwari Shinde setbits_le32(&usb->ehcictrl, 57*7590d3ceSRajeshwari Shinde EHCICTRL_ENAINCRXALIGN | 58*7590d3ceSRajeshwari Shinde EHCICTRL_ENAINCR4 | 59*7590d3ceSRajeshwari Shinde EHCICTRL_ENAINCR8 | 60*7590d3ceSRajeshwari Shinde EHCICTRL_ENAINCR16); 61*7590d3ceSRajeshwari Shinde } 62*7590d3ceSRajeshwari Shinde 63*7590d3ceSRajeshwari Shinde /* Reset the EHCI host controller. */ 64*7590d3ceSRajeshwari Shinde static void reset_usb_phy(struct exynos_usb_phy *usb) 65*7590d3ceSRajeshwari Shinde { 66*7590d3ceSRajeshwari Shinde /* HOST_PHY reset */ 67*7590d3ceSRajeshwari Shinde setbits_le32(&usb->usbphyctrl0, 68*7590d3ceSRajeshwari Shinde HOST_CTRL0_PHYSWRST | 69*7590d3ceSRajeshwari Shinde HOST_CTRL0_PHYSWRSTALL | 70*7590d3ceSRajeshwari Shinde HOST_CTRL0_SIDDQ | 71*7590d3ceSRajeshwari Shinde HOST_CTRL0_FORCESUSPEND | 72*7590d3ceSRajeshwari Shinde HOST_CTRL0_FORCESLEEP); 73*7590d3ceSRajeshwari Shinde } 74*7590d3ceSRajeshwari Shinde 75*7590d3ceSRajeshwari Shinde /* 76*7590d3ceSRajeshwari Shinde * EHCI-initialization 77*7590d3ceSRajeshwari Shinde * Create the appropriate control structures to manage 78*7590d3ceSRajeshwari Shinde * a new EHCI host controller. 79*7590d3ceSRajeshwari Shinde */ 80*7590d3ceSRajeshwari Shinde int ehci_hcd_init(void) 81*7590d3ceSRajeshwari Shinde { 82*7590d3ceSRajeshwari Shinde struct exynos_usb_phy *usb; 83*7590d3ceSRajeshwari Shinde 84*7590d3ceSRajeshwari Shinde usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); 85*7590d3ceSRajeshwari Shinde setup_usb_phy(usb); 86*7590d3ceSRajeshwari Shinde 87*7590d3ceSRajeshwari Shinde hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci(); 88*7590d3ceSRajeshwari Shinde hcor = (struct ehci_hcor *)((uint32_t) hccr 89*7590d3ceSRajeshwari Shinde + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 90*7590d3ceSRajeshwari Shinde 91*7590d3ceSRajeshwari Shinde debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n", 92*7590d3ceSRajeshwari Shinde (uint32_t)hccr, (uint32_t)hcor, 93*7590d3ceSRajeshwari Shinde (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 94*7590d3ceSRajeshwari Shinde 95*7590d3ceSRajeshwari Shinde return 0; 96*7590d3ceSRajeshwari Shinde } 97*7590d3ceSRajeshwari Shinde 98*7590d3ceSRajeshwari Shinde /* 99*7590d3ceSRajeshwari Shinde * Destroy the appropriate control structures corresponding 100*7590d3ceSRajeshwari Shinde * the EHCI host controller. 101*7590d3ceSRajeshwari Shinde */ 102*7590d3ceSRajeshwari Shinde int ehci_hcd_stop() 103*7590d3ceSRajeshwari Shinde { 104*7590d3ceSRajeshwari Shinde struct exynos_usb_phy *usb; 105*7590d3ceSRajeshwari Shinde 106*7590d3ceSRajeshwari Shinde usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); 107*7590d3ceSRajeshwari Shinde reset_usb_phy(usb); 108*7590d3ceSRajeshwari Shinde 109*7590d3ceSRajeshwari Shinde return 0; 110*7590d3ceSRajeshwari Shinde } 111