1 /* 2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <usb.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <phys2bus.h> 15 #include <usbroothubdes.h> 16 #include <asm/io.h> 17 18 #include "dwc2.h" 19 20 /* Use only HC channel 0. */ 21 #define DWC2_HC_CHANNEL 0 22 23 #define DWC2_STATUS_BUF_SIZE 64 24 #define DWC2_DATA_BUF_SIZE (64 * 1024) 25 26 #define MAX_DEVICE 16 27 #define MAX_ENDPOINT 16 28 29 struct dwc2_priv { 30 #ifdef CONFIG_DM_USB 31 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 32 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 33 #else 34 uint8_t *aligned_buffer; 35 uint8_t *status_buffer; 36 #endif 37 int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 38 struct dwc2_core_regs *regs; 39 int root_hub_devnum; 40 }; 41 42 #ifndef CONFIG_DM_USB 43 /* We need cacheline-aligned buffers for DMA transfers and dcache support */ 44 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 45 ARCH_DMA_MINALIGN); 46 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 47 ARCH_DMA_MINALIGN); 48 49 static struct dwc2_priv local; 50 #endif 51 52 /* 53 * DWC2 IP interface 54 */ 55 static int wait_for_bit(void *reg, const uint32_t mask, bool set) 56 { 57 unsigned int timeout = 1000000; 58 uint32_t val; 59 60 while (--timeout) { 61 val = readl(reg); 62 if (!set) 63 val = ~val; 64 65 if ((val & mask) == mask) 66 return 0; 67 68 udelay(1); 69 } 70 71 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 72 __func__, reg, mask, set); 73 74 return -ETIMEDOUT; 75 } 76 77 /* 78 * Initializes the FSLSPClkSel field of the HCFG register 79 * depending on the PHY type. 80 */ 81 static void init_fslspclksel(struct dwc2_core_regs *regs) 82 { 83 uint32_t phyclk; 84 85 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 86 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 87 #else 88 /* High speed PHY running at full speed or high speed */ 89 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; 90 #endif 91 92 #ifdef CONFIG_DWC2_ULPI_FS_LS 93 uint32_t hwcfg2 = readl(®s->ghwcfg2); 94 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 95 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 96 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 97 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 98 99 if (hval == 2 && fval == 1) 100 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 101 #endif 102 103 clrsetbits_le32(®s->host_regs.hcfg, 104 DWC2_HCFG_FSLSPCLKSEL_MASK, 105 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); 106 } 107 108 /* 109 * Flush a Tx FIFO. 110 * 111 * @param regs Programming view of DWC_otg controller. 112 * @param num Tx FIFO to flush. 113 */ 114 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) 115 { 116 int ret; 117 118 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), 119 ®s->grstctl); 120 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0); 121 if (ret) 122 printf("%s: Timeout!\n", __func__); 123 124 /* Wait for 3 PHY Clocks */ 125 udelay(1); 126 } 127 128 /* 129 * Flush Rx FIFO. 130 * 131 * @param regs Programming view of DWC_otg controller. 132 */ 133 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) 134 { 135 int ret; 136 137 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); 138 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0); 139 if (ret) 140 printf("%s: Timeout!\n", __func__); 141 142 /* Wait for 3 PHY Clocks */ 143 udelay(1); 144 } 145 146 /* 147 * Do core a soft reset of the core. Be careful with this because it 148 * resets all the internal state machines of the core. 149 */ 150 static void dwc_otg_core_reset(struct dwc2_core_regs *regs) 151 { 152 int ret; 153 154 /* Wait for AHB master IDLE state. */ 155 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1); 156 if (ret) 157 printf("%s: Timeout!\n", __func__); 158 159 /* Core Soft Reset */ 160 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); 161 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0); 162 if (ret) 163 printf("%s: Timeout!\n", __func__); 164 165 /* 166 * Wait for core to come out of reset. 167 * NOTE: This long sleep is _very_ important, otherwise the core will 168 * not stay in host mode after a connector ID change! 169 */ 170 mdelay(100); 171 } 172 173 /* 174 * This function initializes the DWC_otg controller registers for 175 * host mode. 176 * 177 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the 178 * request queues. Host channels are reset to ensure that they are ready for 179 * performing transfers. 180 * 181 * @param regs Programming view of DWC_otg controller 182 * 183 */ 184 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs) 185 { 186 uint32_t nptxfifosize = 0; 187 uint32_t ptxfifosize = 0; 188 uint32_t hprt0 = 0; 189 int i, ret, num_channels; 190 191 /* Restart the Phy Clock */ 192 writel(0, ®s->pcgcctl); 193 194 /* Initialize Host Configuration Register */ 195 init_fslspclksel(regs); 196 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL 197 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); 198 #endif 199 200 /* Configure data FIFO sizes */ 201 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO 202 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { 203 /* Rx FIFO */ 204 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); 205 206 /* Non-periodic Tx FIFO */ 207 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << 208 DWC2_FIFOSIZE_DEPTH_OFFSET; 209 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << 210 DWC2_FIFOSIZE_STARTADDR_OFFSET; 211 writel(nptxfifosize, ®s->gnptxfsiz); 212 213 /* Periodic Tx FIFO */ 214 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << 215 DWC2_FIFOSIZE_DEPTH_OFFSET; 216 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + 217 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << 218 DWC2_FIFOSIZE_STARTADDR_OFFSET; 219 writel(ptxfifosize, ®s->hptxfsiz); 220 } 221 #endif 222 223 /* Clear Host Set HNP Enable in the OTG Control Register */ 224 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); 225 226 /* Make sure the FIFOs are flushed. */ 227 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ 228 dwc_otg_flush_rx_fifo(regs); 229 230 /* Flush out any leftover queued requests. */ 231 num_channels = readl(®s->ghwcfg2); 232 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; 233 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; 234 num_channels += 1; 235 236 for (i = 0; i < num_channels; i++) 237 clrsetbits_le32(®s->hc_regs[i].hcchar, 238 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, 239 DWC2_HCCHAR_CHDIS); 240 241 /* Halt all channels to put them into a known state. */ 242 for (i = 0; i < num_channels; i++) { 243 clrsetbits_le32(®s->hc_regs[i].hcchar, 244 DWC2_HCCHAR_EPDIR, 245 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); 246 ret = wait_for_bit(®s->hc_regs[i].hcchar, 247 DWC2_HCCHAR_CHEN, 0); 248 if (ret) 249 printf("%s: Timeout!\n", __func__); 250 } 251 252 /* Turn on the vbus power. */ 253 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { 254 hprt0 = readl(®s->hprt0); 255 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); 256 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); 257 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { 258 hprt0 |= DWC2_HPRT0_PRTPWR; 259 writel(hprt0, ®s->hprt0); 260 } 261 } 262 } 263 264 /* 265 * This function initializes the DWC_otg controller registers and 266 * prepares the core for device mode or host mode operation. 267 * 268 * @param regs Programming view of the DWC_otg controller 269 */ 270 static void dwc_otg_core_init(struct dwc2_core_regs *regs) 271 { 272 uint32_t ahbcfg = 0; 273 uint32_t usbcfg = 0; 274 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; 275 276 /* Common Initialization */ 277 usbcfg = readl(®s->gusbcfg); 278 279 /* Program the ULPI External VBUS bit if needed */ 280 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS 281 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 282 #else 283 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 284 #endif 285 286 /* Set external TS Dline pulsing */ 287 #ifdef CONFIG_DWC2_TS_DLINE 288 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 289 #else 290 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 291 #endif 292 writel(usbcfg, ®s->gusbcfg); 293 294 /* Reset the Controller */ 295 dwc_otg_core_reset(regs); 296 297 /* 298 * This programming sequence needs to happen in FS mode before 299 * any other programming occurs 300 */ 301 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ 302 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 303 /* If FS mode with FS PHY */ 304 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); 305 306 /* Reset after a PHY select */ 307 dwc_otg_core_reset(regs); 308 309 /* 310 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. 311 * Also do this on HNP Dev/Host mode switches (done in dev_init 312 * and host_init). 313 */ 314 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 315 init_fslspclksel(regs); 316 317 #ifdef CONFIG_DWC2_I2C_ENABLE 318 /* Program GUSBCFG.OtgUtmifsSel to I2C */ 319 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); 320 321 /* Program GI2CCTL.I2CEn */ 322 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | 323 DWC2_GI2CCTL_I2CDEVADDR_MASK, 324 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); 325 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); 326 #endif 327 328 #else 329 /* High speed PHY. */ 330 331 /* 332 * HS PHY parameters. These parameters are preserved during 333 * soft reset so only program the first time. Do a soft reset 334 * immediately after setting phyif. 335 */ 336 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); 337 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; 338 339 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ 340 #ifdef CONFIG_DWC2_PHY_ULPI_DDR 341 usbcfg |= DWC2_GUSBCFG_DDRSEL; 342 #else 343 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; 344 #endif 345 } else { /* UTMI+ interface */ 346 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16) 347 usbcfg |= DWC2_GUSBCFG_PHYIF; 348 #endif 349 } 350 351 writel(usbcfg, ®s->gusbcfg); 352 353 /* Reset after setting the PHY parameters */ 354 dwc_otg_core_reset(regs); 355 #endif 356 357 usbcfg = readl(®s->gusbcfg); 358 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); 359 #ifdef CONFIG_DWC2_ULPI_FS_LS 360 uint32_t hwcfg2 = readl(®s->ghwcfg2); 361 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 362 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 363 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 364 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 365 if (hval == 2 && fval == 1) { 366 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; 367 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; 368 } 369 #endif 370 writel(usbcfg, ®s->gusbcfg); 371 372 /* Program the GAHBCFG Register. */ 373 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { 374 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: 375 break; 376 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: 377 while (brst_sz > 1) { 378 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); 379 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; 380 brst_sz >>= 1; 381 } 382 383 #ifdef CONFIG_DWC2_DMA_ENABLE 384 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 385 #endif 386 break; 387 388 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: 389 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; 390 #ifdef CONFIG_DWC2_DMA_ENABLE 391 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 392 #endif 393 break; 394 } 395 396 writel(ahbcfg, ®s->gahbcfg); 397 398 /* Program the GUSBCFG register for HNP/SRP. */ 399 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP); 400 401 #ifdef CONFIG_DWC2_IC_USB_CAP 402 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP); 403 #endif 404 } 405 406 /* 407 * Prepares a host channel for transferring packets to/from a specific 408 * endpoint. The HCCHARn register is set up with the characteristics specified 409 * in _hc. Host channel interrupts that may need to be serviced while this 410 * transfer is in progress are enabled. 411 * 412 * @param regs Programming view of DWC_otg controller 413 * @param hc Information needed to initialize the host channel 414 */ 415 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, 416 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, 417 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) 418 { 419 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; 420 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | 421 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | 422 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | 423 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | 424 (max_packet << DWC2_HCCHAR_MPS_OFFSET); 425 426 if (dev->speed == USB_SPEED_LOW) 427 hcchar |= DWC2_HCCHAR_LSPDDEV; 428 429 /* 430 * Program the HCCHARn register with the endpoint characteristics 431 * for the current transfer. 432 */ 433 writel(hcchar, &hc_regs->hcchar); 434 435 /* Program the HCSPLIT register for SPLITs */ 436 writel(0, &hc_regs->hcsplt); 437 } 438 439 /* 440 * DWC2 to USB API interface 441 */ 442 /* Direction: In ; Request: Status */ 443 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, 444 struct usb_device *dev, void *buffer, 445 int txlen, struct devrequest *cmd) 446 { 447 uint32_t hprt0 = 0; 448 uint32_t port_status = 0; 449 uint32_t port_change = 0; 450 int len = 0; 451 int stat = 0; 452 453 switch (cmd->requesttype & ~USB_DIR_IN) { 454 case 0: 455 *(uint16_t *)buffer = cpu_to_le16(1); 456 len = 2; 457 break; 458 case USB_RECIP_INTERFACE: 459 case USB_RECIP_ENDPOINT: 460 *(uint16_t *)buffer = cpu_to_le16(0); 461 len = 2; 462 break; 463 case USB_TYPE_CLASS: 464 *(uint32_t *)buffer = cpu_to_le32(0); 465 len = 4; 466 break; 467 case USB_RECIP_OTHER | USB_TYPE_CLASS: 468 hprt0 = readl(®s->hprt0); 469 if (hprt0 & DWC2_HPRT0_PRTCONNSTS) 470 port_status |= USB_PORT_STAT_CONNECTION; 471 if (hprt0 & DWC2_HPRT0_PRTENA) 472 port_status |= USB_PORT_STAT_ENABLE; 473 if (hprt0 & DWC2_HPRT0_PRTSUSP) 474 port_status |= USB_PORT_STAT_SUSPEND; 475 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) 476 port_status |= USB_PORT_STAT_OVERCURRENT; 477 if (hprt0 & DWC2_HPRT0_PRTRST) 478 port_status |= USB_PORT_STAT_RESET; 479 if (hprt0 & DWC2_HPRT0_PRTPWR) 480 port_status |= USB_PORT_STAT_POWER; 481 482 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) 483 port_status |= USB_PORT_STAT_LOW_SPEED; 484 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 485 DWC2_HPRT0_PRTSPD_HIGH) 486 port_status |= USB_PORT_STAT_HIGH_SPEED; 487 488 if (hprt0 & DWC2_HPRT0_PRTENCHNG) 489 port_change |= USB_PORT_STAT_C_ENABLE; 490 if (hprt0 & DWC2_HPRT0_PRTCONNDET) 491 port_change |= USB_PORT_STAT_C_CONNECTION; 492 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) 493 port_change |= USB_PORT_STAT_C_OVERCURRENT; 494 495 *(uint32_t *)buffer = cpu_to_le32(port_status | 496 (port_change << 16)); 497 len = 4; 498 break; 499 default: 500 puts("unsupported root hub command\n"); 501 stat = USB_ST_STALLED; 502 } 503 504 dev->act_len = min(len, txlen); 505 dev->status = stat; 506 507 return stat; 508 } 509 510 /* Direction: In ; Request: Descriptor */ 511 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, 512 void *buffer, int txlen, 513 struct devrequest *cmd) 514 { 515 unsigned char data[32]; 516 uint32_t dsc; 517 int len = 0; 518 int stat = 0; 519 uint16_t wValue = cpu_to_le16(cmd->value); 520 uint16_t wLength = cpu_to_le16(cmd->length); 521 522 switch (cmd->requesttype & ~USB_DIR_IN) { 523 case 0: 524 switch (wValue & 0xff00) { 525 case 0x0100: /* device descriptor */ 526 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); 527 memcpy(buffer, root_hub_dev_des, len); 528 break; 529 case 0x0200: /* configuration descriptor */ 530 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); 531 memcpy(buffer, root_hub_config_des, len); 532 break; 533 case 0x0300: /* string descriptors */ 534 switch (wValue & 0xff) { 535 case 0x00: 536 len = min3(txlen, (int)sizeof(root_hub_str_index0), 537 (int)wLength); 538 memcpy(buffer, root_hub_str_index0, len); 539 break; 540 case 0x01: 541 len = min3(txlen, (int)sizeof(root_hub_str_index1), 542 (int)wLength); 543 memcpy(buffer, root_hub_str_index1, len); 544 break; 545 } 546 break; 547 default: 548 stat = USB_ST_STALLED; 549 } 550 break; 551 552 case USB_TYPE_CLASS: 553 /* Root port config, set 1 port and nothing else. */ 554 dsc = 0x00000001; 555 556 data[0] = 9; /* min length; */ 557 data[1] = 0x29; 558 data[2] = dsc & RH_A_NDP; 559 data[3] = 0; 560 if (dsc & RH_A_PSM) 561 data[3] |= 0x1; 562 if (dsc & RH_A_NOCP) 563 data[3] |= 0x10; 564 else if (dsc & RH_A_OCPM) 565 data[3] |= 0x8; 566 567 /* corresponds to data[4-7] */ 568 data[5] = (dsc & RH_A_POTPGT) >> 24; 569 data[7] = dsc & RH_B_DR; 570 if (data[2] < 7) { 571 data[8] = 0xff; 572 } else { 573 data[0] += 2; 574 data[8] = (dsc & RH_B_DR) >> 8; 575 data[9] = 0xff; 576 data[10] = data[9]; 577 } 578 579 len = min3(txlen, (int)data[0], (int)wLength); 580 memcpy(buffer, data, len); 581 break; 582 default: 583 puts("unsupported root hub command\n"); 584 stat = USB_ST_STALLED; 585 } 586 587 dev->act_len = min(len, txlen); 588 dev->status = stat; 589 590 return stat; 591 } 592 593 /* Direction: In ; Request: Configuration */ 594 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, 595 void *buffer, int txlen, 596 struct devrequest *cmd) 597 { 598 int len = 0; 599 int stat = 0; 600 601 switch (cmd->requesttype & ~USB_DIR_IN) { 602 case 0: 603 *(uint8_t *)buffer = 0x01; 604 len = 1; 605 break; 606 default: 607 puts("unsupported root hub command\n"); 608 stat = USB_ST_STALLED; 609 } 610 611 dev->act_len = min(len, txlen); 612 dev->status = stat; 613 614 return stat; 615 } 616 617 /* Direction: In */ 618 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, 619 struct usb_device *dev, void *buffer, 620 int txlen, struct devrequest *cmd) 621 { 622 switch (cmd->request) { 623 case USB_REQ_GET_STATUS: 624 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, 625 txlen, cmd); 626 case USB_REQ_GET_DESCRIPTOR: 627 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, 628 txlen, cmd); 629 case USB_REQ_GET_CONFIGURATION: 630 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, 631 txlen, cmd); 632 default: 633 puts("unsupported root hub command\n"); 634 return USB_ST_STALLED; 635 } 636 } 637 638 /* Direction: Out */ 639 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, 640 struct usb_device *dev, 641 void *buffer, int txlen, 642 struct devrequest *cmd) 643 { 644 struct dwc2_core_regs *regs = priv->regs; 645 int len = 0; 646 int stat = 0; 647 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); 648 uint16_t wValue = cpu_to_le16(cmd->value); 649 650 switch (bmrtype_breq & ~USB_DIR_IN) { 651 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: 652 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: 653 break; 654 655 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 656 switch (wValue) { 657 case USB_PORT_FEAT_C_CONNECTION: 658 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); 659 break; 660 } 661 break; 662 663 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 664 switch (wValue) { 665 case USB_PORT_FEAT_SUSPEND: 666 break; 667 668 case USB_PORT_FEAT_RESET: 669 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 670 DWC2_HPRT0_PRTCONNDET | 671 DWC2_HPRT0_PRTENCHNG | 672 DWC2_HPRT0_PRTOVRCURRCHNG, 673 DWC2_HPRT0_PRTRST); 674 mdelay(50); 675 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); 676 break; 677 678 case USB_PORT_FEAT_POWER: 679 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 680 DWC2_HPRT0_PRTCONNDET | 681 DWC2_HPRT0_PRTENCHNG | 682 DWC2_HPRT0_PRTOVRCURRCHNG, 683 DWC2_HPRT0_PRTRST); 684 break; 685 686 case USB_PORT_FEAT_ENABLE: 687 break; 688 } 689 break; 690 case (USB_REQ_SET_ADDRESS << 8): 691 priv->root_hub_devnum = wValue; 692 break; 693 case (USB_REQ_SET_CONFIGURATION << 8): 694 break; 695 default: 696 puts("unsupported root hub command\n"); 697 stat = USB_ST_STALLED; 698 } 699 700 len = min(len, txlen); 701 702 dev->act_len = len; 703 dev->status = stat; 704 705 return stat; 706 } 707 708 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, 709 unsigned long pipe, void *buffer, int txlen, 710 struct devrequest *cmd) 711 { 712 int stat = 0; 713 714 if (usb_pipeint(pipe)) { 715 puts("Root-Hub submit IRQ: NOT implemented\n"); 716 return 0; 717 } 718 719 if (cmd->requesttype & USB_DIR_IN) 720 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); 721 else 722 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); 723 724 mdelay(1); 725 726 return stat; 727 } 728 729 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, int *toggle) 730 { 731 int ret; 732 uint32_t hcint, hctsiz; 733 734 ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true); 735 if (ret) 736 return ret; 737 738 hcint = readl(&hc_regs->hcint); 739 hctsiz = readl(&hc_regs->hctsiz); 740 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> 741 DWC2_HCTSIZ_XFERSIZE_OFFSET; 742 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; 743 744 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, 745 *toggle); 746 747 if (hcint & DWC2_HCINT_XFERCOMP) 748 return 0; 749 750 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) 751 return -EAGAIN; 752 753 debug("%s: Error (HCINT=%08x)\n", __func__, hcint); 754 return -EINVAL; 755 } 756 757 static int dwc2_eptype[] = { 758 DWC2_HCCHAR_EPTYPE_ISOC, 759 DWC2_HCCHAR_EPTYPE_INTR, 760 DWC2_HCCHAR_EPTYPE_CONTROL, 761 DWC2_HCCHAR_EPTYPE_BULK, 762 }; 763 764 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, 765 int *pid, int in, void *buffer, int num_packets, 766 int xfer_len, int *actual_len) 767 { 768 int ret = 0; 769 uint32_t sub; 770 771 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, 772 *pid, xfer_len, num_packets); 773 774 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | 775 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | 776 (*pid << DWC2_HCTSIZ_PID_OFFSET), 777 &hc_regs->hctsiz); 778 779 if (!in && xfer_len) { 780 memcpy(aligned_buffer, buffer, xfer_len); 781 782 flush_dcache_range((unsigned long)aligned_buffer, 783 (unsigned long)aligned_buffer + 784 roundup(xfer_len, ARCH_DMA_MINALIGN)); 785 } 786 787 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); 788 789 /* Clear old interrupt conditions for this host channel. */ 790 writel(0x3fff, &hc_regs->hcint); 791 792 /* Set host channel enable after all other setup is complete. */ 793 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | 794 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS, 795 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | 796 DWC2_HCCHAR_CHEN); 797 798 ret = wait_for_chhltd(hc_regs, &sub, pid); 799 if (ret < 0) 800 return ret; 801 802 if (in) { 803 xfer_len -= sub; 804 805 invalidate_dcache_range((unsigned long)aligned_buffer, 806 (unsigned long)aligned_buffer + 807 roundup(xfer_len, ARCH_DMA_MINALIGN)); 808 809 memcpy(buffer, aligned_buffer, xfer_len); 810 } 811 *actual_len = xfer_len; 812 813 return ret; 814 } 815 816 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, 817 unsigned long pipe, int *pid, int in, void *buffer, int len) 818 { 819 struct dwc2_core_regs *regs = priv->regs; 820 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 821 int devnum = usb_pipedevice(pipe); 822 int ep = usb_pipeendpoint(pipe); 823 int max = usb_maxpacket(dev, pipe); 824 int eptype = dwc2_eptype[usb_pipetype(pipe)]; 825 int done = 0; 826 int ret = 0; 827 uint32_t xfer_len; 828 uint32_t num_packets; 829 int stop_transfer = 0; 830 uint32_t max_xfer_len; 831 832 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, 833 in, len); 834 835 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; 836 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) 837 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; 838 if (max_xfer_len > DWC2_DATA_BUF_SIZE) 839 max_xfer_len = DWC2_DATA_BUF_SIZE; 840 841 /* Make sure that max_xfer_len is a multiple of max packet size. */ 842 num_packets = max_xfer_len / max; 843 max_xfer_len = num_packets * max; 844 845 /* Initialize channel */ 846 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, 847 eptype, max); 848 849 do { 850 int actual_len = 0; 851 xfer_len = len - done; 852 853 if (xfer_len > max_xfer_len) 854 xfer_len = max_xfer_len; 855 else if (xfer_len > max) 856 num_packets = (xfer_len + max - 1) / max; 857 else 858 num_packets = 1; 859 860 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, 861 in, (char *)buffer + done, num_packets, 862 xfer_len, &actual_len); 863 864 if (ret) 865 break; 866 867 if (actual_len < xfer_len) 868 stop_transfer = 1; 869 870 done += actual_len; 871 872 } while ((done < len) && !stop_transfer); 873 874 writel(0, &hc_regs->hcintmsk); 875 writel(0xFFFFFFFF, &hc_regs->hcint); 876 877 dev->status = 0; 878 dev->act_len = done; 879 880 return ret; 881 } 882 883 /* U-Boot USB transmission interface */ 884 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, 885 unsigned long pipe, void *buffer, int len) 886 { 887 int devnum = usb_pipedevice(pipe); 888 int ep = usb_pipeendpoint(pipe); 889 890 if (devnum == priv->root_hub_devnum) { 891 dev->status = 0; 892 return -EINVAL; 893 } 894 895 return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep], 896 usb_pipein(pipe), buffer, len); 897 } 898 899 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, 900 unsigned long pipe, void *buffer, int len, 901 struct devrequest *setup) 902 { 903 int devnum = usb_pipedevice(pipe); 904 int pid, ret, act_len; 905 /* For CONTROL endpoint pid should start with DATA1 */ 906 int status_direction; 907 908 if (devnum == priv->root_hub_devnum) { 909 dev->status = 0; 910 dev->speed = USB_SPEED_HIGH; 911 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, 912 setup); 913 } 914 915 pid = DWC2_HC_PID_SETUP; 916 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8); 917 if (ret) 918 return ret; 919 920 if (buffer) { 921 pid = DWC2_HC_PID_DATA1; 922 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), buffer, 923 len); 924 if (ret) 925 return ret; 926 act_len = dev->act_len; 927 } /* End of DATA stage */ 928 else 929 act_len = 0; 930 931 /* STATUS stage */ 932 if ((len == 0) || usb_pipeout(pipe)) 933 status_direction = 1; 934 else 935 status_direction = 0; 936 937 pid = DWC2_HC_PID_DATA1; 938 ret = chunk_msg(priv, dev, pipe, &pid, status_direction, 939 priv->status_buffer, 0); 940 if (ret) 941 return ret; 942 943 dev->act_len = act_len; 944 945 return 0; 946 } 947 948 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, 949 unsigned long pipe, void *buffer, int len, int interval) 950 { 951 unsigned long timeout; 952 int ret; 953 954 /* FIXME: what is interval? */ 955 956 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 957 for (;;) { 958 if (get_timer(0) > timeout) { 959 printf("Timeout poll on interrupt endpoint\n"); 960 return -ETIMEDOUT; 961 } 962 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); 963 if (ret != -EAGAIN) 964 return ret; 965 } 966 } 967 968 static int dwc2_init_common(struct dwc2_priv *priv) 969 { 970 struct dwc2_core_regs *regs = priv->regs; 971 uint32_t snpsid; 972 int i, j; 973 974 snpsid = readl(®s->gsnpsid); 975 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff); 976 977 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && 978 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { 979 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid); 980 return -ENODEV; 981 } 982 983 dwc_otg_core_init(regs); 984 dwc_otg_core_host_init(regs); 985 986 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 987 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 988 DWC2_HPRT0_PRTOVRCURRCHNG, 989 DWC2_HPRT0_PRTRST); 990 mdelay(50); 991 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | 992 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | 993 DWC2_HPRT0_PRTRST); 994 995 for (i = 0; i < MAX_DEVICE; i++) { 996 for (j = 0; j < MAX_ENDPOINT; j++) 997 priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0; 998 } 999 1000 return 0; 1001 } 1002 1003 static void dwc2_uninit_common(struct dwc2_core_regs *regs) 1004 { 1005 /* Put everything in reset. */ 1006 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1007 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1008 DWC2_HPRT0_PRTOVRCURRCHNG, 1009 DWC2_HPRT0_PRTRST); 1010 } 1011 1012 #ifndef CONFIG_DM_USB 1013 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1014 int len, struct devrequest *setup) 1015 { 1016 return _submit_control_msg(&local, dev, pipe, buffer, len, setup); 1017 } 1018 1019 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1020 int len) 1021 { 1022 return _submit_bulk_msg(&local, dev, pipe, buffer, len); 1023 } 1024 1025 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1026 int len, int interval) 1027 { 1028 return _submit_int_msg(&local, dev, pipe, buffer, len, interval); 1029 } 1030 1031 /* U-Boot USB control interface */ 1032 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1033 { 1034 struct dwc2_priv *priv = &local; 1035 1036 memset(priv, '\0', sizeof(*priv)); 1037 priv->root_hub_devnum = 0; 1038 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; 1039 priv->aligned_buffer = aligned_buffer_addr; 1040 priv->status_buffer = status_buffer_addr; 1041 1042 /* board-dependant init */ 1043 if (board_usb_init(index, USB_INIT_HOST)) 1044 return -1; 1045 1046 return dwc2_init_common(priv); 1047 } 1048 1049 int usb_lowlevel_stop(int index) 1050 { 1051 dwc2_uninit_common(local.regs); 1052 1053 return 0; 1054 } 1055 #endif 1056 1057 #ifdef CONFIG_DM_USB 1058 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1059 unsigned long pipe, void *buffer, int length, 1060 struct devrequest *setup) 1061 { 1062 struct dwc2_priv *priv = dev_get_priv(dev); 1063 1064 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1065 dev->name, udev, udev->dev->name, udev->portnr); 1066 1067 return _submit_control_msg(priv, udev, pipe, buffer, length, setup); 1068 } 1069 1070 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1071 unsigned long pipe, void *buffer, int length) 1072 { 1073 struct dwc2_priv *priv = dev_get_priv(dev); 1074 1075 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1076 1077 return _submit_bulk_msg(priv, udev, pipe, buffer, length); 1078 } 1079 1080 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1081 unsigned long pipe, void *buffer, int length, 1082 int interval) 1083 { 1084 struct dwc2_priv *priv = dev_get_priv(dev); 1085 1086 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1087 1088 return _submit_int_msg(priv, udev, pipe, buffer, length, interval); 1089 } 1090 1091 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) 1092 { 1093 struct dwc2_priv *priv = dev_get_priv(dev); 1094 fdt_addr_t addr; 1095 1096 addr = dev_get_addr(dev); 1097 if (addr == FDT_ADDR_T_NONE) 1098 return -EINVAL; 1099 priv->regs = (struct dwc2_core_regs *)addr; 1100 1101 return 0; 1102 } 1103 1104 static int dwc2_usb_probe(struct udevice *dev) 1105 { 1106 struct dwc2_priv *priv = dev_get_priv(dev); 1107 1108 return dwc2_init_common(priv); 1109 } 1110 1111 static int dwc2_usb_remove(struct udevice *dev) 1112 { 1113 struct dwc2_priv *priv = dev_get_priv(dev); 1114 1115 dwc2_uninit_common(priv->regs); 1116 1117 return 0; 1118 } 1119 1120 struct dm_usb_ops dwc2_usb_ops = { 1121 .control = dwc2_submit_control_msg, 1122 .bulk = dwc2_submit_bulk_msg, 1123 .interrupt = dwc2_submit_int_msg, 1124 }; 1125 1126 static const struct udevice_id dwc2_usb_ids[] = { 1127 { .compatible = "brcm,bcm2835-usb" }, 1128 { .compatible = "snps,dwc2" }, 1129 { } 1130 }; 1131 1132 U_BOOT_DRIVER(usb_dwc2) = { 1133 .name = "dwc2_usb", 1134 .id = UCLASS_USB, 1135 .of_match = dwc2_usb_ids, 1136 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, 1137 .probe = dwc2_usb_probe, 1138 .remove = dwc2_usb_remove, 1139 .ops = &dwc2_usb_ops, 1140 .priv_auto_alloc_size = sizeof(struct dwc2_priv), 1141 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1142 }; 1143 #endif 1144