1 /* 2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <usb.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <phys2bus.h> 15 #include <usbroothubdes.h> 16 #include <asm/io.h> 17 18 #include "dwc2.h" 19 20 /* Use only HC channel 0. */ 21 #define DWC2_HC_CHANNEL 0 22 23 #define DWC2_STATUS_BUF_SIZE 64 24 #define DWC2_DATA_BUF_SIZE (64 * 1024) 25 26 #define MAX_DEVICE 16 27 #define MAX_ENDPOINT 16 28 29 struct dwc2_priv { 30 #ifdef CONFIG_DM_USB 31 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 32 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 33 #else 34 uint8_t *aligned_buffer; 35 uint8_t *status_buffer; 36 #endif 37 int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 38 struct dwc2_core_regs *regs; 39 int root_hub_devnum; 40 }; 41 42 #ifndef CONFIG_DM_USB 43 /* We need cacheline-aligned buffers for DMA transfers and dcache support */ 44 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 45 ARCH_DMA_MINALIGN); 46 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 47 ARCH_DMA_MINALIGN); 48 49 static struct dwc2_priv local; 50 #endif 51 52 /* 53 * DWC2 IP interface 54 */ 55 static int wait_for_bit(void *reg, const uint32_t mask, bool set) 56 { 57 unsigned int timeout = 1000000; 58 uint32_t val; 59 60 while (--timeout) { 61 val = readl(reg); 62 if (!set) 63 val = ~val; 64 65 if ((val & mask) == mask) 66 return 0; 67 68 udelay(1); 69 } 70 71 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 72 __func__, reg, mask, set); 73 74 return -ETIMEDOUT; 75 } 76 77 /* 78 * Initializes the FSLSPClkSel field of the HCFG register 79 * depending on the PHY type. 80 */ 81 static void init_fslspclksel(struct dwc2_core_regs *regs) 82 { 83 uint32_t phyclk; 84 85 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 86 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 87 #else 88 /* High speed PHY running at full speed or high speed */ 89 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; 90 #endif 91 92 #ifdef CONFIG_DWC2_ULPI_FS_LS 93 uint32_t hwcfg2 = readl(®s->ghwcfg2); 94 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 95 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 96 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 97 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 98 99 if (hval == 2 && fval == 1) 100 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 101 #endif 102 103 clrsetbits_le32(®s->host_regs.hcfg, 104 DWC2_HCFG_FSLSPCLKSEL_MASK, 105 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); 106 } 107 108 /* 109 * Flush a Tx FIFO. 110 * 111 * @param regs Programming view of DWC_otg controller. 112 * @param num Tx FIFO to flush. 113 */ 114 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) 115 { 116 int ret; 117 118 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), 119 ®s->grstctl); 120 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0); 121 if (ret) 122 printf("%s: Timeout!\n", __func__); 123 124 /* Wait for 3 PHY Clocks */ 125 udelay(1); 126 } 127 128 /* 129 * Flush Rx FIFO. 130 * 131 * @param regs Programming view of DWC_otg controller. 132 */ 133 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) 134 { 135 int ret; 136 137 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); 138 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0); 139 if (ret) 140 printf("%s: Timeout!\n", __func__); 141 142 /* Wait for 3 PHY Clocks */ 143 udelay(1); 144 } 145 146 /* 147 * Do core a soft reset of the core. Be careful with this because it 148 * resets all the internal state machines of the core. 149 */ 150 static void dwc_otg_core_reset(struct dwc2_core_regs *regs) 151 { 152 int ret; 153 154 /* Wait for AHB master IDLE state. */ 155 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1); 156 if (ret) 157 printf("%s: Timeout!\n", __func__); 158 159 /* Core Soft Reset */ 160 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); 161 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0); 162 if (ret) 163 printf("%s: Timeout!\n", __func__); 164 165 /* 166 * Wait for core to come out of reset. 167 * NOTE: This long sleep is _very_ important, otherwise the core will 168 * not stay in host mode after a connector ID change! 169 */ 170 mdelay(100); 171 } 172 173 /* 174 * This function initializes the DWC_otg controller registers for 175 * host mode. 176 * 177 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the 178 * request queues. Host channels are reset to ensure that they are ready for 179 * performing transfers. 180 * 181 * @param regs Programming view of DWC_otg controller 182 * 183 */ 184 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs) 185 { 186 uint32_t nptxfifosize = 0; 187 uint32_t ptxfifosize = 0; 188 uint32_t hprt0 = 0; 189 int i, ret, num_channels; 190 191 /* Restart the Phy Clock */ 192 writel(0, ®s->pcgcctl); 193 194 /* Initialize Host Configuration Register */ 195 init_fslspclksel(regs); 196 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL 197 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); 198 #endif 199 200 /* Configure data FIFO sizes */ 201 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO 202 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { 203 /* Rx FIFO */ 204 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); 205 206 /* Non-periodic Tx FIFO */ 207 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << 208 DWC2_FIFOSIZE_DEPTH_OFFSET; 209 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << 210 DWC2_FIFOSIZE_STARTADDR_OFFSET; 211 writel(nptxfifosize, ®s->gnptxfsiz); 212 213 /* Periodic Tx FIFO */ 214 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << 215 DWC2_FIFOSIZE_DEPTH_OFFSET; 216 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + 217 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << 218 DWC2_FIFOSIZE_STARTADDR_OFFSET; 219 writel(ptxfifosize, ®s->hptxfsiz); 220 } 221 #endif 222 223 /* Clear Host Set HNP Enable in the OTG Control Register */ 224 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); 225 226 /* Make sure the FIFOs are flushed. */ 227 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ 228 dwc_otg_flush_rx_fifo(regs); 229 230 /* Flush out any leftover queued requests. */ 231 num_channels = readl(®s->ghwcfg2); 232 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; 233 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; 234 num_channels += 1; 235 236 for (i = 0; i < num_channels; i++) 237 clrsetbits_le32(®s->hc_regs[i].hcchar, 238 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, 239 DWC2_HCCHAR_CHDIS); 240 241 /* Halt all channels to put them into a known state. */ 242 for (i = 0; i < num_channels; i++) { 243 clrsetbits_le32(®s->hc_regs[i].hcchar, 244 DWC2_HCCHAR_EPDIR, 245 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); 246 ret = wait_for_bit(®s->hc_regs[i].hcchar, 247 DWC2_HCCHAR_CHEN, 0); 248 if (ret) 249 printf("%s: Timeout!\n", __func__); 250 } 251 252 /* Turn on the vbus power. */ 253 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { 254 hprt0 = readl(®s->hprt0); 255 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); 256 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); 257 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { 258 hprt0 |= DWC2_HPRT0_PRTPWR; 259 writel(hprt0, ®s->hprt0); 260 } 261 } 262 } 263 264 /* 265 * This function initializes the DWC_otg controller registers and 266 * prepares the core for device mode or host mode operation. 267 * 268 * @param regs Programming view of the DWC_otg controller 269 */ 270 static void dwc_otg_core_init(struct dwc2_core_regs *regs) 271 { 272 uint32_t ahbcfg = 0; 273 uint32_t usbcfg = 0; 274 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; 275 276 /* Common Initialization */ 277 usbcfg = readl(®s->gusbcfg); 278 279 /* Program the ULPI External VBUS bit if needed */ 280 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS 281 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 282 #else 283 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 284 #endif 285 286 /* Set external TS Dline pulsing */ 287 #ifdef CONFIG_DWC2_TS_DLINE 288 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 289 #else 290 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 291 #endif 292 writel(usbcfg, ®s->gusbcfg); 293 294 /* Reset the Controller */ 295 dwc_otg_core_reset(regs); 296 297 /* 298 * This programming sequence needs to happen in FS mode before 299 * any other programming occurs 300 */ 301 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ 302 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 303 /* If FS mode with FS PHY */ 304 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); 305 306 /* Reset after a PHY select */ 307 dwc_otg_core_reset(regs); 308 309 /* 310 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. 311 * Also do this on HNP Dev/Host mode switches (done in dev_init 312 * and host_init). 313 */ 314 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 315 init_fslspclksel(regs); 316 317 #ifdef CONFIG_DWC2_I2C_ENABLE 318 /* Program GUSBCFG.OtgUtmifsSel to I2C */ 319 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); 320 321 /* Program GI2CCTL.I2CEn */ 322 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | 323 DWC2_GI2CCTL_I2CDEVADDR_MASK, 324 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); 325 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); 326 #endif 327 328 #else 329 /* High speed PHY. */ 330 331 /* 332 * HS PHY parameters. These parameters are preserved during 333 * soft reset so only program the first time. Do a soft reset 334 * immediately after setting phyif. 335 */ 336 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); 337 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; 338 339 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ 340 #ifdef CONFIG_DWC2_PHY_ULPI_DDR 341 usbcfg |= DWC2_GUSBCFG_DDRSEL; 342 #else 343 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; 344 #endif 345 } else { /* UTMI+ interface */ 346 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16) 347 usbcfg |= DWC2_GUSBCFG_PHYIF; 348 #endif 349 } 350 351 writel(usbcfg, ®s->gusbcfg); 352 353 /* Reset after setting the PHY parameters */ 354 dwc_otg_core_reset(regs); 355 #endif 356 357 usbcfg = readl(®s->gusbcfg); 358 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); 359 #ifdef CONFIG_DWC2_ULPI_FS_LS 360 uint32_t hwcfg2 = readl(®s->ghwcfg2); 361 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 362 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 363 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 364 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 365 if (hval == 2 && fval == 1) { 366 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; 367 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; 368 } 369 #endif 370 writel(usbcfg, ®s->gusbcfg); 371 372 /* Program the GAHBCFG Register. */ 373 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { 374 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: 375 break; 376 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: 377 while (brst_sz > 1) { 378 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); 379 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; 380 brst_sz >>= 1; 381 } 382 383 #ifdef CONFIG_DWC2_DMA_ENABLE 384 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 385 #endif 386 break; 387 388 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: 389 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; 390 #ifdef CONFIG_DWC2_DMA_ENABLE 391 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 392 #endif 393 break; 394 } 395 396 writel(ahbcfg, ®s->gahbcfg); 397 398 /* Program the GUSBCFG register for HNP/SRP. */ 399 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP); 400 401 #ifdef CONFIG_DWC2_IC_USB_CAP 402 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP); 403 #endif 404 } 405 406 /* 407 * Prepares a host channel for transferring packets to/from a specific 408 * endpoint. The HCCHARn register is set up with the characteristics specified 409 * in _hc. Host channel interrupts that may need to be serviced while this 410 * transfer is in progress are enabled. 411 * 412 * @param regs Programming view of DWC_otg controller 413 * @param hc Information needed to initialize the host channel 414 */ 415 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, 416 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, 417 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) 418 { 419 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; 420 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | 421 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | 422 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | 423 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | 424 (max_packet << DWC2_HCCHAR_MPS_OFFSET); 425 426 if (dev->speed == USB_SPEED_LOW) 427 hcchar |= DWC2_HCCHAR_LSPDDEV; 428 429 /* 430 * Program the HCCHARn register with the endpoint characteristics 431 * for the current transfer. 432 */ 433 writel(hcchar, &hc_regs->hcchar); 434 435 /* Program the HCSPLIT register, default to no SPLIT */ 436 writel(0, &hc_regs->hcsplt); 437 } 438 439 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs, 440 uint8_t hub_devnum, uint8_t hub_port) 441 { 442 uint32_t hcsplt = 0; 443 444 hcsplt = DWC2_HCSPLT_SPLTENA; 445 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET; 446 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET; 447 448 /* Program the HCSPLIT register for SPLITs */ 449 writel(hcsplt, &hc_regs->hcsplt); 450 } 451 452 /* 453 * DWC2 to USB API interface 454 */ 455 /* Direction: In ; Request: Status */ 456 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, 457 struct usb_device *dev, void *buffer, 458 int txlen, struct devrequest *cmd) 459 { 460 uint32_t hprt0 = 0; 461 uint32_t port_status = 0; 462 uint32_t port_change = 0; 463 int len = 0; 464 int stat = 0; 465 466 switch (cmd->requesttype & ~USB_DIR_IN) { 467 case 0: 468 *(uint16_t *)buffer = cpu_to_le16(1); 469 len = 2; 470 break; 471 case USB_RECIP_INTERFACE: 472 case USB_RECIP_ENDPOINT: 473 *(uint16_t *)buffer = cpu_to_le16(0); 474 len = 2; 475 break; 476 case USB_TYPE_CLASS: 477 *(uint32_t *)buffer = cpu_to_le32(0); 478 len = 4; 479 break; 480 case USB_RECIP_OTHER | USB_TYPE_CLASS: 481 hprt0 = readl(®s->hprt0); 482 if (hprt0 & DWC2_HPRT0_PRTCONNSTS) 483 port_status |= USB_PORT_STAT_CONNECTION; 484 if (hprt0 & DWC2_HPRT0_PRTENA) 485 port_status |= USB_PORT_STAT_ENABLE; 486 if (hprt0 & DWC2_HPRT0_PRTSUSP) 487 port_status |= USB_PORT_STAT_SUSPEND; 488 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) 489 port_status |= USB_PORT_STAT_OVERCURRENT; 490 if (hprt0 & DWC2_HPRT0_PRTRST) 491 port_status |= USB_PORT_STAT_RESET; 492 if (hprt0 & DWC2_HPRT0_PRTPWR) 493 port_status |= USB_PORT_STAT_POWER; 494 495 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) 496 port_status |= USB_PORT_STAT_LOW_SPEED; 497 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 498 DWC2_HPRT0_PRTSPD_HIGH) 499 port_status |= USB_PORT_STAT_HIGH_SPEED; 500 501 if (hprt0 & DWC2_HPRT0_PRTENCHNG) 502 port_change |= USB_PORT_STAT_C_ENABLE; 503 if (hprt0 & DWC2_HPRT0_PRTCONNDET) 504 port_change |= USB_PORT_STAT_C_CONNECTION; 505 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) 506 port_change |= USB_PORT_STAT_C_OVERCURRENT; 507 508 *(uint32_t *)buffer = cpu_to_le32(port_status | 509 (port_change << 16)); 510 len = 4; 511 break; 512 default: 513 puts("unsupported root hub command\n"); 514 stat = USB_ST_STALLED; 515 } 516 517 dev->act_len = min(len, txlen); 518 dev->status = stat; 519 520 return stat; 521 } 522 523 /* Direction: In ; Request: Descriptor */ 524 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, 525 void *buffer, int txlen, 526 struct devrequest *cmd) 527 { 528 unsigned char data[32]; 529 uint32_t dsc; 530 int len = 0; 531 int stat = 0; 532 uint16_t wValue = cpu_to_le16(cmd->value); 533 uint16_t wLength = cpu_to_le16(cmd->length); 534 535 switch (cmd->requesttype & ~USB_DIR_IN) { 536 case 0: 537 switch (wValue & 0xff00) { 538 case 0x0100: /* device descriptor */ 539 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); 540 memcpy(buffer, root_hub_dev_des, len); 541 break; 542 case 0x0200: /* configuration descriptor */ 543 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); 544 memcpy(buffer, root_hub_config_des, len); 545 break; 546 case 0x0300: /* string descriptors */ 547 switch (wValue & 0xff) { 548 case 0x00: 549 len = min3(txlen, (int)sizeof(root_hub_str_index0), 550 (int)wLength); 551 memcpy(buffer, root_hub_str_index0, len); 552 break; 553 case 0x01: 554 len = min3(txlen, (int)sizeof(root_hub_str_index1), 555 (int)wLength); 556 memcpy(buffer, root_hub_str_index1, len); 557 break; 558 } 559 break; 560 default: 561 stat = USB_ST_STALLED; 562 } 563 break; 564 565 case USB_TYPE_CLASS: 566 /* Root port config, set 1 port and nothing else. */ 567 dsc = 0x00000001; 568 569 data[0] = 9; /* min length; */ 570 data[1] = 0x29; 571 data[2] = dsc & RH_A_NDP; 572 data[3] = 0; 573 if (dsc & RH_A_PSM) 574 data[3] |= 0x1; 575 if (dsc & RH_A_NOCP) 576 data[3] |= 0x10; 577 else if (dsc & RH_A_OCPM) 578 data[3] |= 0x8; 579 580 /* corresponds to data[4-7] */ 581 data[5] = (dsc & RH_A_POTPGT) >> 24; 582 data[7] = dsc & RH_B_DR; 583 if (data[2] < 7) { 584 data[8] = 0xff; 585 } else { 586 data[0] += 2; 587 data[8] = (dsc & RH_B_DR) >> 8; 588 data[9] = 0xff; 589 data[10] = data[9]; 590 } 591 592 len = min3(txlen, (int)data[0], (int)wLength); 593 memcpy(buffer, data, len); 594 break; 595 default: 596 puts("unsupported root hub command\n"); 597 stat = USB_ST_STALLED; 598 } 599 600 dev->act_len = min(len, txlen); 601 dev->status = stat; 602 603 return stat; 604 } 605 606 /* Direction: In ; Request: Configuration */ 607 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, 608 void *buffer, int txlen, 609 struct devrequest *cmd) 610 { 611 int len = 0; 612 int stat = 0; 613 614 switch (cmd->requesttype & ~USB_DIR_IN) { 615 case 0: 616 *(uint8_t *)buffer = 0x01; 617 len = 1; 618 break; 619 default: 620 puts("unsupported root hub command\n"); 621 stat = USB_ST_STALLED; 622 } 623 624 dev->act_len = min(len, txlen); 625 dev->status = stat; 626 627 return stat; 628 } 629 630 /* Direction: In */ 631 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, 632 struct usb_device *dev, void *buffer, 633 int txlen, struct devrequest *cmd) 634 { 635 switch (cmd->request) { 636 case USB_REQ_GET_STATUS: 637 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, 638 txlen, cmd); 639 case USB_REQ_GET_DESCRIPTOR: 640 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, 641 txlen, cmd); 642 case USB_REQ_GET_CONFIGURATION: 643 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, 644 txlen, cmd); 645 default: 646 puts("unsupported root hub command\n"); 647 return USB_ST_STALLED; 648 } 649 } 650 651 /* Direction: Out */ 652 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, 653 struct usb_device *dev, 654 void *buffer, int txlen, 655 struct devrequest *cmd) 656 { 657 struct dwc2_core_regs *regs = priv->regs; 658 int len = 0; 659 int stat = 0; 660 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); 661 uint16_t wValue = cpu_to_le16(cmd->value); 662 663 switch (bmrtype_breq & ~USB_DIR_IN) { 664 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: 665 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: 666 break; 667 668 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 669 switch (wValue) { 670 case USB_PORT_FEAT_C_CONNECTION: 671 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); 672 break; 673 } 674 break; 675 676 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 677 switch (wValue) { 678 case USB_PORT_FEAT_SUSPEND: 679 break; 680 681 case USB_PORT_FEAT_RESET: 682 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 683 DWC2_HPRT0_PRTCONNDET | 684 DWC2_HPRT0_PRTENCHNG | 685 DWC2_HPRT0_PRTOVRCURRCHNG, 686 DWC2_HPRT0_PRTRST); 687 mdelay(50); 688 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); 689 break; 690 691 case USB_PORT_FEAT_POWER: 692 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 693 DWC2_HPRT0_PRTCONNDET | 694 DWC2_HPRT0_PRTENCHNG | 695 DWC2_HPRT0_PRTOVRCURRCHNG, 696 DWC2_HPRT0_PRTRST); 697 break; 698 699 case USB_PORT_FEAT_ENABLE: 700 break; 701 } 702 break; 703 case (USB_REQ_SET_ADDRESS << 8): 704 priv->root_hub_devnum = wValue; 705 break; 706 case (USB_REQ_SET_CONFIGURATION << 8): 707 break; 708 default: 709 puts("unsupported root hub command\n"); 710 stat = USB_ST_STALLED; 711 } 712 713 len = min(len, txlen); 714 715 dev->act_len = len; 716 dev->status = stat; 717 718 return stat; 719 } 720 721 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, 722 unsigned long pipe, void *buffer, int txlen, 723 struct devrequest *cmd) 724 { 725 int stat = 0; 726 727 if (usb_pipeint(pipe)) { 728 puts("Root-Hub submit IRQ: NOT implemented\n"); 729 return 0; 730 } 731 732 if (cmd->requesttype & USB_DIR_IN) 733 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); 734 else 735 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); 736 737 mdelay(1); 738 739 return stat; 740 } 741 742 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, int *toggle) 743 { 744 int ret; 745 uint32_t hcint, hctsiz; 746 747 ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true); 748 if (ret) 749 return ret; 750 751 hcint = readl(&hc_regs->hcint); 752 hctsiz = readl(&hc_regs->hctsiz); 753 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> 754 DWC2_HCTSIZ_XFERSIZE_OFFSET; 755 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; 756 757 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, 758 *toggle); 759 760 if (hcint & DWC2_HCINT_XFERCOMP) 761 return 0; 762 763 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) 764 return -EAGAIN; 765 766 debug("%s: Error (HCINT=%08x)\n", __func__, hcint); 767 return -EINVAL; 768 } 769 770 static int dwc2_eptype[] = { 771 DWC2_HCCHAR_EPTYPE_ISOC, 772 DWC2_HCCHAR_EPTYPE_INTR, 773 DWC2_HCCHAR_EPTYPE_CONTROL, 774 DWC2_HCCHAR_EPTYPE_BULK, 775 }; 776 777 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, 778 int *pid, int in, void *buffer, int num_packets, 779 int xfer_len, int *actual_len, int odd_frame) 780 { 781 int ret = 0; 782 uint32_t sub; 783 784 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, 785 *pid, xfer_len, num_packets); 786 787 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | 788 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | 789 (*pid << DWC2_HCTSIZ_PID_OFFSET), 790 &hc_regs->hctsiz); 791 792 if (!in && xfer_len) { 793 memcpy(aligned_buffer, buffer, xfer_len); 794 795 flush_dcache_range((unsigned long)aligned_buffer, 796 (unsigned long)aligned_buffer + 797 roundup(xfer_len, ARCH_DMA_MINALIGN)); 798 } 799 800 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); 801 802 /* Clear old interrupt conditions for this host channel. */ 803 writel(0x3fff, &hc_regs->hcint); 804 805 /* Set host channel enable after all other setup is complete. */ 806 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | 807 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS | 808 DWC2_HCCHAR_ODDFRM, 809 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | 810 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) | 811 DWC2_HCCHAR_CHEN); 812 813 ret = wait_for_chhltd(hc_regs, &sub, pid); 814 if (ret < 0) 815 return ret; 816 817 if (in) { 818 xfer_len -= sub; 819 820 invalidate_dcache_range((unsigned long)aligned_buffer, 821 (unsigned long)aligned_buffer + 822 roundup(xfer_len, ARCH_DMA_MINALIGN)); 823 824 memcpy(buffer, aligned_buffer, xfer_len); 825 } 826 *actual_len = xfer_len; 827 828 return ret; 829 } 830 831 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, 832 unsigned long pipe, int *pid, int in, void *buffer, int len) 833 { 834 struct dwc2_core_regs *regs = priv->regs; 835 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 836 struct dwc2_host_regs *host_regs = ®s->host_regs; 837 int devnum = usb_pipedevice(pipe); 838 int ep = usb_pipeendpoint(pipe); 839 int max = usb_maxpacket(dev, pipe); 840 int eptype = dwc2_eptype[usb_pipetype(pipe)]; 841 int done = 0; 842 int ret = 0; 843 int do_split = 0; 844 int complete_split = 0; 845 uint32_t xfer_len; 846 uint32_t num_packets; 847 int stop_transfer = 0; 848 uint32_t max_xfer_len; 849 int ssplit_frame_num = 0; 850 851 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, 852 in, len); 853 854 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; 855 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) 856 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; 857 if (max_xfer_len > DWC2_DATA_BUF_SIZE) 858 max_xfer_len = DWC2_DATA_BUF_SIZE; 859 860 /* Make sure that max_xfer_len is a multiple of max packet size. */ 861 num_packets = max_xfer_len / max; 862 max_xfer_len = num_packets * max; 863 864 /* Initialize channel */ 865 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, 866 eptype, max); 867 868 /* Check if the target is a FS/LS device behind a HS hub */ 869 if (dev->speed != USB_SPEED_HIGH) { 870 uint8_t hub_addr; 871 uint8_t hub_port; 872 uint32_t hprt0 = readl(®s->hprt0); 873 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 874 DWC2_HPRT0_PRTSPD_HIGH) { 875 usb_find_usb2_hub_address_port(dev, &hub_addr, 876 &hub_port); 877 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port); 878 879 do_split = 1; 880 num_packets = 1; 881 max_xfer_len = max; 882 } 883 } 884 885 do { 886 int actual_len = 0; 887 uint32_t hcint; 888 int odd_frame = 0; 889 xfer_len = len - done; 890 891 if (xfer_len > max_xfer_len) 892 xfer_len = max_xfer_len; 893 else if (xfer_len > max) 894 num_packets = (xfer_len + max - 1) / max; 895 else 896 num_packets = 1; 897 898 if (complete_split) 899 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 900 else if (do_split) 901 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 902 903 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) { 904 int uframe_num = readl(&host_regs->hfnum); 905 if (!(uframe_num & 0x1)) 906 odd_frame = 1; 907 } 908 909 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, 910 in, (char *)buffer + done, num_packets, 911 xfer_len, &actual_len, odd_frame); 912 913 hcint = readl(&hc_regs->hcint); 914 if (complete_split) { 915 stop_transfer = 0; 916 if (hcint & DWC2_HCINT_NYET) { 917 ret = 0; 918 int frame_num = DWC2_HFNUM_MAX_FRNUM & 919 readl(&host_regs->hfnum); 920 if (((frame_num - ssplit_frame_num) & 921 DWC2_HFNUM_MAX_FRNUM) > 4) 922 ret = -EAGAIN; 923 } else 924 complete_split = 0; 925 } else if (do_split) { 926 if (hcint & DWC2_HCINT_ACK) { 927 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM & 928 readl(&host_regs->hfnum); 929 ret = 0; 930 complete_split = 1; 931 } 932 } 933 934 if (ret) 935 break; 936 937 if (actual_len < xfer_len) 938 stop_transfer = 1; 939 940 done += actual_len; 941 942 /* Transactions are done when when either all data is transferred or 943 * there is a short transfer. In case of a SPLIT make sure the CSPLIT 944 * is executed. 945 */ 946 } while (((done < len) && !stop_transfer) || complete_split); 947 948 writel(0, &hc_regs->hcintmsk); 949 writel(0xFFFFFFFF, &hc_regs->hcint); 950 951 dev->status = 0; 952 dev->act_len = done; 953 954 return ret; 955 } 956 957 /* U-Boot USB transmission interface */ 958 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, 959 unsigned long pipe, void *buffer, int len) 960 { 961 int devnum = usb_pipedevice(pipe); 962 int ep = usb_pipeendpoint(pipe); 963 964 if (devnum == priv->root_hub_devnum) { 965 dev->status = 0; 966 return -EINVAL; 967 } 968 969 return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep], 970 usb_pipein(pipe), buffer, len); 971 } 972 973 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, 974 unsigned long pipe, void *buffer, int len, 975 struct devrequest *setup) 976 { 977 int devnum = usb_pipedevice(pipe); 978 int pid, ret, act_len; 979 /* For CONTROL endpoint pid should start with DATA1 */ 980 int status_direction; 981 982 if (devnum == priv->root_hub_devnum) { 983 dev->status = 0; 984 dev->speed = USB_SPEED_HIGH; 985 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, 986 setup); 987 } 988 989 /* SETUP stage */ 990 pid = DWC2_HC_PID_SETUP; 991 do { 992 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8); 993 } while (ret == -EAGAIN); 994 if (ret) 995 return ret; 996 997 /* DATA stage */ 998 act_len = 0; 999 if (buffer) { 1000 pid = DWC2_HC_PID_DATA1; 1001 do { 1002 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), 1003 buffer, len); 1004 act_len += dev->act_len; 1005 buffer += dev->act_len; 1006 len -= dev->act_len; 1007 } while (ret == -EAGAIN); 1008 if (ret) 1009 return ret; 1010 status_direction = usb_pipeout(pipe); 1011 } else { 1012 /* No-data CONTROL always ends with an IN transaction */ 1013 status_direction = 1; 1014 } 1015 1016 /* STATUS stage */ 1017 pid = DWC2_HC_PID_DATA1; 1018 do { 1019 ret = chunk_msg(priv, dev, pipe, &pid, status_direction, 1020 priv->status_buffer, 0); 1021 } while (ret == -EAGAIN); 1022 if (ret) 1023 return ret; 1024 1025 dev->act_len = act_len; 1026 1027 return 0; 1028 } 1029 1030 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, 1031 unsigned long pipe, void *buffer, int len, int interval) 1032 { 1033 unsigned long timeout; 1034 int ret; 1035 1036 /* FIXME: what is interval? */ 1037 1038 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1039 for (;;) { 1040 if (get_timer(0) > timeout) { 1041 printf("Timeout poll on interrupt endpoint\n"); 1042 return -ETIMEDOUT; 1043 } 1044 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); 1045 if (ret != -EAGAIN) 1046 return ret; 1047 } 1048 } 1049 1050 static int dwc2_init_common(struct dwc2_priv *priv) 1051 { 1052 struct dwc2_core_regs *regs = priv->regs; 1053 uint32_t snpsid; 1054 int i, j; 1055 1056 snpsid = readl(®s->gsnpsid); 1057 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff); 1058 1059 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && 1060 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { 1061 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid); 1062 return -ENODEV; 1063 } 1064 1065 dwc_otg_core_init(regs); 1066 dwc_otg_core_host_init(regs); 1067 1068 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1069 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1070 DWC2_HPRT0_PRTOVRCURRCHNG, 1071 DWC2_HPRT0_PRTRST); 1072 mdelay(50); 1073 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | 1074 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | 1075 DWC2_HPRT0_PRTRST); 1076 1077 for (i = 0; i < MAX_DEVICE; i++) { 1078 for (j = 0; j < MAX_ENDPOINT; j++) 1079 priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1080 } 1081 1082 return 0; 1083 } 1084 1085 static void dwc2_uninit_common(struct dwc2_core_regs *regs) 1086 { 1087 /* Put everything in reset. */ 1088 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1089 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1090 DWC2_HPRT0_PRTOVRCURRCHNG, 1091 DWC2_HPRT0_PRTRST); 1092 } 1093 1094 #ifndef CONFIG_DM_USB 1095 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1096 int len, struct devrequest *setup) 1097 { 1098 return _submit_control_msg(&local, dev, pipe, buffer, len, setup); 1099 } 1100 1101 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1102 int len) 1103 { 1104 return _submit_bulk_msg(&local, dev, pipe, buffer, len); 1105 } 1106 1107 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1108 int len, int interval) 1109 { 1110 return _submit_int_msg(&local, dev, pipe, buffer, len, interval); 1111 } 1112 1113 /* U-Boot USB control interface */ 1114 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1115 { 1116 struct dwc2_priv *priv = &local; 1117 1118 memset(priv, '\0', sizeof(*priv)); 1119 priv->root_hub_devnum = 0; 1120 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; 1121 priv->aligned_buffer = aligned_buffer_addr; 1122 priv->status_buffer = status_buffer_addr; 1123 1124 /* board-dependant init */ 1125 if (board_usb_init(index, USB_INIT_HOST)) 1126 return -1; 1127 1128 return dwc2_init_common(priv); 1129 } 1130 1131 int usb_lowlevel_stop(int index) 1132 { 1133 dwc2_uninit_common(local.regs); 1134 1135 return 0; 1136 } 1137 #endif 1138 1139 #ifdef CONFIG_DM_USB 1140 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1141 unsigned long pipe, void *buffer, int length, 1142 struct devrequest *setup) 1143 { 1144 struct dwc2_priv *priv = dev_get_priv(dev); 1145 1146 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1147 dev->name, udev, udev->dev->name, udev->portnr); 1148 1149 return _submit_control_msg(priv, udev, pipe, buffer, length, setup); 1150 } 1151 1152 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1153 unsigned long pipe, void *buffer, int length) 1154 { 1155 struct dwc2_priv *priv = dev_get_priv(dev); 1156 1157 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1158 1159 return _submit_bulk_msg(priv, udev, pipe, buffer, length); 1160 } 1161 1162 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1163 unsigned long pipe, void *buffer, int length, 1164 int interval) 1165 { 1166 struct dwc2_priv *priv = dev_get_priv(dev); 1167 1168 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1169 1170 return _submit_int_msg(priv, udev, pipe, buffer, length, interval); 1171 } 1172 1173 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) 1174 { 1175 struct dwc2_priv *priv = dev_get_priv(dev); 1176 fdt_addr_t addr; 1177 1178 addr = dev_get_addr(dev); 1179 if (addr == FDT_ADDR_T_NONE) 1180 return -EINVAL; 1181 priv->regs = (struct dwc2_core_regs *)addr; 1182 1183 return 0; 1184 } 1185 1186 static int dwc2_usb_probe(struct udevice *dev) 1187 { 1188 struct dwc2_priv *priv = dev_get_priv(dev); 1189 1190 return dwc2_init_common(priv); 1191 } 1192 1193 static int dwc2_usb_remove(struct udevice *dev) 1194 { 1195 struct dwc2_priv *priv = dev_get_priv(dev); 1196 1197 dwc2_uninit_common(priv->regs); 1198 1199 return 0; 1200 } 1201 1202 struct dm_usb_ops dwc2_usb_ops = { 1203 .control = dwc2_submit_control_msg, 1204 .bulk = dwc2_submit_bulk_msg, 1205 .interrupt = dwc2_submit_int_msg, 1206 }; 1207 1208 static const struct udevice_id dwc2_usb_ids[] = { 1209 { .compatible = "brcm,bcm2835-usb" }, 1210 { .compatible = "snps,dwc2" }, 1211 { } 1212 }; 1213 1214 U_BOOT_DRIVER(usb_dwc2) = { 1215 .name = "dwc2_usb", 1216 .id = UCLASS_USB, 1217 .of_match = dwc2_usb_ids, 1218 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, 1219 .probe = dwc2_usb_probe, 1220 .remove = dwc2_usb_remove, 1221 .ops = &dwc2_usb_ops, 1222 .priv_auto_alloc_size = sizeof(struct dwc2_priv), 1223 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1224 }; 1225 #endif 1226