1 /* 2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <generic-phy.h> 13 #include <malloc.h> 14 #include <memalign.h> 15 #include <phys2bus.h> 16 #include <usb.h> 17 #include <usbroothubdes.h> 18 #include <wait_bit.h> 19 #include <asm/io.h> 20 #include <power/regulator.h> 21 #include <reset.h> 22 23 #include "dwc2.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /* Use only HC channel 0. */ 28 #define DWC2_HC_CHANNEL 0 29 30 #define DWC2_STATUS_BUF_SIZE 64 31 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024) 32 33 #define MAX_DEVICE 16 34 #define MAX_ENDPOINT 16 35 36 struct dwc2_priv { 37 #if CONFIG_IS_ENABLED(DM_USB) 38 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 39 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 40 #ifdef CONFIG_DM_REGULATOR 41 struct udevice *vbus_supply; 42 #endif 43 struct phy phy; 44 struct clk_bulk clks; 45 #else 46 uint8_t *aligned_buffer; 47 uint8_t *status_buffer; 48 #endif 49 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 50 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 51 struct dwc2_core_regs *regs; 52 int root_hub_devnum; 53 bool ext_vbus; 54 /* 55 * The hnp/srp capability must be disabled if the platform 56 * does't support hnp/srp. Otherwise the force mode can't work. 57 */ 58 bool hnp_srp_disable; 59 bool oc_disable; 60 61 struct reset_ctl_bulk resets; 62 }; 63 64 #if !CONFIG_IS_ENABLED(DM_USB) 65 /* We need cacheline-aligned buffers for DMA transfers and dcache support */ 66 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 67 ARCH_DMA_MINALIGN); 68 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 69 ARCH_DMA_MINALIGN); 70 71 static struct dwc2_priv local; 72 #endif 73 74 /* 75 * DWC2 IP interface 76 */ 77 78 /* 79 * Initializes the FSLSPClkSel field of the HCFG register 80 * depending on the PHY type. 81 */ 82 static void init_fslspclksel(struct dwc2_core_regs *regs) 83 { 84 uint32_t phyclk; 85 86 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 87 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 88 #else 89 /* High speed PHY running at full speed or high speed */ 90 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; 91 #endif 92 93 #ifdef CONFIG_DWC2_ULPI_FS_LS 94 uint32_t hwcfg2 = readl(®s->ghwcfg2); 95 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 96 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 97 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 98 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 99 100 if (hval == 2 && fval == 1) 101 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 102 #endif 103 104 clrsetbits_le32(®s->host_regs.hcfg, 105 DWC2_HCFG_FSLSPCLKSEL_MASK, 106 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); 107 } 108 109 /* 110 * Flush a Tx FIFO. 111 * 112 * @param regs Programming view of DWC_otg controller. 113 * @param num Tx FIFO to flush. 114 */ 115 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) 116 { 117 int ret; 118 119 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), 120 ®s->grstctl); 121 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 122 false, 1000, false); 123 if (ret) 124 dev_info(dev, "%s: Timeout!\n", __func__); 125 126 /* Wait for 3 PHY Clocks */ 127 udelay(1); 128 } 129 130 /* 131 * Flush Rx FIFO. 132 * 133 * @param regs Programming view of DWC_otg controller. 134 */ 135 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) 136 { 137 int ret; 138 139 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); 140 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 141 false, 1000, false); 142 if (ret) 143 dev_info(dev, "%s: Timeout!\n", __func__); 144 145 /* Wait for 3 PHY Clocks */ 146 udelay(1); 147 } 148 149 /* 150 * Do core a soft reset of the core. Be careful with this because it 151 * resets all the internal state machines of the core. 152 */ 153 static void dwc_otg_core_reset(struct dwc2_core_regs *regs) 154 { 155 int ret; 156 157 /* Wait for AHB master IDLE state. */ 158 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 159 true, 1000, false); 160 if (ret) 161 dev_info(dev, "%s: Timeout!\n", __func__); 162 163 /* Core Soft Reset */ 164 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); 165 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 166 false, 1000, false); 167 if (ret) 168 dev_info(dev, "%s: Timeout!\n", __func__); 169 170 /* 171 * Wait for core to come out of reset. 172 * NOTE: This long sleep is _very_ important, otherwise the core will 173 * not stay in host mode after a connector ID change! 174 */ 175 mdelay(100); 176 } 177 178 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR) 179 static int dwc_vbus_supply_init(struct udevice *dev) 180 { 181 struct dwc2_priv *priv = dev_get_priv(dev); 182 int ret; 183 184 ret = device_get_supply_regulator(dev, "vbus-supply", 185 &priv->vbus_supply); 186 if (ret) { 187 debug("%s: No vbus supply\n", dev->name); 188 return 0; 189 } 190 191 ret = regulator_set_enable(priv->vbus_supply, true); 192 if (ret) { 193 dev_err(dev, "Error enabling vbus supply\n"); 194 return ret; 195 } 196 197 return 0; 198 } 199 200 static int dwc_vbus_supply_exit(struct udevice *dev) 201 { 202 struct dwc2_priv *priv = dev_get_priv(dev); 203 int ret; 204 205 if (priv->vbus_supply) { 206 ret = regulator_set_enable(priv->vbus_supply, false); 207 if (ret) { 208 dev_err(dev, "Error disabling vbus supply\n"); 209 return ret; 210 } 211 } 212 213 return 0; 214 } 215 #else 216 static int dwc_vbus_supply_init(struct udevice *dev) 217 { 218 return 0; 219 } 220 221 #if CONFIG_IS_ENABLED(DM_USB) 222 static int dwc_vbus_supply_exit(struct udevice *dev) 223 { 224 return 0; 225 } 226 #endif 227 #endif 228 229 /* 230 * This function initializes the DWC_otg controller registers for 231 * host mode. 232 * 233 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the 234 * request queues. Host channels are reset to ensure that they are ready for 235 * performing transfers. 236 * 237 * @param dev USB Device (NULL if driver model is not being used) 238 * @param regs Programming view of DWC_otg controller 239 * 240 */ 241 static void dwc_otg_core_host_init(struct udevice *dev, 242 struct dwc2_core_regs *regs) 243 { 244 uint32_t nptxfifosize = 0; 245 uint32_t ptxfifosize = 0; 246 uint32_t hprt0 = 0; 247 int i, ret, num_channels; 248 249 /* Restart the Phy Clock */ 250 writel(0, ®s->pcgcctl); 251 252 /* Initialize Host Configuration Register */ 253 init_fslspclksel(regs); 254 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL 255 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); 256 #endif 257 258 /* Configure data FIFO sizes */ 259 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO 260 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { 261 /* Rx FIFO */ 262 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); 263 264 /* Non-periodic Tx FIFO */ 265 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << 266 DWC2_FIFOSIZE_DEPTH_OFFSET; 267 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << 268 DWC2_FIFOSIZE_STARTADDR_OFFSET; 269 writel(nptxfifosize, ®s->gnptxfsiz); 270 271 /* Periodic Tx FIFO */ 272 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << 273 DWC2_FIFOSIZE_DEPTH_OFFSET; 274 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + 275 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << 276 DWC2_FIFOSIZE_STARTADDR_OFFSET; 277 writel(ptxfifosize, ®s->hptxfsiz); 278 } 279 #endif 280 281 /* Clear Host Set HNP Enable in the OTG Control Register */ 282 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); 283 284 /* Make sure the FIFOs are flushed. */ 285 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ 286 dwc_otg_flush_rx_fifo(regs); 287 288 /* Flush out any leftover queued requests. */ 289 num_channels = readl(®s->ghwcfg2); 290 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; 291 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; 292 num_channels += 1; 293 294 for (i = 0; i < num_channels; i++) 295 clrsetbits_le32(®s->hc_regs[i].hcchar, 296 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, 297 DWC2_HCCHAR_CHDIS); 298 299 /* Halt all channels to put them into a known state. */ 300 for (i = 0; i < num_channels; i++) { 301 clrsetbits_le32(®s->hc_regs[i].hcchar, 302 DWC2_HCCHAR_EPDIR, 303 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); 304 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar, 305 DWC2_HCCHAR_CHEN, false, 1000, false); 306 if (ret) 307 dev_info("%s: Timeout!\n", __func__); 308 } 309 310 /* Turn on the vbus power. */ 311 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { 312 hprt0 = readl(®s->hprt0); 313 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); 314 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); 315 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { 316 hprt0 |= DWC2_HPRT0_PRTPWR; 317 writel(hprt0, ®s->hprt0); 318 } 319 } 320 321 if (dev) 322 dwc_vbus_supply_init(dev); 323 } 324 325 /* 326 * This function initializes the DWC_otg controller registers and 327 * prepares the core for device mode or host mode operation. 328 * 329 * @param regs Programming view of the DWC_otg controller 330 */ 331 static void dwc_otg_core_init(struct dwc2_priv *priv) 332 { 333 struct dwc2_core_regs *regs = priv->regs; 334 uint32_t ahbcfg = 0; 335 uint32_t usbcfg = 0; 336 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; 337 338 /* Common Initialization */ 339 usbcfg = readl(®s->gusbcfg); 340 341 /* Program the ULPI External VBUS bit if needed */ 342 if (priv->ext_vbus) { 343 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 344 if (!priv->oc_disable) { 345 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR | 346 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH; 347 } 348 } else { 349 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 350 } 351 352 /* Set external TS Dline pulsing */ 353 #ifdef CONFIG_DWC2_TS_DLINE 354 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 355 #else 356 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 357 #endif 358 writel(usbcfg, ®s->gusbcfg); 359 360 /* Reset the Controller */ 361 dwc_otg_core_reset(regs); 362 363 /* 364 * This programming sequence needs to happen in FS mode before 365 * any other programming occurs 366 */ 367 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ 368 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 369 /* If FS mode with FS PHY */ 370 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); 371 372 /* Reset after a PHY select */ 373 dwc_otg_core_reset(regs); 374 375 /* 376 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. 377 * Also do this on HNP Dev/Host mode switches (done in dev_init 378 * and host_init). 379 */ 380 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 381 init_fslspclksel(regs); 382 383 #ifdef CONFIG_DWC2_I2C_ENABLE 384 /* Program GUSBCFG.OtgUtmifsSel to I2C */ 385 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); 386 387 /* Program GI2CCTL.I2CEn */ 388 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | 389 DWC2_GI2CCTL_I2CDEVADDR_MASK, 390 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); 391 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); 392 #endif 393 394 #else 395 /* High speed PHY. */ 396 397 /* 398 * HS PHY parameters. These parameters are preserved during 399 * soft reset so only program the first time. Do a soft reset 400 * immediately after setting phyif. 401 */ 402 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); 403 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; 404 405 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ 406 #ifdef CONFIG_DWC2_PHY_ULPI_DDR 407 usbcfg |= DWC2_GUSBCFG_DDRSEL; 408 #else 409 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; 410 #endif 411 } else { /* UTMI+ interface */ 412 #if (CONFIG_DWC2_UTMI_WIDTH == 16) 413 usbcfg |= DWC2_GUSBCFG_PHYIF; 414 #endif 415 } 416 417 writel(usbcfg, ®s->gusbcfg); 418 419 /* Reset after setting the PHY parameters */ 420 dwc_otg_core_reset(regs); 421 #endif 422 423 usbcfg = readl(®s->gusbcfg); 424 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); 425 #ifdef CONFIG_DWC2_ULPI_FS_LS 426 uint32_t hwcfg2 = readl(®s->ghwcfg2); 427 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 428 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 429 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 430 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 431 if (hval == 2 && fval == 1) { 432 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; 433 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; 434 } 435 #endif 436 if (priv->hnp_srp_disable) 437 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE; 438 439 writel(usbcfg, ®s->gusbcfg); 440 441 /* 442 * Refer to DWC2 Databook 3.10a Table 5-10 443 * After setting the force bit, the application must wait at least 444 * 25 ms before the change to take effect. 445 */ 446 if (usbcfg & DWC2_GUSBCFG_FORCEHOSTMODE) 447 mdelay(30); 448 449 /* Program the GAHBCFG Register. */ 450 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { 451 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: 452 break; 453 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: 454 while (brst_sz > 1) { 455 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); 456 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; 457 brst_sz >>= 1; 458 } 459 460 #ifdef CONFIG_DWC2_DMA_ENABLE 461 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 462 #endif 463 break; 464 465 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: 466 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; 467 #ifdef CONFIG_DWC2_DMA_ENABLE 468 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 469 #endif 470 break; 471 } 472 473 writel(ahbcfg, ®s->gahbcfg); 474 475 /* Program the capabilities in GUSBCFG Register */ 476 usbcfg = 0; 477 478 if (!priv->hnp_srp_disable) 479 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; 480 #ifdef CONFIG_DWC2_IC_USB_CAP 481 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; 482 #endif 483 484 setbits_le32(®s->gusbcfg, usbcfg); 485 } 486 487 /* 488 * Prepares a host channel for transferring packets to/from a specific 489 * endpoint. The HCCHARn register is set up with the characteristics specified 490 * in _hc. Host channel interrupts that may need to be serviced while this 491 * transfer is in progress are enabled. 492 * 493 * @param regs Programming view of DWC_otg controller 494 * @param hc Information needed to initialize the host channel 495 */ 496 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, 497 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, 498 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) 499 { 500 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; 501 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | 502 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | 503 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | 504 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | 505 (max_packet << DWC2_HCCHAR_MPS_OFFSET); 506 507 if (dev->speed == USB_SPEED_LOW) 508 hcchar |= DWC2_HCCHAR_LSPDDEV; 509 510 /* 511 * Program the HCCHARn register with the endpoint characteristics 512 * for the current transfer. 513 */ 514 writel(hcchar, &hc_regs->hcchar); 515 516 /* Program the HCSPLIT register, default to no SPLIT */ 517 writel(0, &hc_regs->hcsplt); 518 } 519 520 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs, 521 uint8_t hub_devnum, uint8_t hub_port) 522 { 523 uint32_t hcsplt = 0; 524 525 hcsplt = DWC2_HCSPLT_SPLTENA; 526 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET; 527 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET; 528 529 /* Program the HCSPLIT register for SPLITs */ 530 writel(hcsplt, &hc_regs->hcsplt); 531 } 532 533 /* 534 * DWC2 to USB API interface 535 */ 536 /* Direction: In ; Request: Status */ 537 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, 538 struct usb_device *dev, void *buffer, 539 int txlen, struct devrequest *cmd) 540 { 541 uint32_t hprt0 = 0; 542 uint32_t port_status = 0; 543 uint32_t port_change = 0; 544 int len = 0; 545 int stat = 0; 546 547 switch (cmd->requesttype & ~USB_DIR_IN) { 548 case 0: 549 *(uint16_t *)buffer = cpu_to_le16(1); 550 len = 2; 551 break; 552 case USB_RECIP_INTERFACE: 553 case USB_RECIP_ENDPOINT: 554 *(uint16_t *)buffer = cpu_to_le16(0); 555 len = 2; 556 break; 557 case USB_TYPE_CLASS: 558 *(uint32_t *)buffer = cpu_to_le32(0); 559 len = 4; 560 break; 561 case USB_RECIP_OTHER | USB_TYPE_CLASS: 562 hprt0 = readl(®s->hprt0); 563 if (hprt0 & DWC2_HPRT0_PRTCONNSTS) 564 port_status |= USB_PORT_STAT_CONNECTION; 565 if (hprt0 & DWC2_HPRT0_PRTENA) 566 port_status |= USB_PORT_STAT_ENABLE; 567 if (hprt0 & DWC2_HPRT0_PRTSUSP) 568 port_status |= USB_PORT_STAT_SUSPEND; 569 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) 570 port_status |= USB_PORT_STAT_OVERCURRENT; 571 if (hprt0 & DWC2_HPRT0_PRTRST) 572 port_status |= USB_PORT_STAT_RESET; 573 if (hprt0 & DWC2_HPRT0_PRTPWR) 574 port_status |= USB_PORT_STAT_POWER; 575 576 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) 577 port_status |= USB_PORT_STAT_LOW_SPEED; 578 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 579 DWC2_HPRT0_PRTSPD_HIGH) 580 port_status |= USB_PORT_STAT_HIGH_SPEED; 581 582 if (hprt0 & DWC2_HPRT0_PRTENCHNG) 583 port_change |= USB_PORT_STAT_C_ENABLE; 584 if (hprt0 & DWC2_HPRT0_PRTCONNDET) 585 port_change |= USB_PORT_STAT_C_CONNECTION; 586 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) 587 port_change |= USB_PORT_STAT_C_OVERCURRENT; 588 589 *(uint32_t *)buffer = cpu_to_le32(port_status | 590 (port_change << 16)); 591 len = 4; 592 break; 593 default: 594 puts("unsupported root hub command\n"); 595 stat = USB_ST_STALLED; 596 } 597 598 dev->act_len = min(len, txlen); 599 dev->status = stat; 600 601 return stat; 602 } 603 604 /* Direction: In ; Request: Descriptor */ 605 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, 606 void *buffer, int txlen, 607 struct devrequest *cmd) 608 { 609 unsigned char data[32]; 610 uint32_t dsc; 611 int len = 0; 612 int stat = 0; 613 uint16_t wValue = cpu_to_le16(cmd->value); 614 uint16_t wLength = cpu_to_le16(cmd->length); 615 616 switch (cmd->requesttype & ~USB_DIR_IN) { 617 case 0: 618 switch (wValue & 0xff00) { 619 case 0x0100: /* device descriptor */ 620 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); 621 memcpy(buffer, root_hub_dev_des, len); 622 break; 623 case 0x0200: /* configuration descriptor */ 624 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); 625 memcpy(buffer, root_hub_config_des, len); 626 break; 627 case 0x0300: /* string descriptors */ 628 switch (wValue & 0xff) { 629 case 0x00: 630 len = min3(txlen, (int)sizeof(root_hub_str_index0), 631 (int)wLength); 632 memcpy(buffer, root_hub_str_index0, len); 633 break; 634 case 0x01: 635 len = min3(txlen, (int)sizeof(root_hub_str_index1), 636 (int)wLength); 637 memcpy(buffer, root_hub_str_index1, len); 638 break; 639 } 640 break; 641 default: 642 stat = USB_ST_STALLED; 643 } 644 break; 645 646 case USB_TYPE_CLASS: 647 /* Root port config, set 1 port and nothing else. */ 648 dsc = 0x00000001; 649 650 data[0] = 9; /* min length; */ 651 data[1] = 0x29; 652 data[2] = dsc & RH_A_NDP; 653 data[3] = 0; 654 if (dsc & RH_A_PSM) 655 data[3] |= 0x1; 656 if (dsc & RH_A_NOCP) 657 data[3] |= 0x10; 658 else if (dsc & RH_A_OCPM) 659 data[3] |= 0x8; 660 661 /* corresponds to data[4-7] */ 662 data[5] = (dsc & RH_A_POTPGT) >> 24; 663 data[7] = dsc & RH_B_DR; 664 if (data[2] < 7) { 665 data[8] = 0xff; 666 } else { 667 data[0] += 2; 668 data[8] = (dsc & RH_B_DR) >> 8; 669 data[9] = 0xff; 670 data[10] = data[9]; 671 } 672 673 len = min3(txlen, (int)data[0], (int)wLength); 674 memcpy(buffer, data, len); 675 break; 676 default: 677 puts("unsupported root hub command\n"); 678 stat = USB_ST_STALLED; 679 } 680 681 dev->act_len = min(len, txlen); 682 dev->status = stat; 683 684 return stat; 685 } 686 687 /* Direction: In ; Request: Configuration */ 688 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, 689 void *buffer, int txlen, 690 struct devrequest *cmd) 691 { 692 int len = 0; 693 int stat = 0; 694 695 switch (cmd->requesttype & ~USB_DIR_IN) { 696 case 0: 697 *(uint8_t *)buffer = 0x01; 698 len = 1; 699 break; 700 default: 701 puts("unsupported root hub command\n"); 702 stat = USB_ST_STALLED; 703 } 704 705 dev->act_len = min(len, txlen); 706 dev->status = stat; 707 708 return stat; 709 } 710 711 /* Direction: In */ 712 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, 713 struct usb_device *dev, void *buffer, 714 int txlen, struct devrequest *cmd) 715 { 716 switch (cmd->request) { 717 case USB_REQ_GET_STATUS: 718 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, 719 txlen, cmd); 720 case USB_REQ_GET_DESCRIPTOR: 721 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, 722 txlen, cmd); 723 case USB_REQ_GET_CONFIGURATION: 724 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, 725 txlen, cmd); 726 default: 727 puts("unsupported root hub command\n"); 728 return USB_ST_STALLED; 729 } 730 } 731 732 /* Direction: Out */ 733 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, 734 struct usb_device *dev, 735 void *buffer, int txlen, 736 struct devrequest *cmd) 737 { 738 struct dwc2_core_regs *regs = priv->regs; 739 int len = 0; 740 int stat = 0; 741 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); 742 uint16_t wValue = cpu_to_le16(cmd->value); 743 744 switch (bmrtype_breq & ~USB_DIR_IN) { 745 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: 746 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: 747 break; 748 749 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 750 switch (wValue) { 751 case USB_PORT_FEAT_C_CONNECTION: 752 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); 753 break; 754 } 755 break; 756 757 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 758 switch (wValue) { 759 case USB_PORT_FEAT_SUSPEND: 760 break; 761 762 case USB_PORT_FEAT_RESET: 763 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 764 DWC2_HPRT0_PRTCONNDET | 765 DWC2_HPRT0_PRTENCHNG | 766 DWC2_HPRT0_PRTOVRCURRCHNG, 767 DWC2_HPRT0_PRTRST); 768 mdelay(50); 769 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); 770 break; 771 772 case USB_PORT_FEAT_POWER: 773 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 774 DWC2_HPRT0_PRTCONNDET | 775 DWC2_HPRT0_PRTENCHNG | 776 DWC2_HPRT0_PRTOVRCURRCHNG, 777 DWC2_HPRT0_PRTRST); 778 break; 779 780 case USB_PORT_FEAT_ENABLE: 781 break; 782 } 783 break; 784 case (USB_REQ_SET_ADDRESS << 8): 785 priv->root_hub_devnum = wValue; 786 break; 787 case (USB_REQ_SET_CONFIGURATION << 8): 788 break; 789 default: 790 puts("unsupported root hub command\n"); 791 stat = USB_ST_STALLED; 792 } 793 794 len = min(len, txlen); 795 796 dev->act_len = len; 797 dev->status = stat; 798 799 return stat; 800 } 801 802 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, 803 unsigned long pipe, void *buffer, int txlen, 804 struct devrequest *cmd) 805 { 806 int stat = 0; 807 808 if (usb_pipeint(pipe)) { 809 puts("Root-Hub submit IRQ: NOT implemented\n"); 810 return 0; 811 } 812 813 if (cmd->requesttype & USB_DIR_IN) 814 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); 815 else 816 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); 817 818 mdelay(1); 819 820 return stat; 821 } 822 823 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle) 824 { 825 int ret; 826 uint32_t hcint, hctsiz; 827 828 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true, 829 2000, false); 830 if (ret) 831 return ret; 832 833 hcint = readl(&hc_regs->hcint); 834 hctsiz = readl(&hc_regs->hctsiz); 835 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> 836 DWC2_HCTSIZ_XFERSIZE_OFFSET; 837 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; 838 839 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, 840 *toggle); 841 842 if (hcint & DWC2_HCINT_XFERCOMP) 843 return 0; 844 845 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) 846 return -EAGAIN; 847 848 debug("%s: Error (HCINT=%08x)\n", __func__, hcint); 849 return -EINVAL; 850 } 851 852 static int dwc2_eptype[] = { 853 DWC2_HCCHAR_EPTYPE_ISOC, 854 DWC2_HCCHAR_EPTYPE_INTR, 855 DWC2_HCCHAR_EPTYPE_CONTROL, 856 DWC2_HCCHAR_EPTYPE_BULK, 857 }; 858 859 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, 860 u8 *pid, int in, void *buffer, int num_packets, 861 int xfer_len, int *actual_len, int odd_frame) 862 { 863 int ret = 0; 864 uint32_t sub; 865 866 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, 867 *pid, xfer_len, num_packets); 868 869 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | 870 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | 871 (*pid << DWC2_HCTSIZ_PID_OFFSET), 872 &hc_regs->hctsiz); 873 874 if (xfer_len) { 875 if (in) { 876 invalidate_dcache_range( 877 (uintptr_t)aligned_buffer, 878 (uintptr_t)aligned_buffer + 879 roundup(xfer_len, ARCH_DMA_MINALIGN)); 880 } else { 881 memcpy(aligned_buffer, buffer, xfer_len); 882 flush_dcache_range( 883 (uintptr_t)aligned_buffer, 884 (uintptr_t)aligned_buffer + 885 roundup(xfer_len, ARCH_DMA_MINALIGN)); 886 } 887 } 888 889 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); 890 891 /* Clear old interrupt conditions for this host channel. */ 892 writel(0x3fff, &hc_regs->hcint); 893 894 /* Set host channel enable after all other setup is complete. */ 895 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | 896 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS | 897 DWC2_HCCHAR_ODDFRM, 898 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | 899 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) | 900 DWC2_HCCHAR_CHEN); 901 902 ret = wait_for_chhltd(hc_regs, &sub, pid); 903 if (ret < 0) 904 return ret; 905 906 if (in) { 907 xfer_len -= sub; 908 909 invalidate_dcache_range((unsigned long)aligned_buffer, 910 (unsigned long)aligned_buffer + 911 roundup(xfer_len, ARCH_DMA_MINALIGN)); 912 913 memcpy(buffer, aligned_buffer, xfer_len); 914 } 915 *actual_len = xfer_len; 916 917 return ret; 918 } 919 920 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, 921 unsigned long pipe, u8 *pid, int in, void *buffer, int len) 922 { 923 struct dwc2_core_regs *regs = priv->regs; 924 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 925 struct dwc2_host_regs *host_regs = ®s->host_regs; 926 int devnum = usb_pipedevice(pipe); 927 int ep = usb_pipeendpoint(pipe); 928 int max = usb_maxpacket(dev, pipe); 929 int eptype = dwc2_eptype[usb_pipetype(pipe)]; 930 int done = 0; 931 int ret = 0; 932 int do_split = 0; 933 int complete_split = 0; 934 uint32_t xfer_len; 935 uint32_t num_packets; 936 int stop_transfer = 0; 937 uint32_t max_xfer_len; 938 int ssplit_frame_num = 0; 939 940 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, 941 in, len); 942 943 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; 944 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) 945 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; 946 if (max_xfer_len > DWC2_DATA_BUF_SIZE) 947 max_xfer_len = DWC2_DATA_BUF_SIZE; 948 949 /* Make sure that max_xfer_len is a multiple of max packet size. */ 950 num_packets = max_xfer_len / max; 951 max_xfer_len = num_packets * max; 952 953 /* Initialize channel */ 954 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, 955 eptype, max); 956 957 /* Check if the target is a FS/LS device behind a HS hub */ 958 if (dev->speed != USB_SPEED_HIGH) { 959 uint8_t hub_addr; 960 uint8_t hub_port; 961 uint32_t hprt0 = readl(®s->hprt0); 962 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 963 DWC2_HPRT0_PRTSPD_HIGH) { 964 usb_find_usb2_hub_address_port(dev, &hub_addr, 965 &hub_port); 966 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port); 967 968 do_split = 1; 969 num_packets = 1; 970 max_xfer_len = max; 971 } 972 } 973 974 do { 975 int actual_len = 0; 976 uint32_t hcint; 977 int odd_frame = 0; 978 xfer_len = len - done; 979 980 if (xfer_len > max_xfer_len) 981 xfer_len = max_xfer_len; 982 else if (xfer_len > max) 983 num_packets = (xfer_len + max - 1) / max; 984 else 985 num_packets = 1; 986 987 if (complete_split) 988 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 989 else if (do_split) 990 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 991 992 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) { 993 int uframe_num = readl(&host_regs->hfnum); 994 if (!(uframe_num & 0x1)) 995 odd_frame = 1; 996 } 997 998 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, 999 in, (char *)buffer + done, num_packets, 1000 xfer_len, &actual_len, odd_frame); 1001 1002 hcint = readl(&hc_regs->hcint); 1003 if (complete_split) { 1004 stop_transfer = 0; 1005 if (hcint & DWC2_HCINT_NYET) { 1006 ret = 0; 1007 int frame_num = DWC2_HFNUM_MAX_FRNUM & 1008 readl(&host_regs->hfnum); 1009 if (((frame_num - ssplit_frame_num) & 1010 DWC2_HFNUM_MAX_FRNUM) > 4) 1011 ret = -EAGAIN; 1012 } else 1013 complete_split = 0; 1014 } else if (do_split) { 1015 if (hcint & DWC2_HCINT_ACK) { 1016 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM & 1017 readl(&host_regs->hfnum); 1018 ret = 0; 1019 complete_split = 1; 1020 } 1021 } 1022 1023 if (ret) 1024 break; 1025 1026 if (actual_len < xfer_len) 1027 stop_transfer = 1; 1028 1029 done += actual_len; 1030 1031 /* Transactions are done when when either all data is transferred or 1032 * there is a short transfer. In case of a SPLIT make sure the CSPLIT 1033 * is executed. 1034 */ 1035 } while (((done < len) && !stop_transfer) || complete_split); 1036 1037 writel(0, &hc_regs->hcintmsk); 1038 writel(0xFFFFFFFF, &hc_regs->hcint); 1039 1040 dev->status = 0; 1041 dev->act_len = done; 1042 1043 return ret; 1044 } 1045 1046 /* U-Boot USB transmission interface */ 1047 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, 1048 unsigned long pipe, void *buffer, int len) 1049 { 1050 int devnum = usb_pipedevice(pipe); 1051 int ep = usb_pipeendpoint(pipe); 1052 u8* pid; 1053 1054 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) { 1055 dev->status = 0; 1056 return -EINVAL; 1057 } 1058 1059 if (usb_pipein(pipe)) 1060 pid = &priv->in_data_toggle[devnum][ep]; 1061 else 1062 pid = &priv->out_data_toggle[devnum][ep]; 1063 1064 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len); 1065 } 1066 1067 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, 1068 unsigned long pipe, void *buffer, int len, 1069 struct devrequest *setup) 1070 { 1071 int devnum = usb_pipedevice(pipe); 1072 int ret, act_len; 1073 u8 pid; 1074 /* For CONTROL endpoint pid should start with DATA1 */ 1075 int status_direction; 1076 1077 if (devnum == priv->root_hub_devnum) { 1078 dev->status = 0; 1079 dev->speed = USB_SPEED_HIGH; 1080 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, 1081 setup); 1082 } 1083 1084 /* SETUP stage */ 1085 pid = DWC2_HC_PID_SETUP; 1086 do { 1087 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8); 1088 } while (ret == -EAGAIN); 1089 if (ret) 1090 return ret; 1091 1092 /* DATA stage */ 1093 act_len = 0; 1094 if (buffer) { 1095 pid = DWC2_HC_PID_DATA1; 1096 do { 1097 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), 1098 buffer, len); 1099 act_len += dev->act_len; 1100 buffer += dev->act_len; 1101 len -= dev->act_len; 1102 } while (ret == -EAGAIN); 1103 if (ret) 1104 return ret; 1105 status_direction = usb_pipeout(pipe); 1106 } else { 1107 /* No-data CONTROL always ends with an IN transaction */ 1108 status_direction = 1; 1109 } 1110 1111 /* STATUS stage */ 1112 pid = DWC2_HC_PID_DATA1; 1113 do { 1114 ret = chunk_msg(priv, dev, pipe, &pid, status_direction, 1115 priv->status_buffer, 0); 1116 } while (ret == -EAGAIN); 1117 if (ret) 1118 return ret; 1119 1120 dev->act_len = act_len; 1121 1122 return 0; 1123 } 1124 1125 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, 1126 unsigned long pipe, void *buffer, int len, int interval, 1127 bool nonblock) 1128 { 1129 unsigned long timeout; 1130 int ret; 1131 1132 /* FIXME: what is interval? */ 1133 1134 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1135 for (;;) { 1136 if (get_timer(0) > timeout) { 1137 dev_err(dev, "Timeout poll on interrupt endpoint\n"); 1138 return -ETIMEDOUT; 1139 } 1140 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); 1141 if ((ret != -EAGAIN) || nonblock) 1142 return ret; 1143 } 1144 } 1145 1146 static int dwc2_reset(struct udevice *dev) 1147 { 1148 int ret; 1149 struct dwc2_priv *priv = dev_get_priv(dev); 1150 1151 ret = reset_get_bulk(dev, &priv->resets); 1152 if (ret) { 1153 dev_warn(dev, "Can't get reset: %d\n", ret); 1154 /* Return 0 if error due to !CONFIG_DM_RESET and reset 1155 * DT property is not present. 1156 */ 1157 if (ret == -ENOENT || ret == -ENOTSUPP) 1158 return 0; 1159 else 1160 return ret; 1161 } 1162 1163 /* force reset to clear all IP register */ 1164 reset_assert_bulk(&priv->resets); 1165 ret = reset_deassert_bulk(&priv->resets); 1166 if (ret) { 1167 reset_release_bulk(&priv->resets); 1168 dev_err(dev, "Failed to reset: %d\n", ret); 1169 return ret; 1170 } 1171 1172 return 0; 1173 } 1174 1175 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) 1176 { 1177 struct dwc2_core_regs *regs = priv->regs; 1178 uint32_t snpsid; 1179 int i, j; 1180 int ret; 1181 1182 ret = dwc2_reset(dev); 1183 if (ret) 1184 return ret; 1185 1186 snpsid = readl(®s->gsnpsid); 1187 dev_info(dev, "Core Release: %x.%03x\n", 1188 snpsid >> 12 & 0xf, snpsid & 0xfff); 1189 1190 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && 1191 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { 1192 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n", 1193 snpsid); 1194 return -ENODEV; 1195 } 1196 1197 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS 1198 priv->ext_vbus = 1; 1199 #else 1200 priv->ext_vbus = 0; 1201 #endif 1202 1203 dwc_otg_core_init(priv); 1204 dwc_otg_core_host_init(dev, regs); 1205 1206 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1207 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1208 DWC2_HPRT0_PRTOVRCURRCHNG, 1209 DWC2_HPRT0_PRTRST); 1210 mdelay(50); 1211 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | 1212 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | 1213 DWC2_HPRT0_PRTRST); 1214 1215 for (i = 0; i < MAX_DEVICE; i++) { 1216 for (j = 0; j < MAX_ENDPOINT; j++) { 1217 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1218 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1219 } 1220 } 1221 1222 /* 1223 * Add a 1 second delay here. This gives the host controller 1224 * a bit time before the comminucation with the USB devices 1225 * is started (the bus is scanned) and fixes the USB detection 1226 * problems with some problematic USB keys. 1227 */ 1228 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 1229 mdelay(1000); 1230 1231 printf("USB DWC2\n"); 1232 1233 return 0; 1234 } 1235 1236 static void dwc2_uninit_common(struct dwc2_core_regs *regs) 1237 { 1238 /* Put everything in reset. */ 1239 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1240 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1241 DWC2_HPRT0_PRTOVRCURRCHNG, 1242 DWC2_HPRT0_PRTRST); 1243 } 1244 1245 #if !CONFIG_IS_ENABLED(DM_USB) 1246 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1247 int len, struct devrequest *setup) 1248 { 1249 return _submit_control_msg(&local, dev, pipe, buffer, len, setup); 1250 } 1251 1252 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1253 int len) 1254 { 1255 return _submit_bulk_msg(&local, dev, pipe, buffer, len); 1256 } 1257 1258 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1259 int len, int interval, bool nonblock) 1260 { 1261 return _submit_int_msg(&local, dev, pipe, buffer, len, interval, 1262 nonblock); 1263 } 1264 1265 /* U-Boot USB control interface */ 1266 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1267 { 1268 struct dwc2_priv *priv = &local; 1269 1270 memset(priv, '\0', sizeof(*priv)); 1271 priv->root_hub_devnum = 0; 1272 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; 1273 priv->aligned_buffer = aligned_buffer_addr; 1274 priv->status_buffer = status_buffer_addr; 1275 1276 /* board-dependant init */ 1277 if (board_usb_init(index, USB_INIT_HOST)) 1278 return -1; 1279 1280 return dwc2_init_common(NULL, priv); 1281 } 1282 1283 int usb_lowlevel_stop(int index) 1284 { 1285 dwc2_uninit_common(local.regs); 1286 1287 return 0; 1288 } 1289 #endif 1290 1291 #if CONFIG_IS_ENABLED(DM_USB) 1292 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1293 unsigned long pipe, void *buffer, int length, 1294 struct devrequest *setup) 1295 { 1296 struct dwc2_priv *priv = dev_get_priv(dev); 1297 1298 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1299 dev->name, udev, udev->dev->name, udev->portnr); 1300 1301 return _submit_control_msg(priv, udev, pipe, buffer, length, setup); 1302 } 1303 1304 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1305 unsigned long pipe, void *buffer, int length) 1306 { 1307 struct dwc2_priv *priv = dev_get_priv(dev); 1308 1309 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1310 1311 return _submit_bulk_msg(priv, udev, pipe, buffer, length); 1312 } 1313 1314 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1315 unsigned long pipe, void *buffer, int length, 1316 int interval, bool nonblock) 1317 { 1318 struct dwc2_priv *priv = dev_get_priv(dev); 1319 1320 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1321 1322 return _submit_int_msg(priv, udev, pipe, buffer, length, interval, 1323 nonblock); 1324 } 1325 1326 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) 1327 { 1328 struct dwc2_priv *priv = dev_get_priv(dev); 1329 fdt_addr_t addr; 1330 1331 addr = dev_read_addr(dev); 1332 if (addr == FDT_ADDR_T_NONE) 1333 return -EINVAL; 1334 priv->regs = (struct dwc2_core_regs *)addr; 1335 1336 priv->oc_disable = dev_read_bool(dev, "disable-over-current"); 1337 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable"); 1338 1339 return 0; 1340 } 1341 1342 static int dwc2_setup_phy(struct udevice *dev) 1343 { 1344 struct dwc2_priv *priv = dev_get_priv(dev); 1345 int ret; 1346 1347 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 1348 if (ret) { 1349 if (ret == -ENOENT) 1350 return 0; /* no PHY, nothing to do */ 1351 dev_err(dev, "Failed to get USB PHY: %d.\n", ret); 1352 return ret; 1353 } 1354 1355 ret = generic_phy_init(&priv->phy); 1356 if (ret) { 1357 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret); 1358 return ret; 1359 } 1360 1361 ret = generic_phy_power_on(&priv->phy); 1362 if (ret) { 1363 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret); 1364 generic_phy_exit(&priv->phy); 1365 return ret; 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int dwc2_shutdown_phy(struct udevice *dev) 1372 { 1373 struct dwc2_priv *priv = dev_get_priv(dev); 1374 int ret; 1375 1376 /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */ 1377 if (!generic_phy_valid(&priv->phy)) 1378 return 0; /* no PHY, nothing to do */ 1379 1380 ret = generic_phy_power_off(&priv->phy); 1381 if (ret) { 1382 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret); 1383 return ret; 1384 } 1385 1386 ret = generic_phy_exit(&priv->phy); 1387 if (ret) { 1388 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret); 1389 return ret; 1390 } 1391 1392 return 0; 1393 } 1394 1395 static int dwc2_clk_init(struct udevice *dev) 1396 { 1397 struct dwc2_priv *priv = dev_get_priv(dev); 1398 int ret; 1399 1400 ret = clk_get_bulk(dev, &priv->clks); 1401 if (ret == -ENOSYS || ret == -ENOENT) 1402 return 0; 1403 if (ret) 1404 return ret; 1405 1406 ret = clk_enable_bulk(&priv->clks); 1407 if (ret) { 1408 clk_release_bulk(&priv->clks); 1409 return ret; 1410 } 1411 1412 return 0; 1413 } 1414 1415 static int dwc2_usb_probe(struct udevice *dev) 1416 { 1417 struct dwc2_priv *priv = dev_get_priv(dev); 1418 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); 1419 int ret; 1420 1421 bus_priv->desc_before_addr = true; 1422 1423 #ifdef CONFIG_ARCH_ROCKCHIP 1424 priv->hnp_srp_disable = true; 1425 #endif 1426 1427 ret = dwc2_clk_init(dev); 1428 if (ret) 1429 return ret; 1430 1431 ret = dwc2_setup_phy(dev); 1432 if (ret) 1433 return ret; 1434 1435 return dwc2_init_common(dev, priv); 1436 } 1437 1438 static int dwc2_usb_remove(struct udevice *dev) 1439 { 1440 struct dwc2_priv *priv = dev_get_priv(dev); 1441 int ret; 1442 1443 ret = dwc_vbus_supply_exit(dev); 1444 if (ret) 1445 return ret; 1446 1447 ret = dwc2_shutdown_phy(dev); 1448 if (ret) { 1449 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret); 1450 return ret; 1451 } 1452 1453 dwc2_uninit_common(priv->regs); 1454 1455 reset_release_bulk(&priv->resets); 1456 clk_disable_bulk(&priv->clks); 1457 clk_release_bulk(&priv->clks); 1458 1459 return 0; 1460 } 1461 1462 struct dm_usb_ops dwc2_usb_ops = { 1463 .control = dwc2_submit_control_msg, 1464 .bulk = dwc2_submit_bulk_msg, 1465 .interrupt = dwc2_submit_int_msg, 1466 }; 1467 1468 static const struct udevice_id dwc2_usb_ids[] = { 1469 { .compatible = "brcm,bcm2835-usb" }, 1470 { .compatible = "brcm,bcm2708-usb" }, 1471 { .compatible = "snps,dwc2" }, 1472 { } 1473 }; 1474 1475 U_BOOT_DRIVER(usb_dwc2) = { 1476 .name = "dwc2_usb", 1477 .id = UCLASS_USB, 1478 .of_match = dwc2_usb_ids, 1479 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, 1480 .probe = dwc2_usb_probe, 1481 .remove = dwc2_usb_remove, 1482 .ops = &dwc2_usb_ops, 1483 .priv_auto_alloc_size = sizeof(struct dwc2_priv), 1484 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1485 }; 1486 #endif 1487