1 /* 2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <usb.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <phys2bus.h> 15 #include <usbroothubdes.h> 16 #include <wait_bit.h> 17 #include <asm/io.h> 18 19 #include "dwc2.h" 20 21 /* Use only HC channel 0. */ 22 #define DWC2_HC_CHANNEL 0 23 24 #define DWC2_STATUS_BUF_SIZE 64 25 #define DWC2_DATA_BUF_SIZE (64 * 1024) 26 27 #define MAX_DEVICE 16 28 #define MAX_ENDPOINT 16 29 30 struct dwc2_priv { 31 #ifdef CONFIG_DM_USB 32 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 33 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 34 #else 35 uint8_t *aligned_buffer; 36 uint8_t *status_buffer; 37 #endif 38 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 39 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 40 struct dwc2_core_regs *regs; 41 int root_hub_devnum; 42 bool ext_vbus; 43 }; 44 45 #ifndef CONFIG_DM_USB 46 /* We need cacheline-aligned buffers for DMA transfers and dcache support */ 47 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 48 ARCH_DMA_MINALIGN); 49 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 50 ARCH_DMA_MINALIGN); 51 52 static struct dwc2_priv local; 53 #endif 54 55 /* 56 * DWC2 IP interface 57 */ 58 59 /* 60 * Initializes the FSLSPClkSel field of the HCFG register 61 * depending on the PHY type. 62 */ 63 static void init_fslspclksel(struct dwc2_core_regs *regs) 64 { 65 uint32_t phyclk; 66 67 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 68 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 69 #else 70 /* High speed PHY running at full speed or high speed */ 71 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; 72 #endif 73 74 #ifdef CONFIG_DWC2_ULPI_FS_LS 75 uint32_t hwcfg2 = readl(®s->ghwcfg2); 76 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 77 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 78 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 79 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 80 81 if (hval == 2 && fval == 1) 82 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 83 #endif 84 85 clrsetbits_le32(®s->host_regs.hcfg, 86 DWC2_HCFG_FSLSPCLKSEL_MASK, 87 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); 88 } 89 90 /* 91 * Flush a Tx FIFO. 92 * 93 * @param regs Programming view of DWC_otg controller. 94 * @param num Tx FIFO to flush. 95 */ 96 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) 97 { 98 int ret; 99 100 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), 101 ®s->grstctl); 102 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 103 false, 1000, false); 104 if (ret) 105 printf("%s: Timeout!\n", __func__); 106 107 /* Wait for 3 PHY Clocks */ 108 udelay(1); 109 } 110 111 /* 112 * Flush Rx FIFO. 113 * 114 * @param regs Programming view of DWC_otg controller. 115 */ 116 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) 117 { 118 int ret; 119 120 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); 121 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 122 false, 1000, false); 123 if (ret) 124 printf("%s: Timeout!\n", __func__); 125 126 /* Wait for 3 PHY Clocks */ 127 udelay(1); 128 } 129 130 /* 131 * Do core a soft reset of the core. Be careful with this because it 132 * resets all the internal state machines of the core. 133 */ 134 static void dwc_otg_core_reset(struct dwc2_core_regs *regs) 135 { 136 int ret; 137 138 /* Wait for AHB master IDLE state. */ 139 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 140 true, 1000, false); 141 if (ret) 142 printf("%s: Timeout!\n", __func__); 143 144 /* Core Soft Reset */ 145 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); 146 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST, 147 false, 1000, false); 148 if (ret) 149 printf("%s: Timeout!\n", __func__); 150 151 /* 152 * Wait for core to come out of reset. 153 * NOTE: This long sleep is _very_ important, otherwise the core will 154 * not stay in host mode after a connector ID change! 155 */ 156 mdelay(100); 157 } 158 159 /* 160 * This function initializes the DWC_otg controller registers for 161 * host mode. 162 * 163 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the 164 * request queues. Host channels are reset to ensure that they are ready for 165 * performing transfers. 166 * 167 * @param regs Programming view of DWC_otg controller 168 * 169 */ 170 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs) 171 { 172 uint32_t nptxfifosize = 0; 173 uint32_t ptxfifosize = 0; 174 uint32_t hprt0 = 0; 175 int i, ret, num_channels; 176 177 /* Restart the Phy Clock */ 178 writel(0, ®s->pcgcctl); 179 180 /* Initialize Host Configuration Register */ 181 init_fslspclksel(regs); 182 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL 183 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); 184 #endif 185 186 /* Configure data FIFO sizes */ 187 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO 188 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { 189 /* Rx FIFO */ 190 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); 191 192 /* Non-periodic Tx FIFO */ 193 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << 194 DWC2_FIFOSIZE_DEPTH_OFFSET; 195 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << 196 DWC2_FIFOSIZE_STARTADDR_OFFSET; 197 writel(nptxfifosize, ®s->gnptxfsiz); 198 199 /* Periodic Tx FIFO */ 200 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << 201 DWC2_FIFOSIZE_DEPTH_OFFSET; 202 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + 203 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << 204 DWC2_FIFOSIZE_STARTADDR_OFFSET; 205 writel(ptxfifosize, ®s->hptxfsiz); 206 } 207 #endif 208 209 /* Clear Host Set HNP Enable in the OTG Control Register */ 210 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); 211 212 /* Make sure the FIFOs are flushed. */ 213 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ 214 dwc_otg_flush_rx_fifo(regs); 215 216 /* Flush out any leftover queued requests. */ 217 num_channels = readl(®s->ghwcfg2); 218 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; 219 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; 220 num_channels += 1; 221 222 for (i = 0; i < num_channels; i++) 223 clrsetbits_le32(®s->hc_regs[i].hcchar, 224 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, 225 DWC2_HCCHAR_CHDIS); 226 227 /* Halt all channels to put them into a known state. */ 228 for (i = 0; i < num_channels; i++) { 229 clrsetbits_le32(®s->hc_regs[i].hcchar, 230 DWC2_HCCHAR_EPDIR, 231 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); 232 ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar, 233 DWC2_HCCHAR_CHEN, false, 1000, false); 234 if (ret) 235 printf("%s: Timeout!\n", __func__); 236 } 237 238 /* Turn on the vbus power. */ 239 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { 240 hprt0 = readl(®s->hprt0); 241 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); 242 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); 243 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { 244 hprt0 |= DWC2_HPRT0_PRTPWR; 245 writel(hprt0, ®s->hprt0); 246 } 247 } 248 } 249 250 /* 251 * This function initializes the DWC_otg controller registers and 252 * prepares the core for device mode or host mode operation. 253 * 254 * @param regs Programming view of the DWC_otg controller 255 */ 256 static void dwc_otg_core_init(struct dwc2_priv *priv) 257 { 258 struct dwc2_core_regs *regs = priv->regs; 259 uint32_t ahbcfg = 0; 260 uint32_t usbcfg = 0; 261 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; 262 263 /* Common Initialization */ 264 usbcfg = readl(®s->gusbcfg); 265 266 /* Program the ULPI External VBUS bit if needed */ 267 if (priv->ext_vbus) { 268 usbcfg |= (DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV | 269 DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR | 270 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH); 271 } else { 272 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 273 } 274 275 /* Set external TS Dline pulsing */ 276 #ifdef CONFIG_DWC2_TS_DLINE 277 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 278 #else 279 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 280 #endif 281 writel(usbcfg, ®s->gusbcfg); 282 283 /* Reset the Controller */ 284 dwc_otg_core_reset(regs); 285 286 /* 287 * This programming sequence needs to happen in FS mode before 288 * any other programming occurs 289 */ 290 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ 291 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 292 /* If FS mode with FS PHY */ 293 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); 294 295 /* Reset after a PHY select */ 296 dwc_otg_core_reset(regs); 297 298 /* 299 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. 300 * Also do this on HNP Dev/Host mode switches (done in dev_init 301 * and host_init). 302 */ 303 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 304 init_fslspclksel(regs); 305 306 #ifdef CONFIG_DWC2_I2C_ENABLE 307 /* Program GUSBCFG.OtgUtmifsSel to I2C */ 308 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); 309 310 /* Program GI2CCTL.I2CEn */ 311 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | 312 DWC2_GI2CCTL_I2CDEVADDR_MASK, 313 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); 314 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); 315 #endif 316 317 #else 318 /* High speed PHY. */ 319 320 /* 321 * HS PHY parameters. These parameters are preserved during 322 * soft reset so only program the first time. Do a soft reset 323 * immediately after setting phyif. 324 */ 325 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); 326 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; 327 328 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ 329 #ifdef CONFIG_DWC2_PHY_ULPI_DDR 330 usbcfg |= DWC2_GUSBCFG_DDRSEL; 331 #else 332 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; 333 #endif 334 } else { /* UTMI+ interface */ 335 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16) 336 usbcfg |= DWC2_GUSBCFG_PHYIF; 337 #endif 338 } 339 340 writel(usbcfg, ®s->gusbcfg); 341 342 /* Reset after setting the PHY parameters */ 343 dwc_otg_core_reset(regs); 344 #endif 345 346 usbcfg = readl(®s->gusbcfg); 347 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); 348 #ifdef CONFIG_DWC2_ULPI_FS_LS 349 uint32_t hwcfg2 = readl(®s->ghwcfg2); 350 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 351 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 352 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 353 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 354 if (hval == 2 && fval == 1) { 355 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; 356 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; 357 } 358 #endif 359 writel(usbcfg, ®s->gusbcfg); 360 361 /* Program the GAHBCFG Register. */ 362 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { 363 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: 364 break; 365 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: 366 while (brst_sz > 1) { 367 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); 368 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; 369 brst_sz >>= 1; 370 } 371 372 #ifdef CONFIG_DWC2_DMA_ENABLE 373 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 374 #endif 375 break; 376 377 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: 378 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; 379 #ifdef CONFIG_DWC2_DMA_ENABLE 380 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 381 #endif 382 break; 383 } 384 385 writel(ahbcfg, ®s->gahbcfg); 386 387 /* Program the GUSBCFG register for HNP/SRP. */ 388 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP); 389 390 #ifdef CONFIG_DWC2_IC_USB_CAP 391 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP); 392 #endif 393 } 394 395 /* 396 * Prepares a host channel for transferring packets to/from a specific 397 * endpoint. The HCCHARn register is set up with the characteristics specified 398 * in _hc. Host channel interrupts that may need to be serviced while this 399 * transfer is in progress are enabled. 400 * 401 * @param regs Programming view of DWC_otg controller 402 * @param hc Information needed to initialize the host channel 403 */ 404 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, 405 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, 406 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) 407 { 408 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; 409 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | 410 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | 411 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | 412 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | 413 (max_packet << DWC2_HCCHAR_MPS_OFFSET); 414 415 if (dev->speed == USB_SPEED_LOW) 416 hcchar |= DWC2_HCCHAR_LSPDDEV; 417 418 /* 419 * Program the HCCHARn register with the endpoint characteristics 420 * for the current transfer. 421 */ 422 writel(hcchar, &hc_regs->hcchar); 423 424 /* Program the HCSPLIT register, default to no SPLIT */ 425 writel(0, &hc_regs->hcsplt); 426 } 427 428 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs, 429 uint8_t hub_devnum, uint8_t hub_port) 430 { 431 uint32_t hcsplt = 0; 432 433 hcsplt = DWC2_HCSPLT_SPLTENA; 434 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET; 435 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET; 436 437 /* Program the HCSPLIT register for SPLITs */ 438 writel(hcsplt, &hc_regs->hcsplt); 439 } 440 441 /* 442 * DWC2 to USB API interface 443 */ 444 /* Direction: In ; Request: Status */ 445 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, 446 struct usb_device *dev, void *buffer, 447 int txlen, struct devrequest *cmd) 448 { 449 uint32_t hprt0 = 0; 450 uint32_t port_status = 0; 451 uint32_t port_change = 0; 452 int len = 0; 453 int stat = 0; 454 455 switch (cmd->requesttype & ~USB_DIR_IN) { 456 case 0: 457 *(uint16_t *)buffer = cpu_to_le16(1); 458 len = 2; 459 break; 460 case USB_RECIP_INTERFACE: 461 case USB_RECIP_ENDPOINT: 462 *(uint16_t *)buffer = cpu_to_le16(0); 463 len = 2; 464 break; 465 case USB_TYPE_CLASS: 466 *(uint32_t *)buffer = cpu_to_le32(0); 467 len = 4; 468 break; 469 case USB_RECIP_OTHER | USB_TYPE_CLASS: 470 hprt0 = readl(®s->hprt0); 471 if (hprt0 & DWC2_HPRT0_PRTCONNSTS) 472 port_status |= USB_PORT_STAT_CONNECTION; 473 if (hprt0 & DWC2_HPRT0_PRTENA) 474 port_status |= USB_PORT_STAT_ENABLE; 475 if (hprt0 & DWC2_HPRT0_PRTSUSP) 476 port_status |= USB_PORT_STAT_SUSPEND; 477 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) 478 port_status |= USB_PORT_STAT_OVERCURRENT; 479 if (hprt0 & DWC2_HPRT0_PRTRST) 480 port_status |= USB_PORT_STAT_RESET; 481 if (hprt0 & DWC2_HPRT0_PRTPWR) 482 port_status |= USB_PORT_STAT_POWER; 483 484 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) 485 port_status |= USB_PORT_STAT_LOW_SPEED; 486 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 487 DWC2_HPRT0_PRTSPD_HIGH) 488 port_status |= USB_PORT_STAT_HIGH_SPEED; 489 490 if (hprt0 & DWC2_HPRT0_PRTENCHNG) 491 port_change |= USB_PORT_STAT_C_ENABLE; 492 if (hprt0 & DWC2_HPRT0_PRTCONNDET) 493 port_change |= USB_PORT_STAT_C_CONNECTION; 494 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) 495 port_change |= USB_PORT_STAT_C_OVERCURRENT; 496 497 *(uint32_t *)buffer = cpu_to_le32(port_status | 498 (port_change << 16)); 499 len = 4; 500 break; 501 default: 502 puts("unsupported root hub command\n"); 503 stat = USB_ST_STALLED; 504 } 505 506 dev->act_len = min(len, txlen); 507 dev->status = stat; 508 509 return stat; 510 } 511 512 /* Direction: In ; Request: Descriptor */ 513 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, 514 void *buffer, int txlen, 515 struct devrequest *cmd) 516 { 517 unsigned char data[32]; 518 uint32_t dsc; 519 int len = 0; 520 int stat = 0; 521 uint16_t wValue = cpu_to_le16(cmd->value); 522 uint16_t wLength = cpu_to_le16(cmd->length); 523 524 switch (cmd->requesttype & ~USB_DIR_IN) { 525 case 0: 526 switch (wValue & 0xff00) { 527 case 0x0100: /* device descriptor */ 528 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); 529 memcpy(buffer, root_hub_dev_des, len); 530 break; 531 case 0x0200: /* configuration descriptor */ 532 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); 533 memcpy(buffer, root_hub_config_des, len); 534 break; 535 case 0x0300: /* string descriptors */ 536 switch (wValue & 0xff) { 537 case 0x00: 538 len = min3(txlen, (int)sizeof(root_hub_str_index0), 539 (int)wLength); 540 memcpy(buffer, root_hub_str_index0, len); 541 break; 542 case 0x01: 543 len = min3(txlen, (int)sizeof(root_hub_str_index1), 544 (int)wLength); 545 memcpy(buffer, root_hub_str_index1, len); 546 break; 547 } 548 break; 549 default: 550 stat = USB_ST_STALLED; 551 } 552 break; 553 554 case USB_TYPE_CLASS: 555 /* Root port config, set 1 port and nothing else. */ 556 dsc = 0x00000001; 557 558 data[0] = 9; /* min length; */ 559 data[1] = 0x29; 560 data[2] = dsc & RH_A_NDP; 561 data[3] = 0; 562 if (dsc & RH_A_PSM) 563 data[3] |= 0x1; 564 if (dsc & RH_A_NOCP) 565 data[3] |= 0x10; 566 else if (dsc & RH_A_OCPM) 567 data[3] |= 0x8; 568 569 /* corresponds to data[4-7] */ 570 data[5] = (dsc & RH_A_POTPGT) >> 24; 571 data[7] = dsc & RH_B_DR; 572 if (data[2] < 7) { 573 data[8] = 0xff; 574 } else { 575 data[0] += 2; 576 data[8] = (dsc & RH_B_DR) >> 8; 577 data[9] = 0xff; 578 data[10] = data[9]; 579 } 580 581 len = min3(txlen, (int)data[0], (int)wLength); 582 memcpy(buffer, data, len); 583 break; 584 default: 585 puts("unsupported root hub command\n"); 586 stat = USB_ST_STALLED; 587 } 588 589 dev->act_len = min(len, txlen); 590 dev->status = stat; 591 592 return stat; 593 } 594 595 /* Direction: In ; Request: Configuration */ 596 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, 597 void *buffer, int txlen, 598 struct devrequest *cmd) 599 { 600 int len = 0; 601 int stat = 0; 602 603 switch (cmd->requesttype & ~USB_DIR_IN) { 604 case 0: 605 *(uint8_t *)buffer = 0x01; 606 len = 1; 607 break; 608 default: 609 puts("unsupported root hub command\n"); 610 stat = USB_ST_STALLED; 611 } 612 613 dev->act_len = min(len, txlen); 614 dev->status = stat; 615 616 return stat; 617 } 618 619 /* Direction: In */ 620 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, 621 struct usb_device *dev, void *buffer, 622 int txlen, struct devrequest *cmd) 623 { 624 switch (cmd->request) { 625 case USB_REQ_GET_STATUS: 626 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, 627 txlen, cmd); 628 case USB_REQ_GET_DESCRIPTOR: 629 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, 630 txlen, cmd); 631 case USB_REQ_GET_CONFIGURATION: 632 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, 633 txlen, cmd); 634 default: 635 puts("unsupported root hub command\n"); 636 return USB_ST_STALLED; 637 } 638 } 639 640 /* Direction: Out */ 641 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, 642 struct usb_device *dev, 643 void *buffer, int txlen, 644 struct devrequest *cmd) 645 { 646 struct dwc2_core_regs *regs = priv->regs; 647 int len = 0; 648 int stat = 0; 649 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); 650 uint16_t wValue = cpu_to_le16(cmd->value); 651 652 switch (bmrtype_breq & ~USB_DIR_IN) { 653 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: 654 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: 655 break; 656 657 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 658 switch (wValue) { 659 case USB_PORT_FEAT_C_CONNECTION: 660 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); 661 break; 662 } 663 break; 664 665 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 666 switch (wValue) { 667 case USB_PORT_FEAT_SUSPEND: 668 break; 669 670 case USB_PORT_FEAT_RESET: 671 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 672 DWC2_HPRT0_PRTCONNDET | 673 DWC2_HPRT0_PRTENCHNG | 674 DWC2_HPRT0_PRTOVRCURRCHNG, 675 DWC2_HPRT0_PRTRST); 676 mdelay(50); 677 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); 678 break; 679 680 case USB_PORT_FEAT_POWER: 681 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 682 DWC2_HPRT0_PRTCONNDET | 683 DWC2_HPRT0_PRTENCHNG | 684 DWC2_HPRT0_PRTOVRCURRCHNG, 685 DWC2_HPRT0_PRTRST); 686 break; 687 688 case USB_PORT_FEAT_ENABLE: 689 break; 690 } 691 break; 692 case (USB_REQ_SET_ADDRESS << 8): 693 priv->root_hub_devnum = wValue; 694 break; 695 case (USB_REQ_SET_CONFIGURATION << 8): 696 break; 697 default: 698 puts("unsupported root hub command\n"); 699 stat = USB_ST_STALLED; 700 } 701 702 len = min(len, txlen); 703 704 dev->act_len = len; 705 dev->status = stat; 706 707 return stat; 708 } 709 710 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, 711 unsigned long pipe, void *buffer, int txlen, 712 struct devrequest *cmd) 713 { 714 int stat = 0; 715 716 if (usb_pipeint(pipe)) { 717 puts("Root-Hub submit IRQ: NOT implemented\n"); 718 return 0; 719 } 720 721 if (cmd->requesttype & USB_DIR_IN) 722 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); 723 else 724 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); 725 726 mdelay(1); 727 728 return stat; 729 } 730 731 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle) 732 { 733 int ret; 734 uint32_t hcint, hctsiz; 735 736 ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true, 737 1000, false); 738 if (ret) 739 return ret; 740 741 hcint = readl(&hc_regs->hcint); 742 hctsiz = readl(&hc_regs->hctsiz); 743 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> 744 DWC2_HCTSIZ_XFERSIZE_OFFSET; 745 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; 746 747 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, 748 *toggle); 749 750 if (hcint & DWC2_HCINT_XFERCOMP) 751 return 0; 752 753 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) 754 return -EAGAIN; 755 756 debug("%s: Error (HCINT=%08x)\n", __func__, hcint); 757 return -EINVAL; 758 } 759 760 static int dwc2_eptype[] = { 761 DWC2_HCCHAR_EPTYPE_ISOC, 762 DWC2_HCCHAR_EPTYPE_INTR, 763 DWC2_HCCHAR_EPTYPE_CONTROL, 764 DWC2_HCCHAR_EPTYPE_BULK, 765 }; 766 767 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, 768 u8 *pid, int in, void *buffer, int num_packets, 769 int xfer_len, int *actual_len, int odd_frame) 770 { 771 int ret = 0; 772 uint32_t sub; 773 774 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, 775 *pid, xfer_len, num_packets); 776 777 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | 778 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | 779 (*pid << DWC2_HCTSIZ_PID_OFFSET), 780 &hc_regs->hctsiz); 781 782 if (!in && xfer_len) { 783 memcpy(aligned_buffer, buffer, xfer_len); 784 785 flush_dcache_range((unsigned long)aligned_buffer, 786 (unsigned long)aligned_buffer + 787 roundup(xfer_len, ARCH_DMA_MINALIGN)); 788 } 789 790 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); 791 792 /* Clear old interrupt conditions for this host channel. */ 793 writel(0x3fff, &hc_regs->hcint); 794 795 /* Set host channel enable after all other setup is complete. */ 796 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | 797 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS | 798 DWC2_HCCHAR_ODDFRM, 799 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | 800 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) | 801 DWC2_HCCHAR_CHEN); 802 803 ret = wait_for_chhltd(hc_regs, &sub, pid); 804 if (ret < 0) 805 return ret; 806 807 if (in) { 808 xfer_len -= sub; 809 810 invalidate_dcache_range((unsigned long)aligned_buffer, 811 (unsigned long)aligned_buffer + 812 roundup(xfer_len, ARCH_DMA_MINALIGN)); 813 814 memcpy(buffer, aligned_buffer, xfer_len); 815 } 816 *actual_len = xfer_len; 817 818 return ret; 819 } 820 821 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, 822 unsigned long pipe, u8 *pid, int in, void *buffer, int len) 823 { 824 struct dwc2_core_regs *regs = priv->regs; 825 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 826 struct dwc2_host_regs *host_regs = ®s->host_regs; 827 int devnum = usb_pipedevice(pipe); 828 int ep = usb_pipeendpoint(pipe); 829 int max = usb_maxpacket(dev, pipe); 830 int eptype = dwc2_eptype[usb_pipetype(pipe)]; 831 int done = 0; 832 int ret = 0; 833 int do_split = 0; 834 int complete_split = 0; 835 uint32_t xfer_len; 836 uint32_t num_packets; 837 int stop_transfer = 0; 838 uint32_t max_xfer_len; 839 int ssplit_frame_num = 0; 840 841 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, 842 in, len); 843 844 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; 845 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) 846 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; 847 if (max_xfer_len > DWC2_DATA_BUF_SIZE) 848 max_xfer_len = DWC2_DATA_BUF_SIZE; 849 850 /* Make sure that max_xfer_len is a multiple of max packet size. */ 851 num_packets = max_xfer_len / max; 852 max_xfer_len = num_packets * max; 853 854 /* Initialize channel */ 855 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, 856 eptype, max); 857 858 /* Check if the target is a FS/LS device behind a HS hub */ 859 if (dev->speed != USB_SPEED_HIGH) { 860 uint8_t hub_addr; 861 uint8_t hub_port; 862 uint32_t hprt0 = readl(®s->hprt0); 863 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 864 DWC2_HPRT0_PRTSPD_HIGH) { 865 usb_find_usb2_hub_address_port(dev, &hub_addr, 866 &hub_port); 867 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port); 868 869 do_split = 1; 870 num_packets = 1; 871 max_xfer_len = max; 872 } 873 } 874 875 do { 876 int actual_len = 0; 877 uint32_t hcint; 878 int odd_frame = 0; 879 xfer_len = len - done; 880 881 if (xfer_len > max_xfer_len) 882 xfer_len = max_xfer_len; 883 else if (xfer_len > max) 884 num_packets = (xfer_len + max - 1) / max; 885 else 886 num_packets = 1; 887 888 if (complete_split) 889 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 890 else if (do_split) 891 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 892 893 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) { 894 int uframe_num = readl(&host_regs->hfnum); 895 if (!(uframe_num & 0x1)) 896 odd_frame = 1; 897 } 898 899 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, 900 in, (char *)buffer + done, num_packets, 901 xfer_len, &actual_len, odd_frame); 902 903 hcint = readl(&hc_regs->hcint); 904 if (complete_split) { 905 stop_transfer = 0; 906 if (hcint & DWC2_HCINT_NYET) { 907 ret = 0; 908 int frame_num = DWC2_HFNUM_MAX_FRNUM & 909 readl(&host_regs->hfnum); 910 if (((frame_num - ssplit_frame_num) & 911 DWC2_HFNUM_MAX_FRNUM) > 4) 912 ret = -EAGAIN; 913 } else 914 complete_split = 0; 915 } else if (do_split) { 916 if (hcint & DWC2_HCINT_ACK) { 917 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM & 918 readl(&host_regs->hfnum); 919 ret = 0; 920 complete_split = 1; 921 } 922 } 923 924 if (ret) 925 break; 926 927 if (actual_len < xfer_len) 928 stop_transfer = 1; 929 930 done += actual_len; 931 932 /* Transactions are done when when either all data is transferred or 933 * there is a short transfer. In case of a SPLIT make sure the CSPLIT 934 * is executed. 935 */ 936 } while (((done < len) && !stop_transfer) || complete_split); 937 938 writel(0, &hc_regs->hcintmsk); 939 writel(0xFFFFFFFF, &hc_regs->hcint); 940 941 dev->status = 0; 942 dev->act_len = done; 943 944 return ret; 945 } 946 947 /* U-Boot USB transmission interface */ 948 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, 949 unsigned long pipe, void *buffer, int len) 950 { 951 int devnum = usb_pipedevice(pipe); 952 int ep = usb_pipeendpoint(pipe); 953 u8* pid; 954 955 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) { 956 dev->status = 0; 957 return -EINVAL; 958 } 959 960 if (usb_pipein(pipe)) 961 pid = &priv->in_data_toggle[devnum][ep]; 962 else 963 pid = &priv->out_data_toggle[devnum][ep]; 964 965 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len); 966 } 967 968 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, 969 unsigned long pipe, void *buffer, int len, 970 struct devrequest *setup) 971 { 972 int devnum = usb_pipedevice(pipe); 973 int ret, act_len; 974 u8 pid; 975 /* For CONTROL endpoint pid should start with DATA1 */ 976 int status_direction; 977 978 if (devnum == priv->root_hub_devnum) { 979 dev->status = 0; 980 dev->speed = USB_SPEED_HIGH; 981 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, 982 setup); 983 } 984 985 /* SETUP stage */ 986 pid = DWC2_HC_PID_SETUP; 987 do { 988 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8); 989 } while (ret == -EAGAIN); 990 if (ret) 991 return ret; 992 993 /* DATA stage */ 994 act_len = 0; 995 if (buffer) { 996 pid = DWC2_HC_PID_DATA1; 997 do { 998 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), 999 buffer, len); 1000 act_len += dev->act_len; 1001 buffer += dev->act_len; 1002 len -= dev->act_len; 1003 } while (ret == -EAGAIN); 1004 if (ret) 1005 return ret; 1006 status_direction = usb_pipeout(pipe); 1007 } else { 1008 /* No-data CONTROL always ends with an IN transaction */ 1009 status_direction = 1; 1010 } 1011 1012 /* STATUS stage */ 1013 pid = DWC2_HC_PID_DATA1; 1014 do { 1015 ret = chunk_msg(priv, dev, pipe, &pid, status_direction, 1016 priv->status_buffer, 0); 1017 } while (ret == -EAGAIN); 1018 if (ret) 1019 return ret; 1020 1021 dev->act_len = act_len; 1022 1023 return 0; 1024 } 1025 1026 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, 1027 unsigned long pipe, void *buffer, int len, int interval) 1028 { 1029 unsigned long timeout; 1030 int ret; 1031 1032 /* FIXME: what is interval? */ 1033 1034 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1035 for (;;) { 1036 if (get_timer(0) > timeout) { 1037 printf("Timeout poll on interrupt endpoint\n"); 1038 return -ETIMEDOUT; 1039 } 1040 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); 1041 if (ret != -EAGAIN) 1042 return ret; 1043 } 1044 } 1045 1046 static int dwc2_init_common(struct dwc2_priv *priv) 1047 { 1048 struct dwc2_core_regs *regs = priv->regs; 1049 uint32_t snpsid; 1050 int i, j; 1051 1052 snpsid = readl(®s->gsnpsid); 1053 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff); 1054 1055 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && 1056 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { 1057 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid); 1058 return -ENODEV; 1059 } 1060 1061 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS 1062 priv->ext_vbus = 1; 1063 #else 1064 priv->ext_vbus = 0; 1065 #endif 1066 1067 dwc_otg_core_init(priv); 1068 dwc_otg_core_host_init(regs); 1069 1070 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1071 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1072 DWC2_HPRT0_PRTOVRCURRCHNG, 1073 DWC2_HPRT0_PRTRST); 1074 mdelay(50); 1075 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | 1076 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | 1077 DWC2_HPRT0_PRTRST); 1078 1079 for (i = 0; i < MAX_DEVICE; i++) { 1080 for (j = 0; j < MAX_ENDPOINT; j++) { 1081 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1082 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1083 } 1084 } 1085 1086 return 0; 1087 } 1088 1089 static void dwc2_uninit_common(struct dwc2_core_regs *regs) 1090 { 1091 /* Put everything in reset. */ 1092 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1093 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1094 DWC2_HPRT0_PRTOVRCURRCHNG, 1095 DWC2_HPRT0_PRTRST); 1096 } 1097 1098 #ifndef CONFIG_DM_USB 1099 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1100 int len, struct devrequest *setup) 1101 { 1102 return _submit_control_msg(&local, dev, pipe, buffer, len, setup); 1103 } 1104 1105 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1106 int len) 1107 { 1108 return _submit_bulk_msg(&local, dev, pipe, buffer, len); 1109 } 1110 1111 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1112 int len, int interval) 1113 { 1114 return _submit_int_msg(&local, dev, pipe, buffer, len, interval); 1115 } 1116 1117 /* U-Boot USB control interface */ 1118 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1119 { 1120 struct dwc2_priv *priv = &local; 1121 1122 memset(priv, '\0', sizeof(*priv)); 1123 priv->root_hub_devnum = 0; 1124 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; 1125 priv->aligned_buffer = aligned_buffer_addr; 1126 priv->status_buffer = status_buffer_addr; 1127 1128 /* board-dependant init */ 1129 if (board_usb_init(index, USB_INIT_HOST)) 1130 return -1; 1131 1132 return dwc2_init_common(priv); 1133 } 1134 1135 int usb_lowlevel_stop(int index) 1136 { 1137 dwc2_uninit_common(local.regs); 1138 1139 return 0; 1140 } 1141 #endif 1142 1143 #ifdef CONFIG_DM_USB 1144 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1145 unsigned long pipe, void *buffer, int length, 1146 struct devrequest *setup) 1147 { 1148 struct dwc2_priv *priv = dev_get_priv(dev); 1149 1150 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1151 dev->name, udev, udev->dev->name, udev->portnr); 1152 1153 return _submit_control_msg(priv, udev, pipe, buffer, length, setup); 1154 } 1155 1156 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1157 unsigned long pipe, void *buffer, int length) 1158 { 1159 struct dwc2_priv *priv = dev_get_priv(dev); 1160 1161 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1162 1163 return _submit_bulk_msg(priv, udev, pipe, buffer, length); 1164 } 1165 1166 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1167 unsigned long pipe, void *buffer, int length, 1168 int interval) 1169 { 1170 struct dwc2_priv *priv = dev_get_priv(dev); 1171 1172 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1173 1174 return _submit_int_msg(priv, udev, pipe, buffer, length, interval); 1175 } 1176 1177 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) 1178 { 1179 struct dwc2_priv *priv = dev_get_priv(dev); 1180 fdt_addr_t addr; 1181 1182 addr = dev_get_addr(dev); 1183 if (addr == FDT_ADDR_T_NONE) 1184 return -EINVAL; 1185 priv->regs = (struct dwc2_core_regs *)addr; 1186 1187 return 0; 1188 } 1189 1190 static int dwc2_usb_probe(struct udevice *dev) 1191 { 1192 struct dwc2_priv *priv = dev_get_priv(dev); 1193 1194 return dwc2_init_common(priv); 1195 } 1196 1197 static int dwc2_usb_remove(struct udevice *dev) 1198 { 1199 struct dwc2_priv *priv = dev_get_priv(dev); 1200 1201 dwc2_uninit_common(priv->regs); 1202 1203 return 0; 1204 } 1205 1206 struct dm_usb_ops dwc2_usb_ops = { 1207 .control = dwc2_submit_control_msg, 1208 .bulk = dwc2_submit_bulk_msg, 1209 .interrupt = dwc2_submit_int_msg, 1210 }; 1211 1212 static const struct udevice_id dwc2_usb_ids[] = { 1213 { .compatible = "brcm,bcm2835-usb" }, 1214 { .compatible = "snps,dwc2" }, 1215 { } 1216 }; 1217 1218 U_BOOT_DRIVER(usb_dwc2) = { 1219 .name = "dwc2_usb", 1220 .id = UCLASS_USB, 1221 .of_match = dwc2_usb_ids, 1222 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, 1223 .probe = dwc2_usb_probe, 1224 .remove = dwc2_usb_remove, 1225 .ops = &dwc2_usb_ops, 1226 .priv_auto_alloc_size = sizeof(struct dwc2_priv), 1227 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1228 }; 1229 #endif 1230