1 /* 2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <generic-phy.h> 13 #include <malloc.h> 14 #include <memalign.h> 15 #include <phys2bus.h> 16 #include <usb.h> 17 #include <usbroothubdes.h> 18 #include <wait_bit.h> 19 #include <asm/io.h> 20 #include <power/regulator.h> 21 #include <reset.h> 22 23 #include "dwc2.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /* Use only HC channel 0. */ 28 #define DWC2_HC_CHANNEL 0 29 30 #define DWC2_STATUS_BUF_SIZE 64 31 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024) 32 33 #define MAX_DEVICE 16 34 #define MAX_ENDPOINT 16 35 36 struct dwc2_priv { 37 #if CONFIG_IS_ENABLED(DM_USB) 38 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 39 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 40 #ifdef CONFIG_DM_REGULATOR 41 struct udevice *vbus_supply; 42 #endif 43 struct phy phy; 44 struct clk_bulk clks; 45 #else 46 uint8_t *aligned_buffer; 47 uint8_t *status_buffer; 48 #endif 49 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 50 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 51 struct dwc2_core_regs *regs; 52 int root_hub_devnum; 53 bool ext_vbus; 54 /* 55 * The hnp/srp capability must be disabled if the platform 56 * does't support hnp/srp. Otherwise the force mode can't work. 57 */ 58 bool hnp_srp_disable; 59 bool oc_disable; 60 61 struct reset_ctl_bulk resets; 62 }; 63 64 #if !CONFIG_IS_ENABLED(DM_USB) 65 /* We need cacheline-aligned buffers for DMA transfers and dcache support */ 66 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 67 ARCH_DMA_MINALIGN); 68 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 69 ARCH_DMA_MINALIGN); 70 71 static struct dwc2_priv local; 72 #endif 73 74 /* 75 * DWC2 IP interface 76 */ 77 78 /* 79 * Initializes the FSLSPClkSel field of the HCFG register 80 * depending on the PHY type. 81 */ 82 static void init_fslspclksel(struct dwc2_core_regs *regs) 83 { 84 uint32_t phyclk; 85 86 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 87 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 88 #else 89 /* High speed PHY running at full speed or high speed */ 90 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; 91 #endif 92 93 #ifdef CONFIG_DWC2_ULPI_FS_LS 94 uint32_t hwcfg2 = readl(®s->ghwcfg2); 95 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 96 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 97 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 98 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 99 100 if (hval == 2 && fval == 1) 101 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 102 #endif 103 104 clrsetbits_le32(®s->host_regs.hcfg, 105 DWC2_HCFG_FSLSPCLKSEL_MASK, 106 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); 107 } 108 109 /* 110 * Flush a Tx FIFO. 111 * 112 * @param regs Programming view of DWC_otg controller. 113 * @param num Tx FIFO to flush. 114 */ 115 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) 116 { 117 int ret; 118 119 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), 120 ®s->grstctl); 121 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 122 false, 1000, false); 123 if (ret) 124 dev_info(dev, "%s: Timeout!\n", __func__); 125 126 /* Wait for 3 PHY Clocks */ 127 udelay(1); 128 } 129 130 /* 131 * Flush Rx FIFO. 132 * 133 * @param regs Programming view of DWC_otg controller. 134 */ 135 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) 136 { 137 int ret; 138 139 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); 140 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 141 false, 1000, false); 142 if (ret) 143 dev_info(dev, "%s: Timeout!\n", __func__); 144 145 /* Wait for 3 PHY Clocks */ 146 udelay(1); 147 } 148 149 /* 150 * Do core a soft reset of the core. Be careful with this because it 151 * resets all the internal state machines of the core. 152 */ 153 static void dwc_otg_core_reset(struct dwc2_core_regs *regs) 154 { 155 int ret; 156 157 /* Wait for AHB master IDLE state. */ 158 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 159 true, 1000, false); 160 if (ret) 161 dev_info(dev, "%s: Timeout!\n", __func__); 162 163 /* Core Soft Reset */ 164 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); 165 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 166 false, 1000, false); 167 if (ret) 168 dev_info(dev, "%s: Timeout!\n", __func__); 169 170 /* 171 * Wait for core to come out of reset. 172 * NOTE: This long sleep is _very_ important, otherwise the core will 173 * not stay in host mode after a connector ID change! 174 */ 175 mdelay(100); 176 } 177 178 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR) 179 static int dwc_vbus_supply_init(struct udevice *dev) 180 { 181 struct dwc2_priv *priv = dev_get_priv(dev); 182 int ret; 183 184 ret = device_get_supply_regulator(dev, "vbus-supply", 185 &priv->vbus_supply); 186 if (ret) { 187 debug("%s: No vbus supply\n", dev->name); 188 return 0; 189 } 190 191 ret = regulator_set_enable(priv->vbus_supply, true); 192 if (ret) { 193 dev_err(dev, "Error enabling vbus supply\n"); 194 return ret; 195 } 196 197 return 0; 198 } 199 200 static int dwc_vbus_supply_exit(struct udevice *dev) 201 { 202 struct dwc2_priv *priv = dev_get_priv(dev); 203 int ret; 204 205 if (priv->vbus_supply) { 206 ret = regulator_set_enable(priv->vbus_supply, false); 207 if (ret) { 208 dev_err(dev, "Error disabling vbus supply\n"); 209 return ret; 210 } 211 } 212 213 return 0; 214 } 215 #else 216 static int dwc_vbus_supply_init(struct udevice *dev) 217 { 218 return 0; 219 } 220 221 #if CONFIG_IS_ENABLED(DM_USB) 222 static int dwc_vbus_supply_exit(struct udevice *dev) 223 { 224 return 0; 225 } 226 #endif 227 #endif 228 229 /* 230 * This function initializes the DWC_otg controller registers for 231 * host mode. 232 * 233 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the 234 * request queues. Host channels are reset to ensure that they are ready for 235 * performing transfers. 236 * 237 * @param dev USB Device (NULL if driver model is not being used) 238 * @param regs Programming view of DWC_otg controller 239 * 240 */ 241 static void dwc_otg_core_host_init(struct udevice *dev, 242 struct dwc2_core_regs *regs) 243 { 244 uint32_t nptxfifosize = 0; 245 uint32_t ptxfifosize = 0; 246 uint32_t hprt0 = 0; 247 int i, ret, num_channels; 248 249 /* Restart the Phy Clock */ 250 writel(0, ®s->pcgcctl); 251 252 /* Initialize Host Configuration Register */ 253 init_fslspclksel(regs); 254 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL 255 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); 256 #endif 257 258 /* Configure data FIFO sizes */ 259 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO 260 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { 261 /* Rx FIFO */ 262 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); 263 264 /* Non-periodic Tx FIFO */ 265 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << 266 DWC2_FIFOSIZE_DEPTH_OFFSET; 267 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << 268 DWC2_FIFOSIZE_STARTADDR_OFFSET; 269 writel(nptxfifosize, ®s->gnptxfsiz); 270 271 /* Periodic Tx FIFO */ 272 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << 273 DWC2_FIFOSIZE_DEPTH_OFFSET; 274 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + 275 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << 276 DWC2_FIFOSIZE_STARTADDR_OFFSET; 277 writel(ptxfifosize, ®s->hptxfsiz); 278 } 279 #endif 280 281 /* Clear Host Set HNP Enable in the OTG Control Register */ 282 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); 283 284 /* Make sure the FIFOs are flushed. */ 285 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ 286 dwc_otg_flush_rx_fifo(regs); 287 288 /* Flush out any leftover queued requests. */ 289 num_channels = readl(®s->ghwcfg2); 290 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; 291 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; 292 num_channels += 1; 293 294 for (i = 0; i < num_channels; i++) 295 clrsetbits_le32(®s->hc_regs[i].hcchar, 296 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, 297 DWC2_HCCHAR_CHDIS); 298 299 /* Halt all channels to put them into a known state. */ 300 for (i = 0; i < num_channels; i++) { 301 clrsetbits_le32(®s->hc_regs[i].hcchar, 302 DWC2_HCCHAR_EPDIR, 303 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); 304 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar, 305 DWC2_HCCHAR_CHEN, false, 1000, false); 306 if (ret) 307 dev_info("%s: Timeout!\n", __func__); 308 } 309 310 /* Turn on the vbus power. */ 311 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { 312 hprt0 = readl(®s->hprt0); 313 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); 314 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); 315 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { 316 hprt0 |= DWC2_HPRT0_PRTPWR; 317 writel(hprt0, ®s->hprt0); 318 } 319 } 320 321 if (dev) 322 dwc_vbus_supply_init(dev); 323 } 324 325 /* 326 * This function initializes the DWC_otg controller registers and 327 * prepares the core for device mode or host mode operation. 328 * 329 * @param regs Programming view of the DWC_otg controller 330 */ 331 static void dwc_otg_core_init(struct dwc2_priv *priv) 332 { 333 struct dwc2_core_regs *regs = priv->regs; 334 uint32_t ahbcfg = 0; 335 uint32_t usbcfg = 0; 336 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; 337 338 /* Common Initialization */ 339 usbcfg = readl(®s->gusbcfg); 340 341 /* Program the ULPI External VBUS bit if needed */ 342 if (priv->ext_vbus) { 343 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 344 if (!priv->oc_disable) { 345 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR | 346 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH; 347 } 348 } else { 349 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 350 } 351 352 /* Set external TS Dline pulsing */ 353 #ifdef CONFIG_DWC2_TS_DLINE 354 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 355 #else 356 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 357 #endif 358 writel(usbcfg, ®s->gusbcfg); 359 360 /* Reset the Controller */ 361 dwc_otg_core_reset(regs); 362 363 /* 364 * This programming sequence needs to happen in FS mode before 365 * any other programming occurs 366 */ 367 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ 368 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 369 /* If FS mode with FS PHY */ 370 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); 371 372 /* Reset after a PHY select */ 373 dwc_otg_core_reset(regs); 374 375 /* 376 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. 377 * Also do this on HNP Dev/Host mode switches (done in dev_init 378 * and host_init). 379 */ 380 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 381 init_fslspclksel(regs); 382 383 #ifdef CONFIG_DWC2_I2C_ENABLE 384 /* Program GUSBCFG.OtgUtmifsSel to I2C */ 385 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); 386 387 /* Program GI2CCTL.I2CEn */ 388 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | 389 DWC2_GI2CCTL_I2CDEVADDR_MASK, 390 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); 391 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); 392 #endif 393 394 #else 395 /* High speed PHY. */ 396 397 /* 398 * HS PHY parameters. These parameters are preserved during 399 * soft reset so only program the first time. Do a soft reset 400 * immediately after setting phyif. 401 */ 402 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); 403 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; 404 405 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ 406 #ifdef CONFIG_DWC2_PHY_ULPI_DDR 407 usbcfg |= DWC2_GUSBCFG_DDRSEL; 408 #else 409 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; 410 #endif 411 } else { /* UTMI+ interface */ 412 #if (CONFIG_DWC2_UTMI_WIDTH == 16) 413 usbcfg |= DWC2_GUSBCFG_PHYIF; 414 #endif 415 } 416 417 writel(usbcfg, ®s->gusbcfg); 418 419 /* Reset after setting the PHY parameters */ 420 dwc_otg_core_reset(regs); 421 #endif 422 423 usbcfg = readl(®s->gusbcfg); 424 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); 425 #ifdef CONFIG_DWC2_ULPI_FS_LS 426 uint32_t hwcfg2 = readl(®s->ghwcfg2); 427 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 428 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 429 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 430 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 431 if (hval == 2 && fval == 1) { 432 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; 433 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; 434 } 435 #endif 436 if (priv->hnp_srp_disable) 437 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE; 438 439 writel(usbcfg, ®s->gusbcfg); 440 441 /* Program the GAHBCFG Register. */ 442 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { 443 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: 444 break; 445 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: 446 while (brst_sz > 1) { 447 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); 448 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; 449 brst_sz >>= 1; 450 } 451 452 #ifdef CONFIG_DWC2_DMA_ENABLE 453 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 454 #endif 455 break; 456 457 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: 458 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; 459 #ifdef CONFIG_DWC2_DMA_ENABLE 460 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 461 #endif 462 break; 463 } 464 465 writel(ahbcfg, ®s->gahbcfg); 466 467 /* Program the capabilities in GUSBCFG Register */ 468 usbcfg = 0; 469 470 if (!priv->hnp_srp_disable) 471 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; 472 #ifdef CONFIG_DWC2_IC_USB_CAP 473 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; 474 #endif 475 476 setbits_le32(®s->gusbcfg, usbcfg); 477 } 478 479 /* 480 * Prepares a host channel for transferring packets to/from a specific 481 * endpoint. The HCCHARn register is set up with the characteristics specified 482 * in _hc. Host channel interrupts that may need to be serviced while this 483 * transfer is in progress are enabled. 484 * 485 * @param regs Programming view of DWC_otg controller 486 * @param hc Information needed to initialize the host channel 487 */ 488 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, 489 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, 490 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) 491 { 492 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; 493 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | 494 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | 495 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | 496 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | 497 (max_packet << DWC2_HCCHAR_MPS_OFFSET); 498 499 if (dev->speed == USB_SPEED_LOW) 500 hcchar |= DWC2_HCCHAR_LSPDDEV; 501 502 /* 503 * Program the HCCHARn register with the endpoint characteristics 504 * for the current transfer. 505 */ 506 writel(hcchar, &hc_regs->hcchar); 507 508 /* Program the HCSPLIT register, default to no SPLIT */ 509 writel(0, &hc_regs->hcsplt); 510 } 511 512 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs, 513 uint8_t hub_devnum, uint8_t hub_port) 514 { 515 uint32_t hcsplt = 0; 516 517 hcsplt = DWC2_HCSPLT_SPLTENA; 518 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET; 519 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET; 520 521 /* Program the HCSPLIT register for SPLITs */ 522 writel(hcsplt, &hc_regs->hcsplt); 523 } 524 525 /* 526 * DWC2 to USB API interface 527 */ 528 /* Direction: In ; Request: Status */ 529 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, 530 struct usb_device *dev, void *buffer, 531 int txlen, struct devrequest *cmd) 532 { 533 uint32_t hprt0 = 0; 534 uint32_t port_status = 0; 535 uint32_t port_change = 0; 536 int len = 0; 537 int stat = 0; 538 539 switch (cmd->requesttype & ~USB_DIR_IN) { 540 case 0: 541 *(uint16_t *)buffer = cpu_to_le16(1); 542 len = 2; 543 break; 544 case USB_RECIP_INTERFACE: 545 case USB_RECIP_ENDPOINT: 546 *(uint16_t *)buffer = cpu_to_le16(0); 547 len = 2; 548 break; 549 case USB_TYPE_CLASS: 550 *(uint32_t *)buffer = cpu_to_le32(0); 551 len = 4; 552 break; 553 case USB_RECIP_OTHER | USB_TYPE_CLASS: 554 hprt0 = readl(®s->hprt0); 555 if (hprt0 & DWC2_HPRT0_PRTCONNSTS) 556 port_status |= USB_PORT_STAT_CONNECTION; 557 if (hprt0 & DWC2_HPRT0_PRTENA) 558 port_status |= USB_PORT_STAT_ENABLE; 559 if (hprt0 & DWC2_HPRT0_PRTSUSP) 560 port_status |= USB_PORT_STAT_SUSPEND; 561 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) 562 port_status |= USB_PORT_STAT_OVERCURRENT; 563 if (hprt0 & DWC2_HPRT0_PRTRST) 564 port_status |= USB_PORT_STAT_RESET; 565 if (hprt0 & DWC2_HPRT0_PRTPWR) 566 port_status |= USB_PORT_STAT_POWER; 567 568 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) 569 port_status |= USB_PORT_STAT_LOW_SPEED; 570 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 571 DWC2_HPRT0_PRTSPD_HIGH) 572 port_status |= USB_PORT_STAT_HIGH_SPEED; 573 574 if (hprt0 & DWC2_HPRT0_PRTENCHNG) 575 port_change |= USB_PORT_STAT_C_ENABLE; 576 if (hprt0 & DWC2_HPRT0_PRTCONNDET) 577 port_change |= USB_PORT_STAT_C_CONNECTION; 578 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) 579 port_change |= USB_PORT_STAT_C_OVERCURRENT; 580 581 *(uint32_t *)buffer = cpu_to_le32(port_status | 582 (port_change << 16)); 583 len = 4; 584 break; 585 default: 586 puts("unsupported root hub command\n"); 587 stat = USB_ST_STALLED; 588 } 589 590 dev->act_len = min(len, txlen); 591 dev->status = stat; 592 593 return stat; 594 } 595 596 /* Direction: In ; Request: Descriptor */ 597 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, 598 void *buffer, int txlen, 599 struct devrequest *cmd) 600 { 601 unsigned char data[32]; 602 uint32_t dsc; 603 int len = 0; 604 int stat = 0; 605 uint16_t wValue = cpu_to_le16(cmd->value); 606 uint16_t wLength = cpu_to_le16(cmd->length); 607 608 switch (cmd->requesttype & ~USB_DIR_IN) { 609 case 0: 610 switch (wValue & 0xff00) { 611 case 0x0100: /* device descriptor */ 612 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); 613 memcpy(buffer, root_hub_dev_des, len); 614 break; 615 case 0x0200: /* configuration descriptor */ 616 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); 617 memcpy(buffer, root_hub_config_des, len); 618 break; 619 case 0x0300: /* string descriptors */ 620 switch (wValue & 0xff) { 621 case 0x00: 622 len = min3(txlen, (int)sizeof(root_hub_str_index0), 623 (int)wLength); 624 memcpy(buffer, root_hub_str_index0, len); 625 break; 626 case 0x01: 627 len = min3(txlen, (int)sizeof(root_hub_str_index1), 628 (int)wLength); 629 memcpy(buffer, root_hub_str_index1, len); 630 break; 631 } 632 break; 633 default: 634 stat = USB_ST_STALLED; 635 } 636 break; 637 638 case USB_TYPE_CLASS: 639 /* Root port config, set 1 port and nothing else. */ 640 dsc = 0x00000001; 641 642 data[0] = 9; /* min length; */ 643 data[1] = 0x29; 644 data[2] = dsc & RH_A_NDP; 645 data[3] = 0; 646 if (dsc & RH_A_PSM) 647 data[3] |= 0x1; 648 if (dsc & RH_A_NOCP) 649 data[3] |= 0x10; 650 else if (dsc & RH_A_OCPM) 651 data[3] |= 0x8; 652 653 /* corresponds to data[4-7] */ 654 data[5] = (dsc & RH_A_POTPGT) >> 24; 655 data[7] = dsc & RH_B_DR; 656 if (data[2] < 7) { 657 data[8] = 0xff; 658 } else { 659 data[0] += 2; 660 data[8] = (dsc & RH_B_DR) >> 8; 661 data[9] = 0xff; 662 data[10] = data[9]; 663 } 664 665 len = min3(txlen, (int)data[0], (int)wLength); 666 memcpy(buffer, data, len); 667 break; 668 default: 669 puts("unsupported root hub command\n"); 670 stat = USB_ST_STALLED; 671 } 672 673 dev->act_len = min(len, txlen); 674 dev->status = stat; 675 676 return stat; 677 } 678 679 /* Direction: In ; Request: Configuration */ 680 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, 681 void *buffer, int txlen, 682 struct devrequest *cmd) 683 { 684 int len = 0; 685 int stat = 0; 686 687 switch (cmd->requesttype & ~USB_DIR_IN) { 688 case 0: 689 *(uint8_t *)buffer = 0x01; 690 len = 1; 691 break; 692 default: 693 puts("unsupported root hub command\n"); 694 stat = USB_ST_STALLED; 695 } 696 697 dev->act_len = min(len, txlen); 698 dev->status = stat; 699 700 return stat; 701 } 702 703 /* Direction: In */ 704 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, 705 struct usb_device *dev, void *buffer, 706 int txlen, struct devrequest *cmd) 707 { 708 switch (cmd->request) { 709 case USB_REQ_GET_STATUS: 710 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, 711 txlen, cmd); 712 case USB_REQ_GET_DESCRIPTOR: 713 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, 714 txlen, cmd); 715 case USB_REQ_GET_CONFIGURATION: 716 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, 717 txlen, cmd); 718 default: 719 puts("unsupported root hub command\n"); 720 return USB_ST_STALLED; 721 } 722 } 723 724 /* Direction: Out */ 725 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, 726 struct usb_device *dev, 727 void *buffer, int txlen, 728 struct devrequest *cmd) 729 { 730 struct dwc2_core_regs *regs = priv->regs; 731 int len = 0; 732 int stat = 0; 733 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); 734 uint16_t wValue = cpu_to_le16(cmd->value); 735 736 switch (bmrtype_breq & ~USB_DIR_IN) { 737 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: 738 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: 739 break; 740 741 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 742 switch (wValue) { 743 case USB_PORT_FEAT_C_CONNECTION: 744 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); 745 break; 746 } 747 break; 748 749 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 750 switch (wValue) { 751 case USB_PORT_FEAT_SUSPEND: 752 break; 753 754 case USB_PORT_FEAT_RESET: 755 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 756 DWC2_HPRT0_PRTCONNDET | 757 DWC2_HPRT0_PRTENCHNG | 758 DWC2_HPRT0_PRTOVRCURRCHNG, 759 DWC2_HPRT0_PRTRST); 760 mdelay(50); 761 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); 762 break; 763 764 case USB_PORT_FEAT_POWER: 765 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 766 DWC2_HPRT0_PRTCONNDET | 767 DWC2_HPRT0_PRTENCHNG | 768 DWC2_HPRT0_PRTOVRCURRCHNG, 769 DWC2_HPRT0_PRTRST); 770 break; 771 772 case USB_PORT_FEAT_ENABLE: 773 break; 774 } 775 break; 776 case (USB_REQ_SET_ADDRESS << 8): 777 priv->root_hub_devnum = wValue; 778 break; 779 case (USB_REQ_SET_CONFIGURATION << 8): 780 break; 781 default: 782 puts("unsupported root hub command\n"); 783 stat = USB_ST_STALLED; 784 } 785 786 len = min(len, txlen); 787 788 dev->act_len = len; 789 dev->status = stat; 790 791 return stat; 792 } 793 794 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, 795 unsigned long pipe, void *buffer, int txlen, 796 struct devrequest *cmd) 797 { 798 int stat = 0; 799 800 if (usb_pipeint(pipe)) { 801 puts("Root-Hub submit IRQ: NOT implemented\n"); 802 return 0; 803 } 804 805 if (cmd->requesttype & USB_DIR_IN) 806 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); 807 else 808 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); 809 810 mdelay(1); 811 812 return stat; 813 } 814 815 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle) 816 { 817 int ret; 818 uint32_t hcint, hctsiz; 819 820 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true, 821 2000, false); 822 if (ret) 823 return ret; 824 825 hcint = readl(&hc_regs->hcint); 826 hctsiz = readl(&hc_regs->hctsiz); 827 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> 828 DWC2_HCTSIZ_XFERSIZE_OFFSET; 829 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; 830 831 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, 832 *toggle); 833 834 if (hcint & DWC2_HCINT_XFERCOMP) 835 return 0; 836 837 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) 838 return -EAGAIN; 839 840 debug("%s: Error (HCINT=%08x)\n", __func__, hcint); 841 return -EINVAL; 842 } 843 844 static int dwc2_eptype[] = { 845 DWC2_HCCHAR_EPTYPE_ISOC, 846 DWC2_HCCHAR_EPTYPE_INTR, 847 DWC2_HCCHAR_EPTYPE_CONTROL, 848 DWC2_HCCHAR_EPTYPE_BULK, 849 }; 850 851 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, 852 u8 *pid, int in, void *buffer, int num_packets, 853 int xfer_len, int *actual_len, int odd_frame) 854 { 855 int ret = 0; 856 uint32_t sub; 857 858 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, 859 *pid, xfer_len, num_packets); 860 861 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | 862 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | 863 (*pid << DWC2_HCTSIZ_PID_OFFSET), 864 &hc_regs->hctsiz); 865 866 if (xfer_len) { 867 if (in) { 868 invalidate_dcache_range( 869 (uintptr_t)aligned_buffer, 870 (uintptr_t)aligned_buffer + 871 roundup(xfer_len, ARCH_DMA_MINALIGN)); 872 } else { 873 memcpy(aligned_buffer, buffer, xfer_len); 874 flush_dcache_range( 875 (uintptr_t)aligned_buffer, 876 (uintptr_t)aligned_buffer + 877 roundup(xfer_len, ARCH_DMA_MINALIGN)); 878 } 879 } 880 881 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); 882 883 /* Clear old interrupt conditions for this host channel. */ 884 writel(0x3fff, &hc_regs->hcint); 885 886 /* Set host channel enable after all other setup is complete. */ 887 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | 888 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS | 889 DWC2_HCCHAR_ODDFRM, 890 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | 891 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) | 892 DWC2_HCCHAR_CHEN); 893 894 ret = wait_for_chhltd(hc_regs, &sub, pid); 895 if (ret < 0) 896 return ret; 897 898 if (in) { 899 xfer_len -= sub; 900 901 invalidate_dcache_range((unsigned long)aligned_buffer, 902 (unsigned long)aligned_buffer + 903 roundup(xfer_len, ARCH_DMA_MINALIGN)); 904 905 memcpy(buffer, aligned_buffer, xfer_len); 906 } 907 *actual_len = xfer_len; 908 909 return ret; 910 } 911 912 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, 913 unsigned long pipe, u8 *pid, int in, void *buffer, int len) 914 { 915 struct dwc2_core_regs *regs = priv->regs; 916 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 917 struct dwc2_host_regs *host_regs = ®s->host_regs; 918 int devnum = usb_pipedevice(pipe); 919 int ep = usb_pipeendpoint(pipe); 920 int max = usb_maxpacket(dev, pipe); 921 int eptype = dwc2_eptype[usb_pipetype(pipe)]; 922 int done = 0; 923 int ret = 0; 924 int do_split = 0; 925 int complete_split = 0; 926 uint32_t xfer_len; 927 uint32_t num_packets; 928 int stop_transfer = 0; 929 uint32_t max_xfer_len; 930 int ssplit_frame_num = 0; 931 932 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, 933 in, len); 934 935 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; 936 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) 937 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; 938 if (max_xfer_len > DWC2_DATA_BUF_SIZE) 939 max_xfer_len = DWC2_DATA_BUF_SIZE; 940 941 /* Make sure that max_xfer_len is a multiple of max packet size. */ 942 num_packets = max_xfer_len / max; 943 max_xfer_len = num_packets * max; 944 945 /* Initialize channel */ 946 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, 947 eptype, max); 948 949 /* Check if the target is a FS/LS device behind a HS hub */ 950 if (dev->speed != USB_SPEED_HIGH) { 951 uint8_t hub_addr; 952 uint8_t hub_port; 953 uint32_t hprt0 = readl(®s->hprt0); 954 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 955 DWC2_HPRT0_PRTSPD_HIGH) { 956 usb_find_usb2_hub_address_port(dev, &hub_addr, 957 &hub_port); 958 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port); 959 960 do_split = 1; 961 num_packets = 1; 962 max_xfer_len = max; 963 } 964 } 965 966 do { 967 int actual_len = 0; 968 uint32_t hcint; 969 int odd_frame = 0; 970 xfer_len = len - done; 971 972 if (xfer_len > max_xfer_len) 973 xfer_len = max_xfer_len; 974 else if (xfer_len > max) 975 num_packets = (xfer_len + max - 1) / max; 976 else 977 num_packets = 1; 978 979 if (complete_split) 980 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 981 else if (do_split) 982 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 983 984 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) { 985 int uframe_num = readl(&host_regs->hfnum); 986 if (!(uframe_num & 0x1)) 987 odd_frame = 1; 988 } 989 990 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, 991 in, (char *)buffer + done, num_packets, 992 xfer_len, &actual_len, odd_frame); 993 994 hcint = readl(&hc_regs->hcint); 995 if (complete_split) { 996 stop_transfer = 0; 997 if (hcint & DWC2_HCINT_NYET) { 998 ret = 0; 999 int frame_num = DWC2_HFNUM_MAX_FRNUM & 1000 readl(&host_regs->hfnum); 1001 if (((frame_num - ssplit_frame_num) & 1002 DWC2_HFNUM_MAX_FRNUM) > 4) 1003 ret = -EAGAIN; 1004 } else 1005 complete_split = 0; 1006 } else if (do_split) { 1007 if (hcint & DWC2_HCINT_ACK) { 1008 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM & 1009 readl(&host_regs->hfnum); 1010 ret = 0; 1011 complete_split = 1; 1012 } 1013 } 1014 1015 if (ret) 1016 break; 1017 1018 if (actual_len < xfer_len) 1019 stop_transfer = 1; 1020 1021 done += actual_len; 1022 1023 /* Transactions are done when when either all data is transferred or 1024 * there is a short transfer. In case of a SPLIT make sure the CSPLIT 1025 * is executed. 1026 */ 1027 } while (((done < len) && !stop_transfer) || complete_split); 1028 1029 writel(0, &hc_regs->hcintmsk); 1030 writel(0xFFFFFFFF, &hc_regs->hcint); 1031 1032 dev->status = 0; 1033 dev->act_len = done; 1034 1035 return ret; 1036 } 1037 1038 /* U-Boot USB transmission interface */ 1039 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, 1040 unsigned long pipe, void *buffer, int len) 1041 { 1042 int devnum = usb_pipedevice(pipe); 1043 int ep = usb_pipeendpoint(pipe); 1044 u8* pid; 1045 1046 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) { 1047 dev->status = 0; 1048 return -EINVAL; 1049 } 1050 1051 if (usb_pipein(pipe)) 1052 pid = &priv->in_data_toggle[devnum][ep]; 1053 else 1054 pid = &priv->out_data_toggle[devnum][ep]; 1055 1056 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len); 1057 } 1058 1059 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, 1060 unsigned long pipe, void *buffer, int len, 1061 struct devrequest *setup) 1062 { 1063 int devnum = usb_pipedevice(pipe); 1064 int ret, act_len; 1065 u8 pid; 1066 /* For CONTROL endpoint pid should start with DATA1 */ 1067 int status_direction; 1068 1069 if (devnum == priv->root_hub_devnum) { 1070 dev->status = 0; 1071 dev->speed = USB_SPEED_HIGH; 1072 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, 1073 setup); 1074 } 1075 1076 /* SETUP stage */ 1077 pid = DWC2_HC_PID_SETUP; 1078 do { 1079 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8); 1080 } while (ret == -EAGAIN); 1081 if (ret) 1082 return ret; 1083 1084 /* DATA stage */ 1085 act_len = 0; 1086 if (buffer) { 1087 pid = DWC2_HC_PID_DATA1; 1088 do { 1089 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), 1090 buffer, len); 1091 act_len += dev->act_len; 1092 buffer += dev->act_len; 1093 len -= dev->act_len; 1094 } while (ret == -EAGAIN); 1095 if (ret) 1096 return ret; 1097 status_direction = usb_pipeout(pipe); 1098 } else { 1099 /* No-data CONTROL always ends with an IN transaction */ 1100 status_direction = 1; 1101 } 1102 1103 /* STATUS stage */ 1104 pid = DWC2_HC_PID_DATA1; 1105 do { 1106 ret = chunk_msg(priv, dev, pipe, &pid, status_direction, 1107 priv->status_buffer, 0); 1108 } while (ret == -EAGAIN); 1109 if (ret) 1110 return ret; 1111 1112 dev->act_len = act_len; 1113 1114 return 0; 1115 } 1116 1117 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, 1118 unsigned long pipe, void *buffer, int len, int interval, 1119 bool nonblock) 1120 { 1121 unsigned long timeout; 1122 int ret; 1123 1124 /* FIXME: what is interval? */ 1125 1126 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1127 for (;;) { 1128 if (get_timer(0) > timeout) { 1129 dev_err(dev, "Timeout poll on interrupt endpoint\n"); 1130 return -ETIMEDOUT; 1131 } 1132 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); 1133 if ((ret != -EAGAIN) || nonblock) 1134 return ret; 1135 } 1136 } 1137 1138 static int dwc2_reset(struct udevice *dev) 1139 { 1140 int ret; 1141 struct dwc2_priv *priv = dev_get_priv(dev); 1142 1143 ret = reset_get_bulk(dev, &priv->resets); 1144 if (ret) { 1145 dev_warn(dev, "Can't get reset: %d\n", ret); 1146 /* Return 0 if error due to !CONFIG_DM_RESET and reset 1147 * DT property is not present. 1148 */ 1149 if (ret == -ENOENT || ret == -ENOTSUPP) 1150 return 0; 1151 else 1152 return ret; 1153 } 1154 1155 /* force reset to clear all IP register */ 1156 reset_assert_bulk(&priv->resets); 1157 ret = reset_deassert_bulk(&priv->resets); 1158 if (ret) { 1159 reset_release_bulk(&priv->resets); 1160 dev_err(dev, "Failed to reset: %d\n", ret); 1161 return ret; 1162 } 1163 1164 return 0; 1165 } 1166 1167 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) 1168 { 1169 struct dwc2_core_regs *regs = priv->regs; 1170 uint32_t snpsid; 1171 int i, j; 1172 int ret; 1173 1174 ret = dwc2_reset(dev); 1175 if (ret) 1176 return ret; 1177 1178 snpsid = readl(®s->gsnpsid); 1179 dev_info(dev, "Core Release: %x.%03x\n", 1180 snpsid >> 12 & 0xf, snpsid & 0xfff); 1181 1182 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && 1183 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { 1184 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n", 1185 snpsid); 1186 return -ENODEV; 1187 } 1188 1189 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS 1190 priv->ext_vbus = 1; 1191 #else 1192 priv->ext_vbus = 0; 1193 #endif 1194 1195 dwc_otg_core_init(priv); 1196 dwc_otg_core_host_init(dev, regs); 1197 1198 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1199 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1200 DWC2_HPRT0_PRTOVRCURRCHNG, 1201 DWC2_HPRT0_PRTRST); 1202 mdelay(50); 1203 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | 1204 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | 1205 DWC2_HPRT0_PRTRST); 1206 1207 for (i = 0; i < MAX_DEVICE; i++) { 1208 for (j = 0; j < MAX_ENDPOINT; j++) { 1209 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1210 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1211 } 1212 } 1213 1214 /* 1215 * Add a 1 second delay here. This gives the host controller 1216 * a bit time before the comminucation with the USB devices 1217 * is started (the bus is scanned) and fixes the USB detection 1218 * problems with some problematic USB keys. 1219 */ 1220 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 1221 mdelay(1000); 1222 1223 printf("USB DWC2\n"); 1224 1225 return 0; 1226 } 1227 1228 static void dwc2_uninit_common(struct dwc2_core_regs *regs) 1229 { 1230 /* Put everything in reset. */ 1231 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1232 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1233 DWC2_HPRT0_PRTOVRCURRCHNG, 1234 DWC2_HPRT0_PRTRST); 1235 } 1236 1237 #if !CONFIG_IS_ENABLED(DM_USB) 1238 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1239 int len, struct devrequest *setup) 1240 { 1241 return _submit_control_msg(&local, dev, pipe, buffer, len, setup); 1242 } 1243 1244 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1245 int len) 1246 { 1247 return _submit_bulk_msg(&local, dev, pipe, buffer, len); 1248 } 1249 1250 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1251 int len, int interval, bool nonblock) 1252 { 1253 return _submit_int_msg(&local, dev, pipe, buffer, len, interval, 1254 nonblock); 1255 } 1256 1257 /* U-Boot USB control interface */ 1258 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1259 { 1260 struct dwc2_priv *priv = &local; 1261 1262 memset(priv, '\0', sizeof(*priv)); 1263 priv->root_hub_devnum = 0; 1264 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; 1265 priv->aligned_buffer = aligned_buffer_addr; 1266 priv->status_buffer = status_buffer_addr; 1267 1268 /* board-dependant init */ 1269 if (board_usb_init(index, USB_INIT_HOST)) 1270 return -1; 1271 1272 return dwc2_init_common(NULL, priv); 1273 } 1274 1275 int usb_lowlevel_stop(int index) 1276 { 1277 dwc2_uninit_common(local.regs); 1278 1279 return 0; 1280 } 1281 #endif 1282 1283 #if CONFIG_IS_ENABLED(DM_USB) 1284 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1285 unsigned long pipe, void *buffer, int length, 1286 struct devrequest *setup) 1287 { 1288 struct dwc2_priv *priv = dev_get_priv(dev); 1289 1290 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1291 dev->name, udev, udev->dev->name, udev->portnr); 1292 1293 return _submit_control_msg(priv, udev, pipe, buffer, length, setup); 1294 } 1295 1296 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1297 unsigned long pipe, void *buffer, int length) 1298 { 1299 struct dwc2_priv *priv = dev_get_priv(dev); 1300 1301 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1302 1303 return _submit_bulk_msg(priv, udev, pipe, buffer, length); 1304 } 1305 1306 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1307 unsigned long pipe, void *buffer, int length, 1308 int interval, bool nonblock) 1309 { 1310 struct dwc2_priv *priv = dev_get_priv(dev); 1311 1312 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1313 1314 return _submit_int_msg(priv, udev, pipe, buffer, length, interval, 1315 nonblock); 1316 } 1317 1318 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) 1319 { 1320 struct dwc2_priv *priv = dev_get_priv(dev); 1321 fdt_addr_t addr; 1322 1323 addr = dev_read_addr(dev); 1324 if (addr == FDT_ADDR_T_NONE) 1325 return -EINVAL; 1326 priv->regs = (struct dwc2_core_regs *)addr; 1327 1328 priv->oc_disable = dev_read_bool(dev, "disable-over-current"); 1329 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable"); 1330 1331 return 0; 1332 } 1333 1334 static int dwc2_setup_phy(struct udevice *dev) 1335 { 1336 struct dwc2_priv *priv = dev_get_priv(dev); 1337 int ret; 1338 1339 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 1340 if (ret) { 1341 if (ret == -ENOENT) 1342 return 0; /* no PHY, nothing to do */ 1343 dev_err(dev, "Failed to get USB PHY: %d.\n", ret); 1344 return ret; 1345 } 1346 1347 ret = generic_phy_init(&priv->phy); 1348 if (ret) { 1349 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret); 1350 return ret; 1351 } 1352 1353 ret = generic_phy_power_on(&priv->phy); 1354 if (ret) { 1355 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret); 1356 generic_phy_exit(&priv->phy); 1357 return ret; 1358 } 1359 1360 return 0; 1361 } 1362 1363 static int dwc2_shutdown_phy(struct udevice *dev) 1364 { 1365 struct dwc2_priv *priv = dev_get_priv(dev); 1366 int ret; 1367 1368 /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */ 1369 if (!generic_phy_valid(&priv->phy)) 1370 return 0; /* no PHY, nothing to do */ 1371 1372 ret = generic_phy_power_off(&priv->phy); 1373 if (ret) { 1374 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret); 1375 return ret; 1376 } 1377 1378 ret = generic_phy_exit(&priv->phy); 1379 if (ret) { 1380 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret); 1381 return ret; 1382 } 1383 1384 return 0; 1385 } 1386 1387 static int dwc2_clk_init(struct udevice *dev) 1388 { 1389 struct dwc2_priv *priv = dev_get_priv(dev); 1390 int ret; 1391 1392 ret = clk_get_bulk(dev, &priv->clks); 1393 if (ret == -ENOSYS || ret == -ENOENT) 1394 return 0; 1395 if (ret) 1396 return ret; 1397 1398 ret = clk_enable_bulk(&priv->clks); 1399 if (ret) { 1400 clk_release_bulk(&priv->clks); 1401 return ret; 1402 } 1403 1404 return 0; 1405 } 1406 1407 static int dwc2_usb_probe(struct udevice *dev) 1408 { 1409 struct dwc2_priv *priv = dev_get_priv(dev); 1410 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); 1411 int ret; 1412 1413 bus_priv->desc_before_addr = true; 1414 1415 #ifdef CONFIG_ARCH_ROCKCHIP 1416 priv->hnp_srp_disable = true; 1417 #endif 1418 1419 ret = dwc2_clk_init(dev); 1420 if (ret) 1421 return ret; 1422 1423 ret = dwc2_setup_phy(dev); 1424 if (ret) 1425 return ret; 1426 1427 return dwc2_init_common(dev, priv); 1428 } 1429 1430 static int dwc2_usb_remove(struct udevice *dev) 1431 { 1432 struct dwc2_priv *priv = dev_get_priv(dev); 1433 int ret; 1434 1435 ret = dwc_vbus_supply_exit(dev); 1436 if (ret) 1437 return ret; 1438 1439 ret = dwc2_shutdown_phy(dev); 1440 if (ret) { 1441 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret); 1442 return ret; 1443 } 1444 1445 dwc2_uninit_common(priv->regs); 1446 1447 reset_release_bulk(&priv->resets); 1448 clk_disable_bulk(&priv->clks); 1449 clk_release_bulk(&priv->clks); 1450 1451 return 0; 1452 } 1453 1454 struct dm_usb_ops dwc2_usb_ops = { 1455 .control = dwc2_submit_control_msg, 1456 .bulk = dwc2_submit_bulk_msg, 1457 .interrupt = dwc2_submit_int_msg, 1458 }; 1459 1460 static const struct udevice_id dwc2_usb_ids[] = { 1461 { .compatible = "brcm,bcm2835-usb" }, 1462 { .compatible = "brcm,bcm2708-usb" }, 1463 { .compatible = "snps,dwc2" }, 1464 { } 1465 }; 1466 1467 U_BOOT_DRIVER(usb_dwc2) = { 1468 .name = "dwc2_usb", 1469 .id = UCLASS_USB, 1470 .of_match = dwc2_usb_ids, 1471 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, 1472 .probe = dwc2_usb_probe, 1473 .remove = dwc2_usb_remove, 1474 .ops = &dwc2_usb_ops, 1475 .priv_auto_alloc_size = sizeof(struct dwc2_priv), 1476 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1477 }; 1478 #endif 1479